Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	100.00	100.00	100.00		100.00	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.31	100.00	85.94			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.31	100.00	85.94			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.31	100.00	85.94			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.31	100.00	85.94			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.31	100.00	85.94			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.31	100.00	85.94			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.31	100.00	85.94			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T37,T79

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T19
DataWait	75	Covered	T19
Disabled	107	Covered	T19
EndPointClear	63	Covered	T19
Error	99	Covered	T19
Idle	68	Covered	T19

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T19
AckPls->Error	99	Covered	T19
AckPls->Idle	85	Covered	T19
DataWait->AckPls	80	Covered	T19
DataWait->Disabled	107	Covered	T19
DataWait->Error	99	Covered	T19
Disabled->EndPointClear	63	Covered	T19
Disabled->Error	99	Covered	T19
EndPointClear->Disabled	107	Covered	T19
EndPointClear->Error	99	Covered	T19
EndPointClear->Idle	68	Covered	T19
Idle->DataWait	75	Covered	T19
Idle->Disabled	107	Covered	T19
Idle->Error	99	Covered	T19

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T32,T10
Idle	-	1	0	-	Covered	T1,T32,T10
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T32,T10
DataWait	-	-	-	0	Covered	T1,T32,T10
AckPls	-	-	-	-	Covered	T1,T32,T10
Error	-	-	-	-	Covered	T4,T14,T7
default	-	-	-	-	Covered	T4,T88,T89

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T7
0	1	Covered	T3,T37,T79
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1484227913	688715	0	0
FpvSecCmErrorStEscalate_A	1484227913	691480	0	0
u_state_regs_A	1484190175	1483413399	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1484227913	688715	0	0
T4	13244	8196	0	0
T5	3216052	0	0	0
T6	1021671	0	0	0
T7	0	2261	0	0
T8	0	2541	0	0
T11	12369	0	0	0
T14	0	7749	0	0
T16	12943	0	0	0
T37	5530	0	0	0
T38	8974	0	0	0
T40	8050	0	0	0
T45	14399	0	0	0
T68	94976	0	0	0
T70	0	1505	0	0
T71	0	4130	0	0
T73	0	2520	0	0
T74	0	4473	0	0
T75	0	2919	0	0
T88	0	3660	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1484227913	691480	0	0
T4	13244	8203	0	0
T5	3216052	0	0	0
T6	1021671	0	0	0
T7	0	2268	0	0
T8	0	2548	0	0
T11	12369	0	0	0
T14	0	7756	0	0
T16	12943	0	0	0
T37	5530	0	0	0
T38	8974	0	0	0
T40	8050	0	0	0
T45	14399	0	0	0
T68	94976	0	0	0
T70	0	1512	0	0
T71	0	4137	0	0
T73	0	2527	0	0
T74	0	4480	0	0
T75	0	2926	0	0
T88	0	3667	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1484190175	1483413399	0	0
T1	13349	12782	0	0
T2	33131	32522	0	0
T3	6895	6237	0	0
T4	13068	11990	0	0
T10	25557	25032	0	0
T32	7560	7105	0	0
T38	8974	8330	0	0
T39	10318	9646	0	0
T40	8050	7392	0	0
T46	11242	10619	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T37,T79

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T19
DataWait	75	Covered	T19
Disabled	107	Covered	T19
EndPointClear	63	Covered	T19
Error	99	Covered	T19
Idle	68	Covered	T19

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T19
DataWait->AckPls	80	Covered	T19
DataWait->Disabled	107	Covered	T19
DataWait->Error	99	Covered	T19
Disabled->EndPointClear	63	Covered	T19
Disabled->Error	99	Covered	T19
EndPointClear->Disabled	107	Covered	T19
EndPointClear->Error	99	Covered	T19
EndPointClear->Idle	68	Covered	T19
Idle->DataWait	75	Covered	T19
Idle->Disabled	107	Covered	T19
Idle->Error	99	Covered	T19

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T11,T33
Idle	-	1	0	-	Covered	T3,T11,T33
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T11,T33
DataWait	-	-	-	0	Covered	T3,T11,T33
AckPls	-	-	-	-	Covered	T3,T11,T33
Error	-	-	-	-	Covered	T4,T14,T7
default	-	-	-	-	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T7
0	1	Covered	T3,T37,T79
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	212032559	98695	0	0
FpvSecCmErrorStEscalate_A	212032559	99090	0	0
u_state_regs_A	212032559	211921591	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	98695	0	0
T4	1892	1178	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	323	0	0
T8	0	363	0	0
T11	1767	0	0	0
T14	0	1107	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	215	0	0
T71	0	590	0	0
T73	0	360	0	0
T74	0	639	0	0
T75	0	417	0	0
T88	0	530	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	99090	0	0
T4	1892	1179	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	324	0	0
T8	0	364	0	0
T11	1767	0	0	0
T14	0	1108	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	216	0	0
T71	0	591	0	0
T73	0	361	0	0
T74	0	640	0	0
T75	0	418	0	0
T88	0	531	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	211921591	0	0
T1	1907	1826	0	0
T2	4733	4646	0	0
T3	985	891	0	0
T4	1892	1738	0	0
T10	3651	3576	0	0
T32	1080	1015	0	0
T38	1282	1190	0	0
T39	1474	1378	0	0
T40	1150	1056	0	0
T46	1606	1517	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T37,T79

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T19
DataWait	75	Covered	T19
Disabled	107	Covered	T19
EndPointClear	63	Covered	T19
Error	99	Covered	T19
Idle	68	Covered	T19

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T19
AckPls->Idle	85	Covered	T19
DataWait->AckPls	80	Covered	T19
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Covered	T19
Disabled->EndPointClear	63	Covered	T19
Disabled->Error	99	Covered	T19
EndPointClear->Disabled	107	Covered	T19
EndPointClear->Error	99	Covered	T19
EndPointClear->Idle	68	Covered	T19
Idle->DataWait	75	Covered	T19
Idle->Disabled	107	Covered	T19
Idle->Error	99	Covered	T19

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T10,T37
Idle	-	1	0	-	Covered	T2,T10,T37
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T10,T37
DataWait	-	-	-	0	Covered	T2,T10,T37
AckPls	-	-	-	-	Covered	T2,T10,T37
Error	-	-	-	-	Covered	T4,T14,T7
default	-	-	-	-	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T7
0	1	Covered	T3,T37,T79
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	212032559	98695	0	0
FpvSecCmErrorStEscalate_A	212032559	99090	0	0
u_state_regs_A	212032559	211921591	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	98695	0	0
T4	1892	1178	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	323	0	0
T8	0	363	0	0
T11	1767	0	0	0
T14	0	1107	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	215	0	0
T71	0	590	0	0
T73	0	360	0	0
T74	0	639	0	0
T75	0	417	0	0
T88	0	530	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	99090	0	0
T4	1892	1179	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	324	0	0
T8	0	364	0	0
T11	1767	0	0	0
T14	0	1108	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	216	0	0
T71	0	591	0	0
T73	0	361	0	0
T74	0	640	0	0
T75	0	418	0	0
T88	0	531	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	211921591	0	0
T1	1907	1826	0	0
T2	4733	4646	0	0
T3	985	891	0	0
T4	1892	1738	0	0
T10	3651	3576	0	0
T32	1080	1015	0	0
T38	1282	1190	0	0
T39	1474	1378	0	0
T40	1150	1056	0	0
T46	1606	1517	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T37,T79

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T19
DataWait	75	Covered	T19
Disabled	107	Covered	T19
EndPointClear	63	Covered	T19
Error	99	Covered	T19
Idle	68	Covered	T19

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T19
DataWait->AckPls	80	Covered	T19
DataWait->Disabled	107	Covered	T19
DataWait->Error	99	Covered	T19
Disabled->EndPointClear	63	Covered	T19
Disabled->Error	99	Covered	T19
EndPointClear->Disabled	107	Covered	T19
EndPointClear->Error	99	Covered	T19
EndPointClear->Idle	68	Covered	T19
Idle->DataWait	75	Covered	T19
Idle->Disabled	107	Covered	T19
Idle->Error	99	Covered	T19

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T38,T11
Idle	-	1	0	-	Covered	T2,T38,T11
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T38,T11
DataWait	-	-	-	0	Covered	T2,T38,T11
AckPls	-	-	-	-	Covered	T2,T38,T11
Error	-	-	-	-	Covered	T4,T14,T7
default	-	-	-	-	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T7
0	1	Covered	T3,T37,T79
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	212032559	98695	0	0
FpvSecCmErrorStEscalate_A	212032559	99090	0	0
u_state_regs_A	212032559	211921591	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	98695	0	0
T4	1892	1178	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	323	0	0
T8	0	363	0	0
T11	1767	0	0	0
T14	0	1107	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	215	0	0
T71	0	590	0	0
T73	0	360	0	0
T74	0	639	0	0
T75	0	417	0	0
T88	0	530	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	99090	0	0
T4	1892	1179	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	324	0	0
T8	0	364	0	0
T11	1767	0	0	0
T14	0	1108	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	216	0	0
T71	0	591	0	0
T73	0	361	0	0
T74	0	640	0	0
T75	0	418	0	0
T88	0	531	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	211921591	0	0
T1	1907	1826	0	0
T2	4733	4646	0	0
T3	985	891	0	0
T4	1892	1738	0	0
T10	3651	3576	0	0
T32	1080	1015	0	0
T38	1282	1190	0	0
T39	1474	1378	0	0
T40	1150	1056	0	0
T46	1606	1517	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T37,T79

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T19
DataWait	75	Covered	T19
Disabled	107	Covered	T19
EndPointClear	63	Covered	T19
Error	99	Covered	T19
Idle	68	Covered	T19

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T19
AckPls->Idle	85	Covered	T19
DataWait->AckPls	80	Covered	T19
DataWait->Disabled	107	Covered	T19
DataWait->Error	99	Covered	T19
Disabled->EndPointClear	63	Covered	T19
Disabled->Error	99	Covered	T19
EndPointClear->Disabled	107	Covered	T19
EndPointClear->Error	99	Covered	T19
EndPointClear->Idle	68	Covered	T19
Idle->DataWait	75	Covered	T19
Idle->Disabled	107	Covered	T19
Idle->Error	99	Covered	T19

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T33,T34,T35
Idle	-	1	0	-	Covered	T33,T34,T35
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T33,T34,T35
DataWait	-	-	-	0	Covered	T33,T34,T35
AckPls	-	-	-	-	Covered	T33,T34,T35
Error	-	-	-	-	Covered	T4,T14,T7
default	-	-	-	-	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T7
0	1	Covered	T3,T37,T79
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	212032559	98695	0	0
FpvSecCmErrorStEscalate_A	212032559	99090	0	0
u_state_regs_A	212032559	211921591	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	98695	0	0
T4	1892	1178	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	323	0	0
T8	0	363	0	0
T11	1767	0	0	0
T14	0	1107	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	215	0	0
T71	0	590	0	0
T73	0	360	0	0
T74	0	639	0	0
T75	0	417	0	0
T88	0	530	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	99090	0	0
T4	1892	1179	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	324	0	0
T8	0	364	0	0
T11	1767	0	0	0
T14	0	1108	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	216	0	0
T71	0	591	0	0
T73	0	361	0	0
T74	0	640	0	0
T75	0	418	0	0
T88	0	531	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	211921591	0	0
T1	1907	1826	0	0
T2	4733	4646	0	0
T3	985	891	0	0
T4	1892	1738	0	0
T10	3651	3576	0	0
T32	1080	1015	0	0
T38	1282	1190	0	0
T39	1474	1378	0	0
T40	1150	1056	0	0
T46	1606	1517	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T37,T79

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T19
DataWait	75	Covered	T19
Disabled	107	Covered	T19
EndPointClear	63	Covered	T19
Error	99	Covered	T19
Idle	68	Covered	T19

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T19
AckPls->Idle	85	Covered	T19
DataWait->AckPls	80	Covered	T19
DataWait->Disabled	107	Covered	T19
DataWait->Error	99	Covered	T19
Disabled->EndPointClear	63	Covered	T19
Disabled->Error	99	Covered	T19
EndPointClear->Disabled	107	Covered	T19
EndPointClear->Error	99	Covered	T19
EndPointClear->Idle	68	Covered	T19
Idle->DataWait	75	Covered	T19
Idle->Disabled	107	Covered	T19
Idle->Error	99	Covered	T19

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T33,T35,T36
Idle	-	1	0	-	Covered	T33,T35,T36
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T33,T35,T36
DataWait	-	-	-	0	Covered	T33,T35,T36
AckPls	-	-	-	-	Covered	T33,T35,T36
Error	-	-	-	-	Covered	T4,T14,T7
default	-	-	-	-	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T7
0	1	Covered	T3,T37,T79
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	212032559	98695	0	0
FpvSecCmErrorStEscalate_A	212032559	99090	0	0
u_state_regs_A	212032559	211921591	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	98695	0	0
T4	1892	1178	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	323	0	0
T8	0	363	0	0
T11	1767	0	0	0
T14	0	1107	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	215	0	0
T71	0	590	0	0
T73	0	360	0	0
T74	0	639	0	0
T75	0	417	0	0
T88	0	530	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	99090	0	0
T4	1892	1179	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	324	0	0
T8	0	364	0	0
T11	1767	0	0	0
T14	0	1108	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	216	0	0
T71	0	591	0	0
T73	0	361	0	0
T74	0	640	0	0
T75	0	418	0	0
T88	0	531	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	211921591	0	0
T1	1907	1826	0	0
T2	4733	4646	0	0
T3	985	891	0	0
T4	1892	1738	0	0
T10	3651	3576	0	0
T32	1080	1015	0	0
T38	1282	1190	0	0
T39	1474	1378	0	0
T40	1150	1056	0	0
T46	1606	1517	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T37,T79

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T19
DataWait	75	Covered	T19
Disabled	107	Covered	T19
EndPointClear	63	Covered	T19
Error	99	Covered	T19
Idle	68	Covered	T19

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T19
AckPls->Idle	85	Covered	T19
DataWait->AckPls	80	Covered	T19
DataWait->Disabled	107	Covered	T19
DataWait->Error	99	Covered	T19
Disabled->EndPointClear	63	Covered	T19
Disabled->Error	99	Covered	T19
EndPointClear->Disabled	107	Covered	T19
EndPointClear->Error	99	Covered	T19
EndPointClear->Idle	68	Covered	T19
Idle->DataWait	75	Covered	T19
Idle->Disabled	107	Covered	T19
Idle->Error	99	Covered	T19

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T16,T11
Idle	-	1	0	-	Covered	T2,T16,T11
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T16,T11
DataWait	-	-	-	0	Covered	T2,T16,T11
AckPls	-	-	-	-	Covered	T2,T16,T11
Error	-	-	-	-	Covered	T4,T14,T7
default	-	-	-	-	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T7
0	1	Covered	T3,T37,T79
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	212032559	98695	0	0
FpvSecCmErrorStEscalate_A	212032559	99090	0	0
u_state_regs_A	212032559	211921591	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	98695	0	0
T4	1892	1178	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	323	0	0
T8	0	363	0	0
T11	1767	0	0	0
T14	0	1107	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	215	0	0
T71	0	590	0	0
T73	0	360	0	0
T74	0	639	0	0
T75	0	417	0	0
T88	0	530	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	99090	0	0
T4	1892	1179	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	324	0	0
T8	0	364	0	0
T11	1767	0	0	0
T14	0	1108	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	216	0	0
T71	0	591	0	0
T73	0	361	0	0
T74	0	640	0	0
T75	0	418	0	0
T88	0	531	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	211921591	0	0
T1	1907	1826	0	0
T2	4733	4646	0	0
T3	985	891	0	0
T4	1892	1738	0	0
T10	3651	3576	0	0
T32	1080	1015	0	0
T38	1282	1190	0	0
T39	1474	1378	0	0
T40	1150	1056	0	0
T46	1606	1517	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T37,T79

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T19
DataWait	75	Covered	T19
Disabled	107	Covered	T19
EndPointClear	63	Covered	T19
Error	99	Covered	T19
Idle	68	Covered	T19

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T19
AckPls->Error	99	Covered	T19
AckPls->Idle	85	Covered	T19
DataWait->AckPls	80	Covered	T19
DataWait->Disabled	107	Covered	T19
DataWait->Error	99	Covered	T19
Disabled->EndPointClear	63	Covered	T19
Disabled->Error	99	Covered	T19
EndPointClear->Disabled	107	Covered	T19
EndPointClear->Error	99	Covered	T19
EndPointClear->Idle	68	Covered	T19
Idle->DataWait	75	Covered	T19
Idle->Disabled	107	Covered	T19
Idle->Error	99	Covered	T19

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T32,T10
Idle	-	1	0	-	Covered	T1,T32,T10
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T32,T10
DataWait	-	-	-	0	Covered	T1,T32,T10
AckPls	-	-	-	-	Covered	T1,T32,T10
Error	-	-	-	-	Covered	T4,T14,T7
default	-	-	-	-	Covered	T4,T88,T89

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T7
0	1	Covered	T3,T37,T79
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	212032559	96545	0	0
FpvSecCmErrorStEscalate_A	212032559	96940	0	0
u_state_regs_A	211994821	211883853	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	96545	0	0
T4	1892	1128	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	323	0	0
T8	0	363	0	0
T11	1767	0	0	0
T14	0	1107	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	215	0	0
T71	0	590	0	0
T73	0	360	0	0
T74	0	639	0	0
T75	0	417	0	0
T88	0	480	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	96940	0	0
T4	1892	1129	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	324	0	0
T8	0	364	0	0
T11	1767	0	0	0
T14	0	1108	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	216	0	0
T71	0	591	0	0
T73	0	361	0	0
T74	0	640	0	0
T75	0	418	0	0
T88	0	481	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211994821	211883853	0	0
T1	1907	1826	0	0
T2	4733	4646	0	0
T3	985	891	0	0
T4	1716	1562	0	0
T10	3651	3576	0	0
T32	1080	1015	0	0
T38	1282	1190	0	0
T39	1474	1378	0	0
T40	1150	1056	0	0
T46	1606	1517	0	0