Line Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 23 | 23 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
Line Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T86,T116,T117 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T32,T10 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T32,T10 |
| 1 | 0 | Covered | T1,T32,T10 |
| 1 | 1 | Covered | T1,T32,T10 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T32,T10 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T32,T10 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T32,T10 |
| 1 | 1 | Covered | T1,T32,T10 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T32,T10 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T32,T10 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T32,T10 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T32,T10 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T32,T10 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T79,T118 |
| 1 | 1 | Covered | T1,T32,T10 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T32,T10 |
| 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_packer_fifo
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T1,T32,T10 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T32,T10 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_packer_fifo
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1696260472 |
196563901 |
0 |
6208 |
| T1 |
1907 |
1406 |
0 |
1 |
| T2 |
4733 |
0 |
0 |
1 |
| T3 |
1970 |
0 |
0 |
2 |
| T4 |
3784 |
0 |
0 |
2 |
| T5 |
0 |
456092 |
0 |
0 |
| T6 |
0 |
894826 |
0 |
0 |
| T7 |
2296 |
0 |
0 |
2 |
| T10 |
7302 |
3452 |
0 |
2 |
| T11 |
0 |
1507 |
0 |
0 |
| T12 |
0 |
2780 |
0 |
0 |
| T32 |
2160 |
913 |
0 |
2 |
| T33 |
2670 |
2368 |
0 |
2 |
| T34 |
3060 |
1224 |
0 |
2 |
| T35 |
0 |
3409 |
0 |
0 |
| T36 |
0 |
3433 |
0 |
0 |
| T37 |
790 |
0 |
0 |
1 |
| T38 |
2564 |
0 |
0 |
2 |
| T39 |
2948 |
1298 |
0 |
2 |
| T40 |
2300 |
823 |
0 |
2 |
| T41 |
0 |
4537 |
0 |
0 |
| T42 |
0 |
3552 |
0 |
0 |
| T43 |
0 |
1446 |
0 |
0 |
| T44 |
0 |
1414 |
0 |
0 |
| T45 |
0 |
1761 |
0 |
0 |
| T46 |
3212 |
0 |
0 |
2 |
| T68 |
0 |
6040 |
0 |
0 |
| T76 |
0 |
1050 |
0 |
0 |
| T77 |
0 |
1349 |
0 |
0 |
| T78 |
8634 |
0 |
0 |
2 |
| T79 |
2464 |
0 |
0 |
2 |
| T80 |
2010 |
0 |
0 |
2 |
| T81 |
2534 |
0 |
0 |
2 |
| T82 |
1299470 |
0 |
0 |
2 |
| T83 |
18856 |
0 |
0 |
2 |
| T84 |
2472 |
0 |
0 |
2 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1696260472 |
196563901 |
0 |
0 |
| T1 |
1907 |
1406 |
0 |
0 |
| T2 |
4733 |
0 |
0 |
0 |
| T3 |
1970 |
0 |
0 |
0 |
| T4 |
3784 |
0 |
0 |
0 |
| T5 |
0 |
456092 |
0 |
0 |
| T6 |
0 |
894826 |
0 |
0 |
| T7 |
2296 |
0 |
0 |
0 |
| T10 |
7302 |
3452 |
0 |
0 |
| T11 |
0 |
1507 |
0 |
0 |
| T12 |
0 |
2780 |
0 |
0 |
| T32 |
2160 |
913 |
0 |
0 |
| T33 |
2670 |
2368 |
0 |
0 |
| T34 |
3060 |
1224 |
0 |
0 |
| T35 |
0 |
3409 |
0 |
0 |
| T36 |
0 |
3433 |
0 |
0 |
| T37 |
790 |
0 |
0 |
0 |
| T38 |
2564 |
0 |
0 |
0 |
| T39 |
2948 |
1298 |
0 |
0 |
| T40 |
2300 |
823 |
0 |
0 |
| T41 |
0 |
4537 |
0 |
0 |
| T42 |
0 |
3552 |
0 |
0 |
| T43 |
0 |
1446 |
0 |
0 |
| T44 |
0 |
1414 |
0 |
0 |
| T45 |
0 |
1761 |
0 |
0 |
| T46 |
3212 |
0 |
0 |
0 |
| T68 |
0 |
6040 |
0 |
0 |
| T76 |
0 |
1050 |
0 |
0 |
| T77 |
0 |
1349 |
0 |
0 |
| T78 |
8634 |
0 |
0 |
0 |
| T79 |
2464 |
0 |
0 |
0 |
| T80 |
2010 |
0 |
0 |
0 |
| T81 |
2534 |
0 |
0 |
0 |
| T82 |
1299470 |
0 |
0 |
0 |
| T83 |
18856 |
0 |
0 |
0 |
| T84 |
2472 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 23 | 23 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T86,T116,T117 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
12 |
85.71 |
| TERNARY |
141 |
4 |
3 |
75.00 |
| TERNARY |
146 |
3 |
2 |
66.67 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Not Covered |
|
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
212032559 |
199874 |
0 |
776 |
| T1 |
1907 |
19 |
0 |
1 |
| T2 |
4733 |
698 |
0 |
1 |
| T3 |
985 |
634 |
0 |
1 |
| T4 |
1892 |
0 |
0 |
1 |
| T10 |
3651 |
494 |
0 |
1 |
| T11 |
0 |
11 |
0 |
0 |
| T14 |
0 |
70 |
0 |
0 |
| T16 |
0 |
81 |
0 |
0 |
| T32 |
1080 |
0 |
0 |
1 |
| T38 |
1282 |
21 |
0 |
1 |
| T39 |
1474 |
0 |
0 |
1 |
| T40 |
1150 |
87 |
0 |
1 |
| T45 |
0 |
21 |
0 |
0 |
| T46 |
1606 |
0 |
0 |
1 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
212032559 |
199874 |
0 |
0 |
| T1 |
1907 |
19 |
0 |
0 |
| T2 |
4733 |
698 |
0 |
0 |
| T3 |
985 |
634 |
0 |
0 |
| T4 |
1892 |
0 |
0 |
0 |
| T10 |
3651 |
494 |
0 |
0 |
| T11 |
0 |
11 |
0 |
0 |
| T14 |
0 |
70 |
0 |
0 |
| T16 |
0 |
81 |
0 |
0 |
| T32 |
1080 |
0 |
0 |
0 |
| T38 |
1282 |
21 |
0 |
0 |
| T39 |
1474 |
0 |
0 |
0 |
| T40 |
1150 |
87 |
0 |
0 |
| T45 |
0 |
21 |
0 |
0 |
| T46 |
1606 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 39 | 92.86 |
| Logical | 42 | 39 | 92.86 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T38,T11 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T38,T11 |
| 1 | 0 | Covered | T2,T38,T11 |
| 1 | 1 | Covered | T2,T38,T11 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T38,T11 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T38,T11 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T38,T11 |
| 1 | 1 | Covered | T2,T38,T11 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T38,T11 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T38,T11 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T38,T11 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T38,T11 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T38,T11 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T38,T11 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T38,T11 |
| 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T2,T38,T11 |
| 0 |
0 |
1 |
Covered |
T2,T38,T11 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T38,T11 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T38,T11 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
212032559 |
118049 |
0 |
776 |
| T2 |
4733 |
4010 |
0 |
1 |
| T3 |
985 |
0 |
0 |
1 |
| T4 |
1892 |
0 |
0 |
1 |
| T10 |
3651 |
0 |
0 |
1 |
| T11 |
0 |
1044 |
0 |
0 |
| T13 |
0 |
1445 |
0 |
0 |
| T32 |
1080 |
0 |
0 |
1 |
| T33 |
0 |
1095 |
0 |
0 |
| T35 |
0 |
1289 |
0 |
0 |
| T37 |
790 |
0 |
0 |
1 |
| T38 |
1282 |
1016 |
0 |
1 |
| T39 |
1474 |
0 |
0 |
1 |
| T40 |
1150 |
0 |
0 |
1 |
| T42 |
0 |
1607 |
0 |
0 |
| T44 |
0 |
1384 |
0 |
0 |
| T46 |
1606 |
0 |
0 |
1 |
| T69 |
0 |
1119 |
0 |
0 |
| T85 |
0 |
1354 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
212032559 |
118049 |
0 |
0 |
| T2 |
4733 |
4010 |
0 |
0 |
| T3 |
985 |
0 |
0 |
0 |
| T4 |
1892 |
0 |
0 |
0 |
| T10 |
3651 |
0 |
0 |
0 |
| T11 |
0 |
1044 |
0 |
0 |
| T13 |
0 |
1445 |
0 |
0 |
| T32 |
1080 |
0 |
0 |
0 |
| T33 |
0 |
1095 |
0 |
0 |
| T35 |
0 |
1289 |
0 |
0 |
| T37 |
790 |
0 |
0 |
0 |
| T38 |
1282 |
1016 |
0 |
0 |
| T39 |
1474 |
0 |
0 |
0 |
| T40 |
1150 |
0 |
0 |
0 |
| T42 |
0 |
1607 |
0 |
0 |
| T44 |
0 |
1384 |
0 |
0 |
| T46 |
1606 |
0 |
0 |
0 |
| T69 |
0 |
1119 |
0 |
0 |
| T85 |
0 |
1354 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T32,T10 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T32,T10 |
| 1 | 0 | Covered | T1,T32,T10 |
| 1 | 1 | Covered | T1,T32,T10 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T32,T10 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T32,T10 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T32,T10 |
| 1 | 1 | Covered | T1,T32,T10 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T32,T10 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T32,T10 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T32,T10 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T32,T10 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T32,T10 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T79,T118 |
| 1 | 1 | Covered | T1,T32,T10 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T32,T10 |
| 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T32,T10 |
| 0 |
0 |
1 |
Covered |
T1,T32,T10 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T32,T10 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T32,T10 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
212032559 |
195136569 |
0 |
776 |
| T1 |
1907 |
1406 |
0 |
1 |
| T2 |
4733 |
0 |
0 |
1 |
| T3 |
985 |
0 |
0 |
1 |
| T4 |
1892 |
0 |
0 |
1 |
| T5 |
0 |
456092 |
0 |
0 |
| T6 |
0 |
894826 |
0 |
0 |
| T10 |
3651 |
3452 |
0 |
1 |
| T11 |
0 |
1507 |
0 |
0 |
| T32 |
1080 |
913 |
0 |
1 |
| T38 |
1282 |
0 |
0 |
1 |
| T39 |
1474 |
1298 |
0 |
1 |
| T40 |
1150 |
823 |
0 |
1 |
| T45 |
0 |
1761 |
0 |
0 |
| T46 |
1606 |
0 |
0 |
1 |
| T68 |
0 |
6040 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
212032559 |
195136569 |
0 |
0 |
| T1 |
1907 |
1406 |
0 |
0 |
| T2 |
4733 |
0 |
0 |
0 |
| T3 |
985 |
0 |
0 |
0 |
| T4 |
1892 |
0 |
0 |
0 |
| T5 |
0 |
456092 |
0 |
0 |
| T6 |
0 |
894826 |
0 |
0 |
| T10 |
3651 |
3452 |
0 |
0 |
| T11 |
0 |
1507 |
0 |
0 |
| T32 |
1080 |
913 |
0 |
0 |
| T38 |
1282 |
0 |
0 |
0 |
| T39 |
1474 |
1298 |
0 |
0 |
| T40 |
1150 |
823 |
0 |
0 |
| T45 |
0 |
1761 |
0 |
0 |
| T46 |
1606 |
0 |
0 |
0 |
| T68 |
0 |
6040 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T33,T34,T35 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T33,T34,T35 |
| 1 | 0 | Covered | T33,T34,T35 |
| 1 | 1 | Covered | T33,T34,T35 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T33,T34,T35 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T33,T34,T35 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T33,T34,T35 |
| 1 | 1 | Covered | T33,T34,T35 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T33,T34,T35 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T33,T34,T35 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T33,T34,T35 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T33,T34,T35 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T33,T34,T35 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T119,T120,T121 |
| 1 | 1 | Covered | T33,T34,T35 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T33,T34,T35 |
| 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T33,T34,T35 |
| 0 |
0 |
1 |
Covered |
T33,T34,T35 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T33,T34,T35 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T33,T34,T35 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
212032559 |
182611 |
0 |
776 |
| T7 |
1148 |
0 |
0 |
1 |
| T12 |
0 |
1701 |
0 |
0 |
| T33 |
1335 |
1200 |
0 |
1 |
| T34 |
1530 |
1224 |
0 |
1 |
| T35 |
0 |
1712 |
0 |
0 |
| T36 |
0 |
1753 |
0 |
0 |
| T41 |
0 |
1660 |
0 |
0 |
| T42 |
0 |
1497 |
0 |
0 |
| T43 |
0 |
1446 |
0 |
0 |
| T76 |
0 |
1050 |
0 |
0 |
| T77 |
0 |
1349 |
0 |
0 |
| T78 |
4317 |
0 |
0 |
1 |
| T79 |
1232 |
0 |
0 |
1 |
| T80 |
1005 |
0 |
0 |
1 |
| T81 |
1267 |
0 |
0 |
1 |
| T82 |
649735 |
0 |
0 |
1 |
| T83 |
9428 |
0 |
0 |
1 |
| T84 |
1236 |
0 |
0 |
1 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
212032559 |
182611 |
0 |
0 |
| T7 |
1148 |
0 |
0 |
0 |
| T12 |
0 |
1701 |
0 |
0 |
| T33 |
1335 |
1200 |
0 |
0 |
| T34 |
1530 |
1224 |
0 |
0 |
| T35 |
0 |
1712 |
0 |
0 |
| T36 |
0 |
1753 |
0 |
0 |
| T41 |
0 |
1660 |
0 |
0 |
| T42 |
0 |
1497 |
0 |
0 |
| T43 |
0 |
1446 |
0 |
0 |
| T76 |
0 |
1050 |
0 |
0 |
| T77 |
0 |
1349 |
0 |
0 |
| T78 |
4317 |
0 |
0 |
0 |
| T79 |
1232 |
0 |
0 |
0 |
| T80 |
1005 |
0 |
0 |
0 |
| T81 |
1267 |
0 |
0 |
0 |
| T82 |
649735 |
0 |
0 |
0 |
| T83 |
9428 |
0 |
0 |
0 |
| T84 |
1236 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T33,T35,T36 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T33,T35,T36 |
| 1 | 0 | Covered | T33,T35,T36 |
| 1 | 1 | Covered | T33,T35,T36 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T33,T35,T36 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T33,T35,T36 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T33,T35,T36 |
| 1 | 1 | Covered | T33,T35,T36 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T33,T35,T36 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T33,T35,T36 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T33,T35,T36 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T33,T35,T36 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T33,T35,T36 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T122 |
| 1 | 1 | Covered | T33,T35,T36 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T33,T35,T36 |
| 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T33,T35,T36 |
| 0 |
0 |
1 |
Covered |
T33,T35,T36 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T33,T35,T36 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T33,T35,T36 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
212032559 |
187132 |
0 |
776 |
| T7 |
1148 |
0 |
0 |
1 |
| T12 |
0 |
1079 |
0 |
0 |
| T13 |
0 |
1995 |
0 |
0 |
| T33 |
1335 |
1168 |
0 |
1 |
| T34 |
1530 |
0 |
0 |
1 |
| T35 |
0 |
1697 |
0 |
0 |
| T36 |
0 |
1680 |
0 |
0 |
| T41 |
0 |
2877 |
0 |
0 |
| T42 |
0 |
2055 |
0 |
0 |
| T44 |
0 |
1414 |
0 |
0 |
| T74 |
0 |
1533 |
0 |
0 |
| T78 |
4317 |
0 |
0 |
1 |
| T79 |
1232 |
0 |
0 |
1 |
| T80 |
1005 |
0 |
0 |
1 |
| T81 |
1267 |
0 |
0 |
1 |
| T82 |
649735 |
0 |
0 |
1 |
| T83 |
9428 |
0 |
0 |
1 |
| T84 |
1236 |
0 |
0 |
1 |
| T85 |
0 |
1444 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
212032559 |
187132 |
0 |
0 |
| T7 |
1148 |
0 |
0 |
0 |
| T12 |
0 |
1079 |
0 |
0 |
| T13 |
0 |
1995 |
0 |
0 |
| T33 |
1335 |
1168 |
0 |
0 |
| T34 |
1530 |
0 |
0 |
0 |
| T35 |
0 |
1697 |
0 |
0 |
| T36 |
0 |
1680 |
0 |
0 |
| T41 |
0 |
2877 |
0 |
0 |
| T42 |
0 |
2055 |
0 |
0 |
| T44 |
0 |
1414 |
0 |
0 |
| T74 |
0 |
1533 |
0 |
0 |
| T78 |
4317 |
0 |
0 |
0 |
| T79 |
1232 |
0 |
0 |
0 |
| T80 |
1005 |
0 |
0 |
0 |
| T81 |
1267 |
0 |
0 |
0 |
| T82 |
649735 |
0 |
0 |
0 |
| T83 |
9428 |
0 |
0 |
0 |
| T84 |
1236 |
0 |
0 |
0 |
| T85 |
0 |
1444 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T11,T33 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T11,T33 |
| 1 | 0 | Covered | T3,T11,T33 |
| 1 | 1 | Covered | T3,T11,T33 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T11,T33 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T3,T11,T33 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T3,T11,T33 |
| 1 | 1 | Covered | T3,T11,T33 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T11,T33 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T11,T33 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T11,T33 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T11,T33 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T11,T33 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T123 |
| 1 | 1 | Covered | T3,T11,T33 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T11,T33 |
| 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T3,T11,T33 |
| 0 |
0 |
1 |
Covered |
T3,T11,T33 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T3,T11,T33 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T3,T11,T33 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
212032559 |
368702 |
0 |
776 |
| T3 |
985 |
136 |
0 |
1 |
| T4 |
1892 |
0 |
0 |
1 |
| T5 |
459436 |
0 |
0 |
1 |
| T10 |
3651 |
0 |
0 |
1 |
| T11 |
0 |
1092 |
0 |
0 |
| T18 |
0 |
1229 |
0 |
0 |
| T32 |
1080 |
0 |
0 |
1 |
| T33 |
0 |
1025 |
0 |
0 |
| T35 |
0 |
1669 |
0 |
0 |
| T36 |
0 |
1600 |
0 |
0 |
| T37 |
790 |
0 |
0 |
1 |
| T38 |
1282 |
0 |
0 |
1 |
| T39 |
1474 |
0 |
0 |
1 |
| T40 |
1150 |
0 |
0 |
1 |
| T41 |
0 |
3602 |
0 |
0 |
| T42 |
0 |
1529 |
0 |
0 |
| T44 |
0 |
1670 |
0 |
0 |
| T46 |
1606 |
0 |
0 |
1 |
| T86 |
0 |
985 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
212032559 |
368702 |
0 |
0 |
| T3 |
985 |
136 |
0 |
0 |
| T4 |
1892 |
0 |
0 |
0 |
| T5 |
459436 |
0 |
0 |
0 |
| T10 |
3651 |
0 |
0 |
0 |
| T11 |
0 |
1092 |
0 |
0 |
| T18 |
0 |
1229 |
0 |
0 |
| T32 |
1080 |
0 |
0 |
0 |
| T33 |
0 |
1025 |
0 |
0 |
| T35 |
0 |
1669 |
0 |
0 |
| T36 |
0 |
1600 |
0 |
0 |
| T37 |
790 |
0 |
0 |
0 |
| T38 |
1282 |
0 |
0 |
0 |
| T39 |
1474 |
0 |
0 |
0 |
| T40 |
1150 |
0 |
0 |
0 |
| T41 |
0 |
3602 |
0 |
0 |
| T42 |
0 |
1529 |
0 |
0 |
| T44 |
0 |
1670 |
0 |
0 |
| T46 |
1606 |
0 |
0 |
0 |
| T86 |
0 |
985 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T10,T37 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T10,T37 |
| 1 | 0 | Covered | T2,T10,T37 |
| 1 | 1 | Covered | T2,T10,T37 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T10,T37 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T10,T37 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T10,T37 |
| 1 | 1 | Covered | T2,T10,T37 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T10,T37 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T10,T37 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T10,T37 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T10,T37 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T10,T37 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T124 |
| 1 | 1 | Covered | T2,T10,T37 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T10,T37 |
| 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T2,T10,T37 |
| 0 |
0 |
1 |
Covered |
T2,T10,T37 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T10,T37 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T10,T37 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
212032559 |
125525 |
0 |
776 |
| T2 |
4733 |
4322 |
0 |
1 |
| T3 |
985 |
0 |
0 |
1 |
| T4 |
1892 |
0 |
0 |
1 |
| T10 |
3651 |
1985 |
0 |
1 |
| T12 |
0 |
1556 |
0 |
0 |
| T32 |
1080 |
0 |
0 |
1 |
| T33 |
0 |
1105 |
0 |
0 |
| T36 |
0 |
1564 |
0 |
0 |
| T37 |
790 |
581 |
0 |
1 |
| T38 |
1282 |
0 |
0 |
1 |
| T39 |
1474 |
0 |
0 |
1 |
| T40 |
1150 |
0 |
0 |
1 |
| T42 |
0 |
1762 |
0 |
0 |
| T45 |
0 |
1633 |
0 |
0 |
| T46 |
1606 |
0 |
0 |
1 |
| T57 |
0 |
1017 |
0 |
0 |
| T87 |
0 |
636 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
212032559 |
125525 |
0 |
0 |
| T2 |
4733 |
4322 |
0 |
0 |
| T3 |
985 |
0 |
0 |
0 |
| T4 |
1892 |
0 |
0 |
0 |
| T10 |
3651 |
1985 |
0 |
0 |
| T12 |
0 |
1556 |
0 |
0 |
| T32 |
1080 |
0 |
0 |
0 |
| T33 |
0 |
1105 |
0 |
0 |
| T36 |
0 |
1564 |
0 |
0 |
| T37 |
790 |
581 |
0 |
0 |
| T38 |
1282 |
0 |
0 |
0 |
| T39 |
1474 |
0 |
0 |
0 |
| T40 |
1150 |
0 |
0 |
0 |
| T42 |
0 |
1762 |
0 |
0 |
| T45 |
0 |
1633 |
0 |
0 |
| T46 |
1606 |
0 |
0 |
0 |
| T57 |
0 |
1017 |
0 |
0 |
| T87 |
0 |
636 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T16,T11 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T16,T11 |
| 1 | 0 | Covered | T2,T16,T11 |
| 1 | 1 | Covered | T2,T16,T11 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T16,T11 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T16,T11 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T16,T11 |
| 1 | 1 | Covered | T2,T16,T11 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T16,T11 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T16,T11 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T16,T11 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T16,T11 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T16,T11 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T125,T126,T127 |
| 1 | 1 | Covered | T2,T16,T11 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T16,T11 |
| 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T2,T16,T11 |
| 0 |
0 |
1 |
Covered |
T2,T16,T11 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T16,T11 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T16,T11 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
212032559 |
245439 |
0 |
776 |
| T2 |
4733 |
2152 |
0 |
1 |
| T3 |
985 |
0 |
0 |
1 |
| T4 |
1892 |
0 |
0 |
1 |
| T10 |
3651 |
0 |
0 |
1 |
| T11 |
0 |
1375 |
0 |
0 |
| T12 |
0 |
1057 |
0 |
0 |
| T14 |
0 |
1123 |
0 |
0 |
| T16 |
0 |
1389 |
0 |
0 |
| T32 |
1080 |
0 |
0 |
1 |
| T33 |
0 |
1017 |
0 |
0 |
| T35 |
0 |
1664 |
0 |
0 |
| T36 |
0 |
1649 |
0 |
0 |
| T37 |
790 |
0 |
0 |
1 |
| T38 |
1282 |
0 |
0 |
1 |
| T39 |
1474 |
0 |
0 |
1 |
| T40 |
1150 |
0 |
0 |
1 |
| T41 |
0 |
2695 |
0 |
0 |
| T42 |
0 |
1815 |
0 |
0 |
| T46 |
1606 |
0 |
0 |
1 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
212032559 |
245439 |
0 |
0 |
| T2 |
4733 |
2152 |
0 |
0 |
| T3 |
985 |
0 |
0 |
0 |
| T4 |
1892 |
0 |
0 |
0 |
| T10 |
3651 |
0 |
0 |
0 |
| T11 |
0 |
1375 |
0 |
0 |
| T12 |
0 |
1057 |
0 |
0 |
| T14 |
0 |
1123 |
0 |
0 |
| T16 |
0 |
1389 |
0 |
0 |
| T32 |
1080 |
0 |
0 |
0 |
| T33 |
0 |
1017 |
0 |
0 |
| T35 |
0 |
1664 |
0 |
0 |
| T36 |
0 |
1649 |
0 |
0 |
| T37 |
790 |
0 |
0 |
0 |
| T38 |
1282 |
0 |
0 |
0 |
| T39 |
1474 |
0 |
0 |
0 |
| T40 |
1150 |
0 |
0 |
0 |
| T41 |
0 |
2695 |
0 |
0 |
| T42 |
0 |
1815 |
0 |
0 |
| T46 |
1606 |
0 |
0 |
0 |