SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
95.31 | 100.00 | 85.94 | 100.00 | u_edn_core |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
95.31 | 100.00 | 85.94 | 100.00 | u_edn_core |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
95.31 | 100.00 | 85.94 | 100.00 | u_edn_core |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
95.31 | 100.00 | 85.94 | 100.00 | u_edn_core |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 24 | 24 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 23 | 23 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 3104 | 3104 | 0 | 0 |
OutputsKnown_A | 848130236 | 847686364 | 0 | 0 |
gen_no_flops.OutputDelay_A | 848130236 | 847686364 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3104 | 3104 | 0 | 0 |
T1 | 4 | 4 | 0 | 0 |
T2 | 4 | 4 | 0 | 0 |
T3 | 4 | 4 | 0 | 0 |
T4 | 4 | 4 | 0 | 0 |
T10 | 4 | 4 | 0 | 0 |
T32 | 4 | 4 | 0 | 0 |
T38 | 4 | 4 | 0 | 0 |
T39 | 4 | 4 | 0 | 0 |
T40 | 4 | 4 | 0 | 0 |
T46 | 4 | 4 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 848130236 | 847686364 | 0 | 0 |
T1 | 7628 | 7304 | 0 | 0 |
T2 | 18932 | 18584 | 0 | 0 |
T3 | 3940 | 3564 | 0 | 0 |
T4 | 7568 | 6952 | 0 | 0 |
T10 | 14604 | 14304 | 0 | 0 |
T32 | 4320 | 4060 | 0 | 0 |
T38 | 5128 | 4760 | 0 | 0 |
T39 | 5896 | 5512 | 0 | 0 |
T40 | 4600 | 4224 | 0 | 0 |
T46 | 6424 | 6068 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 848130236 | 847686364 | 0 | 0 |
T1 | 7628 | 7304 | 0 | 0 |
T2 | 18932 | 18584 | 0 | 0 |
T3 | 3940 | 3564 | 0 | 0 |
T4 | 7568 | 6952 | 0 | 0 |
T10 | 14604 | 14304 | 0 | 0 |
T32 | 4320 | 4060 | 0 | 0 |
T38 | 5128 | 4760 | 0 | 0 |
T39 | 5896 | 5512 | 0 | 0 |
T40 | 4600 | 4224 | 0 | 0 |
T46 | 6424 | 6068 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 24 | 24 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 23 | 23 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 776 | 776 | 0 | 0 |
OutputsKnown_A | 212032559 | 211921591 | 0 | 0 |
gen_no_flops.OutputDelay_A | 212032559 | 211921591 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 776 | 776 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 212032559 | 211921591 | 0 | 0 |
T1 | 1907 | 1826 | 0 | 0 |
T2 | 4733 | 4646 | 0 | 0 |
T3 | 985 | 891 | 0 | 0 |
T4 | 1892 | 1738 | 0 | 0 |
T10 | 3651 | 3576 | 0 | 0 |
T32 | 1080 | 1015 | 0 | 0 |
T38 | 1282 | 1190 | 0 | 0 |
T39 | 1474 | 1378 | 0 | 0 |
T40 | 1150 | 1056 | 0 | 0 |
T46 | 1606 | 1517 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 212032559 | 211921591 | 0 | 0 |
T1 | 1907 | 1826 | 0 | 0 |
T2 | 4733 | 4646 | 0 | 0 |
T3 | 985 | 891 | 0 | 0 |
T4 | 1892 | 1738 | 0 | 0 |
T10 | 3651 | 3576 | 0 | 0 |
T32 | 1080 | 1015 | 0 | 0 |
T38 | 1282 | 1190 | 0 | 0 |
T39 | 1474 | 1378 | 0 | 0 |
T40 | 1150 | 1056 | 0 | 0 |
T46 | 1606 | 1517 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 776 | 776 | 0 | 0 |
OutputsKnown_A | 212032559 | 211921591 | 0 | 0 |
gen_no_flops.OutputDelay_A | 212032559 | 211921591 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 776 | 776 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 212032559 | 211921591 | 0 | 0 |
T1 | 1907 | 1826 | 0 | 0 |
T2 | 4733 | 4646 | 0 | 0 |
T3 | 985 | 891 | 0 | 0 |
T4 | 1892 | 1738 | 0 | 0 |
T10 | 3651 | 3576 | 0 | 0 |
T32 | 1080 | 1015 | 0 | 0 |
T38 | 1282 | 1190 | 0 | 0 |
T39 | 1474 | 1378 | 0 | 0 |
T40 | 1150 | 1056 | 0 | 0 |
T46 | 1606 | 1517 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 212032559 | 211921591 | 0 | 0 |
T1 | 1907 | 1826 | 0 | 0 |
T2 | 4733 | 4646 | 0 | 0 |
T3 | 985 | 891 | 0 | 0 |
T4 | 1892 | 1738 | 0 | 0 |
T10 | 3651 | 3576 | 0 | 0 |
T32 | 1080 | 1015 | 0 | 0 |
T38 | 1282 | 1190 | 0 | 0 |
T39 | 1474 | 1378 | 0 | 0 |
T40 | 1150 | 1056 | 0 | 0 |
T46 | 1606 | 1517 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 776 | 776 | 0 | 0 |
OutputsKnown_A | 212032559 | 211921591 | 0 | 0 |
gen_no_flops.OutputDelay_A | 212032559 | 211921591 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 776 | 776 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 212032559 | 211921591 | 0 | 0 |
T1 | 1907 | 1826 | 0 | 0 |
T2 | 4733 | 4646 | 0 | 0 |
T3 | 985 | 891 | 0 | 0 |
T4 | 1892 | 1738 | 0 | 0 |
T10 | 3651 | 3576 | 0 | 0 |
T32 | 1080 | 1015 | 0 | 0 |
T38 | 1282 | 1190 | 0 | 0 |
T39 | 1474 | 1378 | 0 | 0 |
T40 | 1150 | 1056 | 0 | 0 |
T46 | 1606 | 1517 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 212032559 | 211921591 | 0 | 0 |
T1 | 1907 | 1826 | 0 | 0 |
T2 | 4733 | 4646 | 0 | 0 |
T3 | 985 | 891 | 0 | 0 |
T4 | 1892 | 1738 | 0 | 0 |
T10 | 3651 | 3576 | 0 | 0 |
T32 | 1080 | 1015 | 0 | 0 |
T38 | 1282 | 1190 | 0 | 0 |
T39 | 1474 | 1378 | 0 | 0 |
T40 | 1150 | 1056 | 0 | 0 |
T46 | 1606 | 1517 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 776 | 776 | 0 | 0 |
OutputsKnown_A | 212032559 | 211921591 | 0 | 0 |
gen_no_flops.OutputDelay_A | 212032559 | 211921591 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 776 | 776 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 212032559 | 211921591 | 0 | 0 |
T1 | 1907 | 1826 | 0 | 0 |
T2 | 4733 | 4646 | 0 | 0 |
T3 | 985 | 891 | 0 | 0 |
T4 | 1892 | 1738 | 0 | 0 |
T10 | 3651 | 3576 | 0 | 0 |
T32 | 1080 | 1015 | 0 | 0 |
T38 | 1282 | 1190 | 0 | 0 |
T39 | 1474 | 1378 | 0 | 0 |
T40 | 1150 | 1056 | 0 | 0 |
T46 | 1606 | 1517 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 212032559 | 211921591 | 0 | 0 |
T1 | 1907 | 1826 | 0 | 0 |
T2 | 4733 | 4646 | 0 | 0 |
T3 | 985 | 891 | 0 | 0 |
T4 | 1892 | 1738 | 0 | 0 |
T10 | 3651 | 3576 | 0 | 0 |
T32 | 1080 | 1015 | 0 | 0 |
T38 | 1282 | 1190 | 0 | 0 |
T39 | 1474 | 1378 | 0 | 0 |
T40 | 1150 | 1056 | 0 | 0 |
T46 | 1606 | 1517 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |