Module Definition
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Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.31 100.00 85.94 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[10].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[10].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[10].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[10].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[11].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[11].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[11].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[11].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[12].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[12].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[12].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[12].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[13].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[13].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[13].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[13].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[14].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[14].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[14].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[14].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[15].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[15].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[15].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[15].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[16].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[16].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[16].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[16].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[17].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[17].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[17].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[17].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[18].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[18].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[18].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[18].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[19].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[19].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[19].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[19].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[20].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[20].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[20].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[20].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[21].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[21].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[21].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[21].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[22].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[22].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[22].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[22].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[6].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[6].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[6].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[6].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[7].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[7].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[7].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[7].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[8].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[8].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[8].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[8].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[9].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[9].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[9].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[9].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.31 100.00 85.94 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.31 100.00 85.94 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.31 100.00 85.94 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=23,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable

Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 23 23


Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=4,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst

Line No.TotalCoveredPercent
TOTAL55100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 4 4


Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=2,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode

SCORELINE
100.00 100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 3104 3104 0 0
OutputsKnown_A 848130236 847686364 0 0
gen_no_flops.OutputDelay_A 848130236 847686364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3104 3104 0 0
T1 4 4 0 0
T2 4 4 0 0
T3 4 4 0 0
T4 4 4 0 0
T10 4 4 0 0
T32 4 4 0 0
T38 4 4 0 0
T39 4 4 0 0
T40 4 4 0 0
T46 4 4 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 848130236 847686364 0 0
T1 7628 7304 0 0
T2 18932 18584 0 0
T3 3940 3564 0 0
T4 7568 6952 0 0
T10 14604 14304 0 0
T32 4320 4060 0 0
T38 5128 4760 0 0
T39 5896 5512 0 0
T40 4600 4224 0 0
T46 6424 6068 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 848130236 847686364 0 0
T1 7628 7304 0 0
T2 18932 18584 0 0
T3 3940 3564 0 0
T4 7568 6952 0 0
T10 14604 14304 0 0
T32 4320 4060 0 0
T38 5128 4760 0 0
T39 5896 5512 0 0
T40 4600 4224 0 0
T46 6424 6068 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 23 23


Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 776 776 0 0
OutputsKnown_A 212032559 211921591 0 0
gen_no_flops.OutputDelay_A 212032559 211921591 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 776 776 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T10 1 1 0 0
T32 1 1 0 0
T38 1 1 0 0
T39 1 1 0 0
T40 1 1 0 0
T46 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 212032559 211921591 0 0
T1 1907 1826 0 0
T2 4733 4646 0 0
T3 985 891 0 0
T4 1892 1738 0 0
T10 3651 3576 0 0
T32 1080 1015 0 0
T38 1282 1190 0 0
T39 1474 1378 0 0
T40 1150 1056 0 0
T46 1606 1517 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 212032559 211921591 0 0
T1 1907 1826 0 0
T2 4733 4646 0 0
T3 985 891 0 0
T4 1892 1738 0 0
T10 3651 3576 0 0
T32 1080 1015 0 0
T38 1282 1190 0 0
T39 1474 1378 0 0
T40 1150 1056 0 0
T46 1606 1517 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst
Line No.TotalCoveredPercent
TOTAL55100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 4 4


Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 776 776 0 0
OutputsKnown_A 212032559 211921591 0 0
gen_no_flops.OutputDelay_A 212032559 211921591 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 776 776 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T10 1 1 0 0
T32 1 1 0 0
T38 1 1 0 0
T39 1 1 0 0
T40 1 1 0 0
T46 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 212032559 211921591 0 0
T1 1907 1826 0 0
T2 4733 4646 0 0
T3 985 891 0 0
T4 1892 1738 0 0
T10 3651 3576 0 0
T32 1080 1015 0 0
T38 1282 1190 0 0
T39 1474 1378 0 0
T40 1150 1056 0 0
T46 1606 1517 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 212032559 211921591 0 0
T1 1907 1826 0 0
T2 4733 4646 0 0
T3 985 891 0 0
T4 1892 1738 0 0
T10 3651 3576 0 0
T32 1080 1015 0 0
T38 1282 1190 0 0
T39 1474 1378 0 0
T40 1150 1056 0 0
T46 1606 1517 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 776 776 0 0
OutputsKnown_A 212032559 211921591 0 0
gen_no_flops.OutputDelay_A 212032559 211921591 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 776 776 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T10 1 1 0 0
T32 1 1 0 0
T38 1 1 0 0
T39 1 1 0 0
T40 1 1 0 0
T46 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 212032559 211921591 0 0
T1 1907 1826 0 0
T2 4733 4646 0 0
T3 985 891 0 0
T4 1892 1738 0 0
T10 3651 3576 0 0
T32 1080 1015 0 0
T38 1282 1190 0 0
T39 1474 1378 0 0
T40 1150 1056 0 0
T46 1606 1517 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 212032559 211921591 0 0
T1 1907 1826 0 0
T2 4733 4646 0 0
T3 985 891 0 0
T4 1892 1738 0 0
T10 3651 3576 0 0
T32 1080 1015 0 0
T38 1282 1190 0 0
T39 1474 1378 0 0
T40 1150 1056 0 0
T46 1606 1517 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 776 776 0 0
OutputsKnown_A 212032559 211921591 0 0
gen_no_flops.OutputDelay_A 212032559 211921591 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 776 776 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T10 1 1 0 0
T32 1 1 0 0
T38 1 1 0 0
T39 1 1 0 0
T40 1 1 0 0
T46 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 212032559 211921591 0 0
T1 1907 1826 0 0
T2 4733 4646 0 0
T3 985 891 0 0
T4 1892 1738 0 0
T10 3651 3576 0 0
T32 1080 1015 0 0
T38 1282 1190 0 0
T39 1474 1378 0 0
T40 1150 1056 0 0
T46 1606 1517 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 212032559 211921591 0 0
T1 1907 1826 0 0
T2 4733 4646 0 0
T3 985 891 0 0
T4 1892 1738 0 0
T10 3651 3576 0 0
T32 1080 1015 0 0
T38 1282 1190 0 0
T39 1474 1378 0 0
T40 1150 1056 0 0
T46 1606 1517 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%