Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	124	1			T7	1		T40	1		T39	1
auto_req_mode	123	1			T1	1		T2	1		T11	1
sw_mode	2503	1			T34	1		T42	1		T35	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

255

1

T1

1

T2

1

T42

1

single

92

1

T7

1

T98

1

T127

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	940	1			T2	1		T7	1		T34	1
auto[2]	144	1			T120	10		T238	1		T239	1
auto[3]	71	1			T46	6		T87	1		T88	1
auto[4]	188	1			T95	6		T122	69		T77	52
auto[5]	139	1			T71	1		T48	1		T99	1
auto[6]	47	1			T39	1		T100	1		T12	1
auto[7]	1221	1			T1	1		T42	1		T45	7

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	79	1			T7	1		T40	1		T101	1
auto[1]	auto_req_mode	73	1			T2	1		T11	1		T41	1
auto[1]	sw_mode	788	1			T34	1		T35	1		T47	73
auto[2]	boot_req_mode	2	1			T238	1		T240	1		-	-
auto[2]	auto_req_mode	5	1			T241	1		T242	1		T243	1
auto[2]	sw_mode	137	1			T120	10		T239	1		T152	49
auto[3]	boot_req_mode	5	1			T87	1		T88	1		T244	1
auto[3]	auto_req_mode	4	1			T245	1		T246	1		T247	1
auto[3]	sw_mode	62	1			T46	6		T248	1		T249	1
auto[4]	boot_req_mode	1	1			T250	1		-	-		-	-
auto[4]	auto_req_mode	4	1			T251	1		T252	1		T253	1
auto[4]	sw_mode	183	1			T95	6		T122	69		T77	52
auto[5]	boot_req_mode	1	1			T99	1		-	-		-	-
auto[5]	auto_req_mode	4	1			T48	1		T209	1		T254	1
auto[5]	sw_mode	134	1			T71	1		T255	41		T256	11
auto[6]	boot_req_mode	5	1			T39	1		T100	1		T257	1
auto[6]	auto_req_mode	4	1			T12	1		T258	1		T13	1
auto[6]	sw_mode	38	1			T259	1		T260	1		T153	22
auto[7]	boot_req_mode	31	1			T52	1		T206	1		T53	1
auto[7]	auto_req_mode	29	1			T1	1		T44	1		T57	1
auto[7]	sw_mode	1161	1			T42	1		T45	7		T36	1