Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cs_cmds_cg 100.00 1 100 1 64 64



Group Instance : edn_cs_cmds_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance edn_cs_cmds_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 19 0 19 100.00
Crosses 49 0 49 100.00


Variables for Group Instance edn_cs_cmds_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acmd 5 0 5 100.00 100 1 1 0
cp_clen 2 0 2 100.00 100 1 1 0
cp_cmd_src 5 0 5 100.00 100 1 1 0
cp_flags 2 0 2 100.00 100 1 1 0
cp_glen 2 0 2 100.00 100 1 1 0
cp_mode 3 0 3 100.00 100 1 1 0


Crosses for Group Instance edn_cs_cmds_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_generate_intended 13 0 13 100.00 100 1 1 0
cr_instantiate_intended 13 0 13 100.00 100 1 1 0
cr_reseed_intended 12 0 12 100.00 100 1 1 0
cr_update_intended 4 0 4 100.00 100 1 1 0
cr_uninstantiate_intended 2 0 2 100.00 100 1 1 0
cr_acmd_mode_cmd_src_unintended 5 0 5 100.00 100 1 1 0


Summary for Variable cp_acmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for cp_acmd

Excluded/Illegal bins
NAMECOUNTSTATUS
auto[INV] 0 Excluded
auto[GENB] 0 Excluded
auto[GENU] 0 Excluded
unused 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] 3494 1 T1 1 T2 2 T7 1
auto[RES] 712 1 T1 1 T2 2 T45 2
auto[GEN] 3322 1 T1 3 T2 2 T7 1
auto[UPD] 461 1 T46 1 T47 9 T82 15
auto[UNI] 3129 1 T1 1 T34 1 T42 2


Summary for Variable cp_clen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_clen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
some_cmd_data 3730 1 T1 4 T2 5 T42 3
no_cmd_data 7388 1 T1 2 T2 1 T7 2


Summary for Variable cp_cmd_src

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for cp_cmd_src

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_cmd_req 10128 1 T1 4 T2 2 T34 3
reseed_cmd 252 1 T1 1 T2 2 T11 2
generate_cmd 250 1 T1 1 T2 2 T11 1
boot_gen_cmd 244 1 T7 1 T4 3 T37 3
boot_ins_cmd 244 1 T7 1 T4 3 T37 3


Summary for Variable cp_flags

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_flags

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
true 3498 1 T1 4 T2 2 T7 1
false 7620 1 T1 2 T2 4 T7 1


Summary for Variable cp_glen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_glen

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
multiple 1002 1 T1 3 T2 5 T7 1
one 1726 1 T1 2 T7 1 T34 1


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_mode 9545 1 T1 2 T34 3 T5 2
boot_mode 678 1 T7 2 T4 6 T37 6
auto_mode 895 1 T1 4 T2 6 T17 3


Summary for Cross cr_generate_intended

Samples crossed: cp_acmd cp_clen cp_glen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 13 0 13 100.00
Automatically Generated Cross Bins 13 0 13 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_generate_intended

Excluded/Illegal bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[GEN] some_cmd_data multiple sw_mode sw_cmd_req 114 1 T42 1 T44 1 T98 1
auto[GEN] some_cmd_data multiple boot_mode sw_cmd_req 52 1 T39 1 T52 1 T53 1
auto[GEN] some_cmd_data multiple auto_mode generate_cmd 87 1 T2 2 T44 1 T127 1
auto[GEN] some_cmd_data one sw_mode sw_cmd_req 38 1 T1 1 T36 1 T93 1
auto[GEN] some_cmd_data one boot_mode sw_cmd_req 19 1 T206 1 T261 1 T262 1
auto[GEN] some_cmd_data one auto_mode generate_cmd 77 1 T1 1 T59 1 T54 1
auto[GEN] no_cmd_data multiple sw_mode sw_cmd_req 18 1 T60 1 T210 1 T216 1
auto[GEN] no_cmd_data multiple boot_mode sw_cmd_req 5 1 T263 1 T208 1 T257 1
auto[GEN] no_cmd_data multiple boot_mode boot_gen_cmd 58 1 T39 1 T52 1 T206 1
auto[GEN] no_cmd_data multiple auto_mode generate_cmd 29 1 T41 2 T93 1 T127 1
auto[GEN] no_cmd_data one sw_mode sw_cmd_req 1311 1 T34 1 T5 1 T35 1
auto[GEN] no_cmd_data one boot_mode sw_cmd_req 5 1 T238 1 T264 1 T265 1
auto[GEN] no_cmd_data one auto_mode generate_cmd 57 1 T11 1 T59 1 T245 1


User Defined Cross Bins for cr_generate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_gen 0 Excluded
gen_auto_wrong_src 0 Excluded
gen_boot_wrong_src 0 Excluded
gen_boot_seq_wrong_clen 0 Excluded
gen_boot_seq_wrong_glen 0 Excluded
gen_sw_wrong_src 0 Excluded


Summary for Cross cr_instantiate_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 13 0 13 100.00
Automatically Generated Cross Bins 13 0 13 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] some_cmd_data true sw_mode sw_cmd_req 651 1 T42 2 T45 2 T71 1
auto[INS] some_cmd_data true boot_mode sw_cmd_req 10 1 T52 1 T261 1 T266 1
auto[INS] some_cmd_data true auto_mode sw_cmd_req 73 1 T1 1 T2 2 T11 1
auto[INS] some_cmd_data false sw_mode sw_cmd_req 669 1 T45 1 T36 1 T46 1
auto[INS] some_cmd_data false boot_mode sw_cmd_req 12 1 T267 1 T55 1 T91 1
auto[INS] some_cmd_data false auto_mode sw_cmd_req 60 1 T41 1 T93 1 T128 1
auto[INS] no_cmd_data true sw_mode sw_cmd_req 185 1 T45 1 T47 7 T82 10
auto[INS] no_cmd_data true boot_mode sw_cmd_req 2 1 T268 1 T269 1 - -
auto[INS] no_cmd_data true auto_mode sw_cmd_req 61 1 T17 1 T18 1 T19 1
auto[INS] no_cmd_data false sw_mode sw_cmd_req 1475 1 T34 1 T5 1 T35 1
auto[INS] no_cmd_data false boot_mode sw_cmd_req 4 1 T97 1 T108 1 T257 1
auto[INS] no_cmd_data false boot_mode boot_ins_cmd 145 1 T4 1 T37 2 T15 1
auto[INS] no_cmd_data false auto_mode sw_cmd_req 48 1 T41 1 T129 1 T8 1


User Defined Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_ins 0 Excluded
ins_auto_wrong_src 0 Excluded
ins_boot_wrong_src 0 Excluded
ins_boot_seq_wrong_clen 0 Excluded
ins_boot_seq_wrong_flag0 0 Excluded
ins_sw_wrong_src 0 Excluded


Summary for Cross cr_reseed_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 12 0 12 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_reseed_intended

Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[RES] some_cmd_data true sw_mode sw_cmd_req 179 1 T46 3 T47 6 T60 1
auto[RES] some_cmd_data true boot_mode sw_cmd_req 14 1 T238 1 T53 1 T244 1
auto[RES] some_cmd_data true auto_mode reseed_cmd 86 1 T93 1 T129 1 T48 1
auto[RES] some_cmd_data false sw_mode sw_cmd_req 158 1 T45 2 T71 1 T47 3
auto[RES] some_cmd_data false boot_mode sw_cmd_req 12 1 T39 1 T87 1 T270 1
auto[RES] some_cmd_data false auto_mode reseed_cmd 90 1 T2 1 T11 2 T44 1
auto[RES] no_cmd_data true sw_mode sw_cmd_req 39 1 T156 1 T207 1 T122 3
auto[RES] no_cmd_data true boot_mode sw_cmd_req 1 1 T271 1 - - - -
auto[RES] no_cmd_data true auto_mode reseed_cmd 25 1 T41 1 T127 1 T8 1
auto[RES] no_cmd_data false sw_mode sw_cmd_req 43 1 T47 1 T82 1 T121 2
auto[RES] no_cmd_data false boot_mode sw_cmd_req 3 1 T272 1 T273 1 T274 1
auto[RES] no_cmd_data false auto_mode reseed_cmd 51 1 T1 1 T2 1 T127 1


User Defined Cross Bins for cr_reseed_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_res 0 Excluded
res_auto_wrong_src 0 Excluded
res_boot_wrong_src 0 Excluded
res_sw_wrong_src 0 Excluded


Summary for Cross cr_update_intended

Samples crossed: cp_acmd cp_clen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_update_intended

Excluded/Illegal bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)


Covered bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UPD] some_cmd_data sw_mode sw_cmd_req 326 1 T46 1 T47 7 T82 11
auto[UPD] some_cmd_data boot_mode sw_cmd_req 19 1 T206 1 T275 1 T263 1
auto[UPD] no_cmd_data sw_mode sw_cmd_req 96 1 T47 2 T82 4 T119 1
auto[UPD] no_cmd_data boot_mode sw_cmd_req 4 1 T276 1 T277 1 T278 1


User Defined Cross Bins for cr_update_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_upd 0 Excluded
upd_auto_wrong_src 0 Excluded
upd_boot_wrong_src 0 Excluded
upd_sw_wrong_src 0 Excluded


Summary for Cross cr_uninstantiate_intended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UNI] sw_mode sw_cmd_req 3083 1 T1 1 T34 1 T42 2
auto[UNI] boot_mode sw_cmd_req 28 1 T52 1 T261 1 T267 1


User Defined Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_uni 0 Excluded
uni_auto_wrong_src 0 Excluded
uni_boot_wrong_src 0 Excluded
uni_sw_wrong_src 0 Excluded


Summary for Cross cr_acmd_mode_cmd_src_unintended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 5 0 5 100.00
Automatically Generated Cross Bins 5 0 5 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] auto_mode sw_cmd_req 242 1 T1 1 T2 2 T17 1
auto[RES] auto_mode sw_cmd_req 11 1 T48 1 T79 1 T279 1
auto[GEN] auto_mode sw_cmd_req 106 1 T1 1 T17 2 T18 2
auto[UPD] auto_mode sw_cmd_req 16 1 T280 1 T107 1 T12 1
auto[UNI] auto_mode sw_cmd_req 18 1 T44 1 T246 1 T212 1


User Defined Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_sw_cmd 0 Excluded
not_auto_mode 0 Excluded

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