Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	578818	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5074766

1

T20

234

T21

9

T22

159

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1472305	1			T20	273		T21	18		T22	89
values[0x0]	1939234	1			T20	119		T21	6		T22	62
values[0x1]	2242045	1			T20	101		T21	5		T22	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	280511	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5373073

1

T20

322

T21

13

T22

170

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21811	1			T20	3		T22	1		T146	6
valid_sources[0x01]	22043	1			T20	3		T28	1		T29	1
valid_sources[0x02]	21722	1			T22	3		T29	5		T145	10
valid_sources[0x03]	22637	1			T20	3		T21	1		T23	2
valid_sources[0x04]	22417	1			T20	3		T22	1		T26	173
valid_sources[0x05]	22045	1			T20	2		T33	1		T205	1
valid_sources[0x06]	22105	1			T20	1		T155	4		T143	2
valid_sources[0x07]	22114	1			T20	1		T24	1		T146	2
valid_sources[0x08]	21559	1			T20	2		T22	1		T23	1
valid_sources[0x09]	21862	1			T20	2		T21	1		T33	1
valid_sources[0x0a]	21980	1			T20	2		T29	2		T146	2
valid_sources[0x0b]	21799	1			T20	7		T28	3		T146	1
valid_sources[0x0c]	21876	1			T20	3		T22	2		T24	6
valid_sources[0x0d]	21541	1			T20	3		T28	1		T70	1
valid_sources[0x0e]	22457	1			T20	1		T24	29		T146	1
valid_sources[0x0f]	22167	1			T20	1		T33	1		T143	3
valid_sources[0x10]	21951	1			T20	3		T22	1		T33	2
valid_sources[0x11]	22060	1			T20	3		T22	3		T154	26
valid_sources[0x12]	22632	1			T20	1		T22	3		T28	3
valid_sources[0x13]	21477	1			T20	1		T22	2		T24	5
valid_sources[0x14]	22576	1			T20	1		T29	6		T33	1
valid_sources[0x15]	21580	1			T20	4		T22	1		T23	1
valid_sources[0x16]	22087	1			T20	1		T29	1		T33	2
valid_sources[0x17]	21286	1			T20	2		T22	2		T24	20
valid_sources[0x18]	22535	1			T20	1		T22	2		T23	4
valid_sources[0x19]	22456	1			T20	4		T22	1		T28	1
valid_sources[0x1a]	21647	1			T20	1		T29	3		T146	2
valid_sources[0x1b]	22996	1			T20	3		T23	5		T29	1
valid_sources[0x1c]	21705	1			T20	1		T28	2		T146	5
valid_sources[0x1d]	22523	1			T29	3		T143	1		T34	1
valid_sources[0x1e]	21872	1			T20	2		T22	2		T28	1
valid_sources[0x1f]	22342	1			T20	1		T21	1		T22	4
valid_sources[0x20]	22096	1			T20	1		T33	1		T155	2
valid_sources[0x21]	22190	1			T24	2		T28	1		T145	7
valid_sources[0x22]	22363	1			T27	1		T28	1		T143	2
valid_sources[0x23]	21357	1			T20	6		T23	2		T29	8
valid_sources[0x24]	23528	1			T20	1		T2	1		T45	2
valid_sources[0x25]	22525	1			T21	1		T22	1		T25	20
valid_sources[0x26]	21006	1			T20	2		T27	1		T146	2
valid_sources[0x27]	21838	1			T20	2		T27	1		T146	1
valid_sources[0x28]	21396	1			T29	1		T33	3		T143	2
valid_sources[0x29]	21345	1			T29	5		T33	1		T143	1
valid_sources[0x2a]	22598	1			T23	6		T29	1		T144	1
valid_sources[0x2b]	23980	1			T20	3		T22	1		T27	1
valid_sources[0x2c]	21577	1			T146	1		T144	1		T143	1
valid_sources[0x2d]	23228	1			T20	1		T22	1		T24	1
valid_sources[0x2e]	22499	1			T20	1		T29	1		T146	3
valid_sources[0x2f]	22905	1			T20	2		T155	2		T143	1
valid_sources[0x30]	21434	1			T20	1		T23	6		T29	1
valid_sources[0x31]	23400	1			T20	1		T22	1		T23	13
valid_sources[0x32]	21816	1			T23	1		T29	21		T146	1
valid_sources[0x33]	23057	1			T20	2		T22	3		T28	1
valid_sources[0x34]	22533	1			T20	2		T27	1		T29	5
valid_sources[0x35]	20967	1			T20	2		T21	1		T22	1
valid_sources[0x36]	22125	1			T20	5		T22	5		T24	10
valid_sources[0x37]	22446	1			T20	2		T29	3		T62	1
valid_sources[0x38]	22206	1			T20	2		T21	2		T144	1
valid_sources[0x39]	22235	1			T20	2		T22	3		T27	1
valid_sources[0x3a]	21901	1			T20	3		T29	1		T144	1
valid_sources[0x3b]	21753	1			T28	1		T29	5		T146	1
valid_sources[0x3c]	22317	1			T20	1		T22	1		T28	2
valid_sources[0x3d]	21564	1			T20	1		T34	1		T63	1
valid_sources[0x3e]	23111	1			T20	1		T146	1		T144	1
valid_sources[0x3f]	21501	1			T20	3		T22	4		T281	1
valid_sources[0x40]	22484	1			T20	3		T28	1		T29	3
valid_sources[0x41]	22258	1			T20	3		T22	2		T28	1
valid_sources[0x42]	21851	1			T20	2		T33	1		T1	1
valid_sources[0x43]	22281	1			T20	2		T22	2		T28	2
valid_sources[0x44]	21871	1			T20	1		T22	1		T28	1
valid_sources[0x45]	22246	1			T20	5		T26	61		T146	2
valid_sources[0x46]	22417	1			T20	2		T23	1		T24	2
valid_sources[0x47]	21931	1			T24	9		T33	1		T192	5
valid_sources[0x48]	21637	1			T146	1		T71	3		T17	1
valid_sources[0x49]	22743	1			T20	2		T28	3		T33	1
valid_sources[0x4a]	21942	1			T20	1		T155	5		T45	1
valid_sources[0x4b]	23452	1			T20	2		T145	7		T143	2
valid_sources[0x4c]	22725	1			T20	4		T22	2		T28	1
valid_sources[0x4d]	21478	1			T20	2		T22	1		T23	4
valid_sources[0x4e]	22339	1			T20	7		T27	1		T143	2
valid_sources[0x4f]	21270	1			T20	1		T27	1		T29	9
valid_sources[0x50]	22350	1			T20	1		T33	2		T144	2
valid_sources[0x51]	22203	1			T20	2		T27	1		T146	2
valid_sources[0x52]	22103	1			T20	4		T21	1		T62	5
valid_sources[0x53]	22710	1			T20	5		T21	2		T22	1
valid_sources[0x54]	20948	1			T20	1		T29	2		T3	2
valid_sources[0x55]	21351	1			T20	4		T22	1		T29	13
valid_sources[0x56]	22529	1			T20	1		T22	1		T28	1
valid_sources[0x57]	22384	1			T20	3		T24	17		T27	2
valid_sources[0x58]	21240	1			T20	2		T143	1		T34	1
valid_sources[0x59]	21244	1			T23	11		T27	2		T29	2
valid_sources[0x5a]	21950	1			T20	2		T29	6		T146	1
valid_sources[0x5b]	20834	1			T20	2		T23	1		T24	1
valid_sources[0x5c]	22296	1			T23	7		T62	8		T143	1
valid_sources[0x5d]	22867	1			T20	2		T28	1		T144	3
valid_sources[0x5e]	21637	1			T21	1		T22	4		T24	2
valid_sources[0x5f]	21396	1			T20	4		T28	1		T146	1
valid_sources[0x60]	23854	1			T20	2		T143	1		T281	1
valid_sources[0x61]	22050	1			T20	2		T24	1		T29	1
valid_sources[0x62]	23261	1			T20	1		T21	1		T22	2
valid_sources[0x63]	23409	1			T20	1		T27	1		T28	2
valid_sources[0x64]	21009	1			T23	4		T144	1		T143	2
valid_sources[0x65]	22395	1			T20	2		T22	3		T23	1
valid_sources[0x66]	22628	1			T20	2		T33	1		T205	1
valid_sources[0x67]	22318	1			T20	1		T21	3		T28	1
valid_sources[0x68]	21766	1			T20	2		T143	2		T47	577
valid_sources[0x69]	21563	1			T20	1		T33	1		T45	3
valid_sources[0x6a]	22392	1			T5	3		T70	1		T45	6
valid_sources[0x6b]	21850	1			T20	2		T146	1		T143	1
valid_sources[0x6c]	21782	1			T20	2		T146	3		T33	1
valid_sources[0x6d]	21785	1			T20	1		T28	2		T146	2
valid_sources[0x6e]	21826	1			T20	2		T22	2		T28	1
valid_sources[0x6f]	23041	1			T27	1		T144	1		T143	1
valid_sources[0x70]	22214	1			T20	3		T27	1		T29	6
valid_sources[0x71]	22053	1			T20	3		T29	6		T33	3
valid_sources[0x72]	21243	1			T20	2		T22	1		T146	2
valid_sources[0x73]	22314	1			T144	1		T143	1		T45	6
valid_sources[0x74]	23493	1			T20	2		T22	1		T24	7
valid_sources[0x75]	21867	1			T20	2		T29	2		T146	1
valid_sources[0x76]	22444	1			T20	1		T22	1		T29	3
valid_sources[0x77]	21884	1			T20	2		T22	5		T27	2
valid_sources[0x78]	21798	1			T20	3		T28	1		T155	2
valid_sources[0x79]	22081	1			T20	1		T22	1		T28	1
valid_sources[0x7a]	21837	1			T20	2		T27	1		T29	7
valid_sources[0x7b]	22416	1			T22	1		T145	2		T155	1
valid_sources[0x7c]	22530	1			T20	1		T155	5		T281	2
valid_sources[0x7d]	21241	1			T20	3		T33	1		T63	1
valid_sources[0x7e]	22229	1			T20	1		T27	1		T143	2
valid_sources[0x7f]	21826	1			T20	7		T26	91		T34	1
valid_sources[0x80]	21682	1			T20	2		T33	2		T144	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1274660

1

T20

88

T21

4

T22

55

values[0x0]

all_enables

biggest_size

1901255

1

T20

85

T21

2

T22

56

values[0x1]

all_enables

biggest_size

1898851

1

T20

61

T21

3

T22

48