Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	100.00	1	100	1	64	64

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	0	52	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	0	52	100.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
non_zero_bins[0]	2144	1		T1	5	T42	1	T45	6
non_zero_bins[1]	1515	1		T2	1	T42	2	T45	2
zero	7069	1		T1	3	T2	2	T7	2

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	423	1		T46	1	T47	9	T82	15
uni	2982	1		T1	1	T34	1	T42	2
gen	3240	1		T1	4	T7	1	T34	1
res	668	1		T1	2	T2	2	T45	2
ins	3415	1		T1	1	T2	1	T7	1

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

7319

mubi_true

3409

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

5387

pass

5341

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	0	52	100.00
Automatically Generated Cross Bins	52	0	52	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	non_zero_bins[0]	fail	mubi_false	51	1		T47	2	T119	1	T121	1
upd	non_zero_bins[0]	fail	mubi_true	49	1		T46	1	T47	1	T82	4
upd	non_zero_bins[0]	pass	mubi_false	43	1		T82	3	T119	1	T156	2
upd	non_zero_bins[0]	pass	mubi_true	41	1		T82	1	T159	2	T81	1
upd	non_zero_bins[1]	fail	mubi_false	45	1		T47	1	T98	1	T206	1
upd	non_zero_bins[1]	fail	mubi_true	41	1		T47	1	T82	1	T119	1
upd	non_zero_bins[1]	pass	mubi_false	32	1		T47	1	T82	1	T148	1
upd	non_zero_bins[1]	pass	mubi_true	25	1		T47	1	T82	1	T119	1
upd	zero	fail	mubi_false	33	1		T47	1	T82	1	T119	1
upd	zero	fail	mubi_true	21	1		T122	1	T148	1	T150	1
upd	zero	pass	mubi_false	22	1		T82	1	T156	1	T122	1
upd	zero	pass	mubi_true	20	1		T47	1	T82	2	T122	1
uni	zero	fail	mubi_false	1080	1		T42	1	T35	1	T45	1
uni	zero	fail	mubi_true	415	1		T34	1	T45	3	T46	1
uni	zero	pass	mubi_false	1080	1		T1	1	T45	4	T71	1
uni	zero	pass	mubi_true	407	1		T42	1	T47	11	T82	12
gen	non_zero_bins[0]	fail	mubi_false	203	1		T45	1	T46	1	T47	2
gen	non_zero_bins[0]	fail	mubi_true	194	1		T1	2	T45	1	T47	6
gen	non_zero_bins[0]	pass	mubi_false	199	1		T42	1	T46	1	T47	3
gen	non_zero_bins[0]	pass	mubi_true	209	1		T1	2	T36	1	T46	1
gen	non_zero_bins[1]	fail	mubi_false	140	1		T46	1	T47	3	T82	1
gen	non_zero_bins[1]	fail	mubi_true	143	1		T47	2	T82	7	T156	1
gen	non_zero_bins[1]	pass	mubi_false	152	1		T71	1	T47	5	T82	4
gen	non_zero_bins[1]	pass	mubi_true	119	1		T45	1	T47	3	T82	4
gen	zero	fail	mubi_false	779	1		T7	1	T34	1	T5	1
gen	zero	fail	mubi_true	151	1		T4	1	T17	2	T47	2
gen	zero	pass	mubi_false	784	1		T6	1	T45	1	T46	1
gen	zero	pass	mubi_true	167	1		T4	1	T47	1	T82	5
res	non_zero_bins[0]	fail	mubi_false	85	1		T45	2	T82	3	T121	2
res	non_zero_bins[0]	fail	mubi_true	68	1		T46	2	T47	2	T82	2
res	non_zero_bins[0]	pass	mubi_false	62	1		T82	2	T87	1	T121	2
res	non_zero_bins[0]	pass	mubi_true	88	1		T46	1	T47	3	T82	1
res	non_zero_bins[1]	fail	mubi_false	62	1		T11	2	T82	1	T120	1
res	non_zero_bins[1]	fail	mubi_true	42	1		T47	1	T82	1	T156	1
res	non_zero_bins[1]	pass	mubi_false	52	1		T71	1	T11	1	T47	3
res	non_zero_bins[1]	pass	mubi_true	72	1		T82	2	T119	1	T156	1
res	zero	fail	mubi_false	35	1		T1	1	T2	1	T47	1
res	zero	fail	mubi_true	38	1		T41	1	T207	1	T122	2
res	zero	pass	mubi_false	38	1		T1	1	T2	1	T121	1
res	zero	pass	mubi_true	26	1		T41	1	T156	1	T122	1
ins	non_zero_bins[0]	fail	mubi_false	213	1		T46	1	T47	11	T60	1
ins	non_zero_bins[0]	fail	mubi_true	223	1		T45	2	T11	1	T47	5
ins	non_zero_bins[0]	pass	mubi_false	217	1		T36	1	T47	3	T82	9
ins	non_zero_bins[0]	pass	mubi_true	199	1		T1	1	T46	1	T47	3
ins	non_zero_bins[1]	fail	mubi_false	149	1		T47	3	T82	9	T119	1
ins	non_zero_bins[1]	fail	mubi_true	157	1		T71	1	T46	2	T47	2
ins	non_zero_bins[1]	pass	mubi_false	145	1		T45	1	T47	8	T82	8
ins	non_zero_bins[1]	pass	mubi_true	139	1		T2	1	T42	2	T36	1
ins	zero	fail	mubi_false	792	1		T34	1	T5	1	T35	1
ins	zero	fail	mubi_true	178	1		T17	1	T47	4	T37	1
ins	zero	pass	mubi_false	826	1		T45	2	T47	21	T37	1
ins	zero	pass	mubi_true	177	1		T7	1	T4	2	T45	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded