Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cs_cmds_cg 100.00 1 100 1 64 64



Group Instance : edn_cs_cmds_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance edn_cs_cmds_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 19 0 19 100.00
Crosses 49 0 49 100.00


Variables for Group Instance edn_cs_cmds_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acmd 5 0 5 100.00 100 1 1 0
cp_clen 2 0 2 100.00 100 1 1 0
cp_cmd_src 5 0 5 100.00 100 1 1 0
cp_flags 2 0 2 100.00 100 1 1 0
cp_glen 2 0 2 100.00 100 1 1 0
cp_mode 3 0 3 100.00 100 1 1 0


Crosses for Group Instance edn_cs_cmds_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_generate_intended 13 0 13 100.00 100 1 1 0
cr_instantiate_intended 13 0 13 100.00 100 1 1 0
cr_reseed_intended 12 0 12 100.00 100 1 1 0
cr_update_intended 4 0 4 100.00 100 1 1 0
cr_uninstantiate_intended 2 0 2 100.00 100 1 1 0
cr_acmd_mode_cmd_src_unintended 5 0 5 100.00 100 1 1 0


Summary for Variable cp_acmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for cp_acmd

Excluded/Illegal bins
NAMECOUNTSTATUS
auto[INV] 0 Excluded
auto[GENB] 0 Excluded
auto[GENU] 0 Excluded
unused 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] 3972 1 T1 1 T2 1 T3 2
auto[RES] 822 1 T1 1 T4 3 T22 1
auto[GEN] 3757 1 T1 2 T2 1 T3 1
auto[UPD] 528 1 T1 1 T2 1 T6 2
auto[UNI] 3543 1 T1 1 T2 1 T3 2


Summary for Variable cp_clen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_clen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
some_cmd_data 4301 1 T1 3 T2 3 T3 3
no_cmd_data 8321 1 T1 3 T2 1 T3 2


Summary for Variable cp_cmd_src

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for cp_cmd_src

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_cmd_req 11501 1 T1 4 T2 4 T3 5
reseed_cmd 298 1 T1 1 T4 3 T9 1
generate_cmd 297 1 T1 1 T4 3 T9 1
boot_gen_cmd 263 1 T21 1 T25 3 T71 3
boot_ins_cmd 263 1 T21 1 T25 3 T71 3


Summary for Variable cp_flags

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_flags

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
true 3980 1 T1 3 T2 3 T3 3
false 8642 1 T1 3 T2 1 T3 2


Summary for Variable cp_glen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_glen

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
multiple 1154 1 T1 3 T3 2 T4 2
one 1951 1 T1 1 T2 2 T17 2


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_mode 10831 1 T1 2 T2 4 T3 5
boot_mode 738 1 T21 2 T25 6 T71 6
auto_mode 1053 1 T1 4 T17 3 T18 3


Summary for Cross cr_generate_intended

Samples crossed: cp_acmd cp_clen cp_glen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 13 0 13 100.00
Automatically Generated Cross Bins 13 0 13 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_generate_intended

Excluded/Illegal bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[GEN] some_cmd_data multiple sw_mode sw_cmd_req 116 1 T1 1 T3 1 T22 1
auto[GEN] some_cmd_data multiple boot_mode sw_cmd_req 56 1 T32 1 T74 1 T330 1
auto[GEN] some_cmd_data multiple auto_mode generate_cmd 101 1 T7 2 T84 2 T117 1
auto[GEN] some_cmd_data one sw_mode sw_cmd_req 50 1 T2 1 T9 1 T13 1
auto[GEN] some_cmd_data one boot_mode sw_cmd_req 16 1 T309 1 T331 1 T332 1
auto[GEN] some_cmd_data one auto_mode generate_cmd 110 1 T1 1 T4 2 T9 1
auto[GEN] no_cmd_data multiple sw_mode sw_cmd_req 31 1 T31 1 T75 1 T37 1
auto[GEN] no_cmd_data multiple boot_mode sw_cmd_req 12 1 T56 1 T64 1 T265 1
auto[GEN] no_cmd_data multiple boot_mode boot_gen_cmd 68 1 T74 1 T330 1 T35 1
auto[GEN] no_cmd_data multiple auto_mode generate_cmd 28 1 T77 1 T333 1 T301 1
auto[GEN] no_cmd_data one sw_mode sw_cmd_req 1464 1 T20 1 T5 1 T6 4
auto[GEN] no_cmd_data one boot_mode sw_cmd_req 6 1 T334 1 T335 1 T285 1
auto[GEN] no_cmd_data one auto_mode generate_cmd 58 1 T4 1 T7 1 T8 1


User Defined Cross Bins for cr_generate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_gen 0 Excluded
gen_auto_wrong_src 0 Excluded
gen_boot_wrong_src 0 Excluded
gen_boot_seq_wrong_clen 0 Excluded
gen_boot_seq_wrong_glen 0 Excluded
gen_sw_wrong_src 0 Excluded


Summary for Cross cr_instantiate_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 13 0 13 100.00
Automatically Generated Cross Bins 13 0 13 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] some_cmd_data true sw_mode sw_cmd_req 706 1 T2 1 T3 1 T6 1
auto[INS] some_cmd_data true boot_mode sw_cmd_req 13 1 T265 1 T331 1 T332 1
auto[INS] some_cmd_data true auto_mode sw_cmd_req 72 1 T9 1 T13 1 T77 1
auto[INS] some_cmd_data false sw_mode sw_cmd_req 820 1 T3 1 T22 1 T6 4
auto[INS] some_cmd_data false boot_mode sw_cmd_req 13 1 T35 1 T336 1 T337 1
auto[INS] some_cmd_data false auto_mode sw_cmd_req 82 1 T84 1 T117 1 T81 2
auto[INS] no_cmd_data true sw_mode sw_cmd_req 196 1 T6 1 T29 1 T79 1
auto[INS] no_cmd_data true boot_mode sw_cmd_req 5 1 T338 1 T339 1 T281 1
auto[INS] no_cmd_data true auto_mode sw_cmd_req 75 1 T17 1 T18 1 T19 1
auto[INS] no_cmd_data false sw_mode sw_cmd_req 1665 1 T20 1 T5 1 T6 4
auto[INS] no_cmd_data false boot_mode sw_cmd_req 1 1 T340 1 - - - -
auto[INS] no_cmd_data false boot_mode boot_ins_cmd 138 1 T25 2 T71 2 T32 1
auto[INS] no_cmd_data false auto_mode sw_cmd_req 61 1 T1 1 T4 1 T7 1


User Defined Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_ins 0 Excluded
ins_auto_wrong_src 0 Excluded
ins_boot_wrong_src 0 Excluded
ins_boot_seq_wrong_clen 0 Excluded
ins_boot_seq_wrong_flag0 0 Excluded
ins_sw_wrong_src 0 Excluded


Summary for Cross cr_reseed_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 12 0 12 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_reseed_intended

Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[RES] some_cmd_data true sw_mode sw_cmd_req 212 1 T6 1 T68 1 T104 1
auto[RES] some_cmd_data true boot_mode sw_cmd_req 12 1 T32 1 T341 1 T307 1
auto[RES] some_cmd_data true auto_mode reseed_cmd 107 1 T4 1 T9 1 T13 1
auto[RES] some_cmd_data false sw_mode sw_cmd_req 172 1 T22 1 T6 1 T29 1
auto[RES] some_cmd_data false boot_mode sw_cmd_req 9 1 T330 1 T334 1 T66 1
auto[RES] some_cmd_data false auto_mode reseed_cmd 108 1 T1 1 T4 1 T7 1
auto[RES] no_cmd_data true sw_mode sw_cmd_req 49 1 T79 1 T80 3 T298 1
auto[RES] no_cmd_data true boot_mode sw_cmd_req 5 1 T342 1 T304 1 T343 1
auto[RES] no_cmd_data true auto_mode reseed_cmd 23 1 T7 1 T301 1 T46 1
auto[RES] no_cmd_data false sw_mode sw_cmd_req 45 1 T80 1 T264 1 T105 2
auto[RES] no_cmd_data false boot_mode sw_cmd_req 1 1 T344 1 - - - -
auto[RES] no_cmd_data false auto_mode reseed_cmd 60 1 T4 1 T7 1 T8 1


User Defined Cross Bins for cr_reseed_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_res 0 Excluded
res_auto_wrong_src 0 Excluded
res_boot_wrong_src 0 Excluded
res_sw_wrong_src 0 Excluded


Summary for Cross cr_update_intended

Samples crossed: cp_acmd cp_clen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_update_intended

Excluded/Illegal bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)


Covered bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UPD] some_cmd_data sw_mode sw_cmd_req 384 1 T2 1 T6 1 T30 1
auto[UPD] some_cmd_data boot_mode sw_cmd_req 25 1 T74 1 T64 1 T345 1
auto[UPD] no_cmd_data sw_mode sw_cmd_req 98 1 T6 1 T104 1 T79 4
auto[UPD] no_cmd_data boot_mode sw_cmd_req 6 1 T309 1 T56 1 T286 1


User Defined Cross Bins for cr_update_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_upd 0 Excluded
upd_auto_wrong_src 0 Excluded
upd_boot_wrong_src 0 Excluded
upd_sw_wrong_src 0 Excluded


Summary for Cross cr_uninstantiate_intended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UNI] sw_mode sw_cmd_req 3495 1 T1 1 T2 1 T3 2
auto[UNI] boot_mode sw_cmd_req 32 1 T35 1 T265 1 T336 1


User Defined Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_uni 0 Excluded
uni_auto_wrong_src 0 Excluded
uni_boot_wrong_src 0 Excluded
uni_sw_wrong_src 0 Excluded


Summary for Cross cr_acmd_mode_cmd_src_unintended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 5 0 5 100.00
Automatically Generated Cross Bins 5 0 5 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] auto_mode sw_cmd_req 290 1 T1 1 T17 1 T18 1
auto[RES] auto_mode sw_cmd_req 19 1 T37 1 T346 1 T347 1
auto[GEN] auto_mode sw_cmd_req 118 1 T17 2 T18 2 T9 1
auto[UPD] auto_mode sw_cmd_req 15 1 T1 1 T13 1 T117 1
auto[UNI] auto_mode sw_cmd_req 16 1 T333 1 T112 1 T348 1


User Defined Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_sw_cmd 0 Excluded
not_auto_mode 0 Excluded

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