Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	651170	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5500250

1

T1

44

T2

27

T3

30

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1620385	1			T1	204		T2	29		T3	32
values[0x0]	2101170	1			T1	23		T2	16		T3	13
values[0x1]	2429865	1			T1	25		T2	14		T3	17

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	320870	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5830550

1

T1

111

T2

35

T3

43

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25353	1			T4	1		T6	2		T40	1
valid_sources[0x01]	24404	1			T4	4		T6	3		T26	2
valid_sources[0x02]	25016	1			T6	2		T26	3		T183	2
valid_sources[0x03]	24247	1			T5	1		T6	3		T9	1
valid_sources[0x04]	24252	1			T17	1		T4	1		T6	4
valid_sources[0x05]	24497	1			T17	1		T4	3		T6	3
valid_sources[0x06]	23320	1			T2	1		T4	1		T6	1
valid_sources[0x07]	23503	1			T6	2		T26	1		T183	2
valid_sources[0x08]	23822	1			T4	1		T6	4		T30	1
valid_sources[0x09]	24578	1			T4	1		T22	2		T115	1
valid_sources[0x0a]	24340	1			T4	2		T6	1		T29	2
valid_sources[0x0b]	24867	1			T17	1		T6	1		T29	4
valid_sources[0x0c]	25122	1			T4	1		T6	4		T29	2
valid_sources[0x0d]	23620	1			T22	1		T30	4		T26	2
valid_sources[0x0e]	24039	1			T2	1		T4	2		T5	3
valid_sources[0x0f]	23611	1			T4	2		T6	4		T9	2
valid_sources[0x10]	24328	1			T17	2		T4	1		T6	4
valid_sources[0x11]	23486	1			T5	1		T40	1		T26	2
valid_sources[0x12]	23188	1			T4	1		T6	3		T26	2
valid_sources[0x13]	24195	1			T20	4		T6	4		T26	2
valid_sources[0x14]	24217	1			T4	1		T6	5		T29	1
valid_sources[0x15]	23611	1			T6	3		T193	1		T194	8
valid_sources[0x16]	24742	1			T4	2		T22	2		T6	1
valid_sources[0x17]	23866	1			T2	3		T6	4		T114	2
valid_sources[0x18]	23223	1			T4	1		T6	2		T26	1
valid_sources[0x19]	22797	1			T17	1		T4	1		T6	1
valid_sources[0x1a]	23934	1			T2	3		T4	4		T6	2
valid_sources[0x1b]	23305	1			T6	8		T26	1		T194	1
valid_sources[0x1c]	23294	1			T17	1		T4	1		T6	4
valid_sources[0x1d]	23898	1			T17	2		T6	3		T9	1
valid_sources[0x1e]	24138	1			T2	2		T6	2		T26	1
valid_sources[0x1f]	24460	1			T4	2		T6	2		T40	1
valid_sources[0x20]	24681	1			T26	1		T198	1		T194	1
valid_sources[0x21]	24246	1			T22	1		T6	3		T29	19
valid_sources[0x22]	24008	1			T6	3		T114	1		T26	1
valid_sources[0x23]	24534	1			T17	2		T4	2		T6	3
valid_sources[0x24]	23555	1			T6	5		T9	1		T193	1
valid_sources[0x25]	24659	1			T2	2		T17	1		T40	1
valid_sources[0x26]	23146	1			T17	1		T4	1		T6	2
valid_sources[0x27]	24017	1			T4	3		T6	4		T29	1
valid_sources[0x28]	25756	1			T4	1		T6	2		T9	1
valid_sources[0x29]	25497	1			T4	2		T22	4		T6	2
valid_sources[0x2a]	24905	1			T6	5		T9	1		T30	1
valid_sources[0x2b]	24855	1			T17	1		T4	2		T22	1
valid_sources[0x2c]	24254	1			T2	1		T17	1		T6	1
valid_sources[0x2d]	24375	1			T114	1		T115	2		T183	2
valid_sources[0x2e]	24997	1			T22	3		T6	3		T26	1
valid_sources[0x2f]	23077	1			T4	2		T6	1		T9	1
valid_sources[0x30]	25344	1			T4	4		T6	3		T183	1
valid_sources[0x31]	25158	1			T2	2		T4	1		T6	2
valid_sources[0x32]	24854	1			T193	5		T41	2		T27	1
valid_sources[0x33]	24497	1			T4	3		T22	2		T6	4
valid_sources[0x34]	23814	1			T4	3		T6	4		T40	1
valid_sources[0x35]	22891	1			T6	2		T115	4		T198	4
valid_sources[0x36]	24056	1			T17	1		T4	2		T6	2
valid_sources[0x37]	25486	1			T17	1		T6	4		T30	10
valid_sources[0x38]	23102	1			T6	5		T29	1		T9	1
valid_sources[0x39]	23913	1			T4	1		T6	3		T198	1
valid_sources[0x3a]	23682	1			T6	5		T26	1		T194	2
valid_sources[0x3b]	23647	1			T6	1		T26	1		T183	1
valid_sources[0x3c]	24928	1			T4	2		T6	4		T9	1
valid_sources[0x3d]	23642	1			T4	2		T6	3		T9	1
valid_sources[0x3e]	24241	1			T2	2		T17	2		T6	4
valid_sources[0x3f]	23006	1			T17	1		T4	1		T22	1
valid_sources[0x40]	23910	1			T22	5		T6	1		T40	1
valid_sources[0x41]	23701	1			T4	4		T6	1		T26	1
valid_sources[0x42]	24032	1			T4	1		T6	4		T9	1
valid_sources[0x43]	24167	1			T2	1		T4	1		T6	4
valid_sources[0x44]	23230	1			T3	1		T17	1		T6	2
valid_sources[0x45]	23826	1			T22	1		T6	4		T183	2
valid_sources[0x46]	23999	1			T5	2		T6	3		T26	1
valid_sources[0x47]	24640	1			T6	4		T26	2		T183	3
valid_sources[0x48]	24092	1			T17	2		T6	4		T26	1
valid_sources[0x49]	24877	1			T6	7		T26	2		T183	2
valid_sources[0x4a]	24708	1			T4	3		T6	3		T183	1
valid_sources[0x4b]	23983	1			T6	3		T29	29		T26	1
valid_sources[0x4c]	23569	1			T4	2		T22	1		T6	3
valid_sources[0x4d]	23286	1			T4	2		T6	4		T26	3
valid_sources[0x4e]	24685	1			T6	3		T26	2		T115	1
valid_sources[0x4f]	23601	1			T17	1		T4	1		T6	4
valid_sources[0x50]	23894	1			T17	1		T22	1		T6	3
valid_sources[0x51]	22597	1			T6	4		T29	14		T9	2
valid_sources[0x52]	24290	1			T3	1		T6	2		T26	2
valid_sources[0x53]	23855	1			T2	1		T17	1		T6	6
valid_sources[0x54]	23586	1			T4	2		T22	1		T6	3
valid_sources[0x55]	24861	1			T4	2		T6	1		T183	1
valid_sources[0x56]	23932	1			T5	1		T6	3		T9	1
valid_sources[0x57]	24345	1			T4	3		T6	3		T9	1
valid_sources[0x58]	24279	1			T4	2		T5	6		T22	6
valid_sources[0x59]	24118	1			T17	1		T4	1		T6	4
valid_sources[0x5a]	24482	1			T4	2		T6	1		T26	2
valid_sources[0x5b]	22989	1			T4	1		T6	7		T183	4
valid_sources[0x5c]	23219	1			T17	1		T4	3		T9	1
valid_sources[0x5d]	23698	1			T4	1		T6	2		T183	2
valid_sources[0x5e]	23784	1			T17	1		T4	1		T6	5
valid_sources[0x5f]	24928	1			T22	1		T6	1		T26	2
valid_sources[0x60]	23850	1			T29	6		T9	1		T26	1
valid_sources[0x61]	24023	1			T2	1		T17	1		T4	2
valid_sources[0x62]	23188	1			T2	2		T6	2		T26	2
valid_sources[0x63]	24198	1			T6	2		T183	3		T194	1
valid_sources[0x64]	23019	1			T22	1		T6	1		T26	4
valid_sources[0x65]	24742	1			T6	1		T29	11		T9	1
valid_sources[0x66]	24127	1			T17	2		T6	3		T26	1
valid_sources[0x67]	23759	1			T4	2		T22	2		T6	2
valid_sources[0x68]	24033	1			T2	2		T4	2		T6	3
valid_sources[0x69]	23581	1			T6	2		T40	1		T26	1
valid_sources[0x6a]	25109	1			T4	1		T6	4		T115	1
valid_sources[0x6b]	23996	1			T22	6		T6	3		T26	1
valid_sources[0x6c]	23418	1			T4	2		T5	7		T22	2
valid_sources[0x6d]	23956	1			T4	3		T22	2		T6	5
valid_sources[0x6e]	23945	1			T4	1		T6	2		T114	2
valid_sources[0x6f]	23659	1			T4	3		T6	1		T183	2
valid_sources[0x70]	22681	1			T4	1		T6	3		T26	1
valid_sources[0x71]	23913	1			T4	1		T26	1		T115	2
valid_sources[0x72]	24322	1			T3	1		T4	3		T22	1
valid_sources[0x73]	25512	1			T20	22		T4	1		T6	2
valid_sources[0x74]	23469	1			T4	1		T5	1		T6	5
valid_sources[0x75]	25246	1			T4	1		T6	3		T30	3
valid_sources[0x76]	22959	1			T17	3		T6	1		T28	3
valid_sources[0x77]	23177	1			T4	2		T6	2		T30	1
valid_sources[0x78]	24453	1			T4	1		T6	5		T26	3
valid_sources[0x79]	24209	1			T4	1		T6	3		T9	1
valid_sources[0x7a]	24412	1			T22	3		T6	5		T183	1
valid_sources[0x7b]	24086	1			T4	1		T6	1		T183	1
valid_sources[0x7c]	23484	1			T2	2		T4	1		T6	2
valid_sources[0x7d]	24548	1			T4	1		T22	1		T6	2
valid_sources[0x7e]	22772	1			T20	1		T4	2		T6	3
valid_sources[0x7f]	23690	1			T4	3		T6	2		T29	8
valid_sources[0x80]	23574	1			T2	3		T17	1		T22	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1382454

1

T1

2

T2

2

T3

3

values[0x0]

all_enables

biggest_size

2059191

1

T1

20

T2

12

T3

12

values[0x1]

all_enables

biggest_size

2058605

1

T1

22

T2

13

T3

15