Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	100.00	1	100	1	64	64

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	0	52	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	0	52	100.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
non_zero_bins[0]	2539	1		T1	19	T2	2	T3	2
non_zero_bins[1]	1832	1		T1	3	T2	1	T3	1
zero	8036	1		T1	2	T2	1	T3	2

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	491	1		T2	1	T6	2	T104	3
uni	3409	1		T1	1	T2	1	T3	2
gen	3857	1		T1	20	T2	1	T3	1
res	763	1		T1	2	T22	1	T6	2
ins	3887	1		T1	1	T2	1	T3	2

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8344

mubi_true

4063

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

6209

pass

6198

T17

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	0	52	100.00
Automatically Generated Cross Bins	52	0	52	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	non_zero_bins[0]	fail	mubi_false	49	1		T80	2	T102	1	T298	1
upd	non_zero_bins[0]	fail	mubi_true	59	1		T79	1	T80	2	T299	1
upd	non_zero_bins[0]	pass	mubi_false	64	1		T6	1	T79	2	T102	4
upd	non_zero_bins[0]	pass	mubi_true	58	1		T104	1	T79	1	T80	1
upd	non_zero_bins[1]	fail	mubi_false	36	1		T104	1	T80	1	T102	2
upd	non_zero_bins[1]	fail	mubi_true	47	1		T79	1	T80	1	T103	1
upd	non_zero_bins[1]	pass	mubi_false	38	1		T80	1	T103	1	T227	1
upd	non_zero_bins[1]	pass	mubi_true	41	1		T2	1	T103	1	T102	1
upd	zero	fail	mubi_false	19	1		T6	1	T56	1	T105	2
upd	zero	fail	mubi_true	34	1		T104	1	T300	1	T86	1
upd	zero	pass	mubi_false	26	1		T79	1	T80	1	T102	2
upd	zero	pass	mubi_true	20	1		T79	3	T298	1	T105	3
uni	zero	fail	mubi_false	1248	1		T2	1	T3	1	T22	1
uni	zero	fail	mubi_true	461	1		T3	1	T20	1	T79	8
uni	zero	pass	mubi_false	1262	1		T1	1	T6	3	T29	1
uni	zero	pass	mubi_true	438	1		T6	1	T104	1	T79	5
gen	non_zero_bins[0]	fail	mubi_false	256	1		T6	1	T29	1	T79	3
gen	non_zero_bins[0]	fail	mubi_true	263	1		T1	11	T2	1	T3	1
gen	non_zero_bins[0]	pass	mubi_false	241	1		T79	4	T80	4	T103	1
gen	non_zero_bins[0]	pass	mubi_true	222	1		T1	8	T6	1	T9	3
gen	non_zero_bins[1]	fail	mubi_false	167	1		T6	1	T79	2	T299	1
gen	non_zero_bins[1]	fail	mubi_true	193	1		T1	1	T9	1	T104	1
gen	non_zero_bins[1]	pass	mubi_false	151	1		T104	1	T79	2	T80	4
gen	non_zero_bins[1]	pass	mubi_true	205	1		T104	1	T79	2	T80	5
gen	zero	fail	mubi_false	858	1		T20	1	T6	2	T36	1
gen	zero	fail	mubi_true	233	1		T17	1	T18	2	T25	1
gen	zero	pass	mubi_false	855	1		T5	1	T6	3	T71	1
gen	zero	pass	mubi_true	213	1		T17	1	T21	2	T31	1
res	non_zero_bins[0]	fail	mubi_false	87	1		T22	1	T29	1	T102	1
res	non_zero_bins[0]	fail	mubi_true	98	1		T6	1	T9	2	T80	2
res	non_zero_bins[0]	pass	mubi_false	88	1		T104	1	T79	3	T80	3
res	non_zero_bins[0]	pass	mubi_true	101	1		T79	1	T80	1	T102	3
res	non_zero_bins[1]	fail	mubi_false	53	1		T6	1	T102	1	T117	1
res	non_zero_bins[1]	fail	mubi_true	68	1		T104	1	T79	1	T80	1
res	non_zero_bins[1]	pass	mubi_false	60	1		T1	2	T102	2	T101	2
res	non_zero_bins[1]	pass	mubi_true	54	1		T68	1	T80	1	T101	1
res	zero	fail	mubi_false	36	1		T80	1	T37	1	T105	2
res	zero	fail	mubi_true	33	1		T80	2	T301	2	T298	1
res	zero	pass	mubi_false	43	1		T264	1	T37	1	T11	1
res	zero	pass	mubi_true	42	1		T79	1	T80	1	T105	2
ins	non_zero_bins[0]	fail	mubi_false	263	1		T3	1	T22	1	T6	1
ins	non_zero_bins[0]	fail	mubi_true	230	1		T2	1	T6	1	T9	1
ins	non_zero_bins[0]	pass	mubi_false	253	1		T6	1	T68	1	T79	4
ins	non_zero_bins[0]	pass	mubi_true	207	1		T104	1	T79	4	T80	2
ins	non_zero_bins[1]	fail	mubi_false	177	1		T104	1	T79	2	T80	2
ins	non_zero_bins[1]	fail	mubi_true	158	1		T3	1	T104	1	T79	4
ins	non_zero_bins[1]	pass	mubi_false	205	1		T6	2	T31	1	T104	1
ins	non_zero_bins[1]	pass	mubi_true	179	1		T79	2	T80	6	T103	1
ins	zero	fail	mubi_false	884	1		T6	1	T104	1	T79	11
ins	zero	fail	mubi_true	199	1		T18	1	T29	1	T25	1
ins	zero	pass	mubi_false	925	1		T1	1	T20	1	T5	1
ins	zero	pass	mubi_true	207	1		T17	1	T21	2	T6	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded