Group : csrng_agent_pkg::device_genbits_cg
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Group : csrng_agent_pkg::device_genbits_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
csrng_agent_pkg.csrng_device_genbits_cg 100.00 1 100 1 64 64




Group Instance : csrng_agent_pkg.csrng_device_genbits_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance csrng_agent_pkg.csrng_device_genbits_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group Instance csrng_agent_pkg.csrng_device_genbits_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csrng_glen 4 0 4 100.00 100 1 1 0
csrng_sts 2 0 2 100.00 100 1 1 0


Crosses for Group Instance csrng_agent_pkg.csrng_device_genbits_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
csrng_genbits_cross 8 0 8 100.00 100 1 1 0


Summary for Variable csrng_glen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for csrng_glen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
glens[0] 2291 1 T1 19 T2 1 T3 1
glens[1] 43 1 T31 1 T299 1 T35 1
glens[2] 34 1 T301 3 T10 1 T11 1
glens[3] 19 1 T33 1 T34 1 T66 1



Summary for Variable csrng_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_sts

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fail 1970 1 T1 12 T2 1 T3 1
pass 1887 1 T1 8 T17 1 T21 2



Summary for Cross csrng_genbits_cross

Samples crossed: csrng_glen csrng_sts
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for csrng_genbits_cross

Bins
csrng_glencsrng_stsCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
glens[0] fail 1184 1 T1 11 T2 1 T3 1
glens[0] pass 1107 1 T1 8 T17 1 T21 2
glens[1] fail 15 1 T299 1 T301 1 T302 1
glens[1] pass 28 1 T31 1 T35 1 T12 1
glens[2] fail 23 1 T10 1 T11 1 T303 1
glens[2] pass 11 1 T301 3 T286 1 T304 1
glens[3] fail 9 1 T34 1 T305 1 T306 1
glens[3] pass 10 1 T33 1 T66 1 T307 1

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