Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	100.00	100.00	100.00		100.00	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T39,T76

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T25
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T130
AckPls->Error	99	Covered	T5,T226,T48
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T50,T108,T151
DataWait->Error	99	Covered	T71,T60,T44
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T23,T24
EndPointClear->Disabled	107	Covered	T227,T228,T173
EndPointClear->Error	99	Covered	T4,T70,T145
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T21,T6,T104
Idle->Error	99	Covered	T5,T25,T36

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T4,T5,T25
default	-	-	-	-	Covered	T4,T25,T7

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T25
0	1	Covered	T21,T39,T76
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1473719387	859675	0	0
FpvSecCmErrorStEscalate_A	1473719387	864358	0	0
u_state_regs_A	1473675898	1472710675	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1473719387	859675	0	0
T4	5383	2568	0	0
T5	13468	7770	0	0
T6	69580	0	0	0
T7	0	7720	0	0
T8	0	4963	0	0
T9	11396	0	0	0
T21	7308	0	0	0
T22	14945	0	0	0
T25	13132	7804	0	0
T29	11697	0	0	0
T30	9065	0	0	0
T31	7539	0	0	0
T36	0	2296	0	0
T70	0	8148	0	0
T71	0	4130	0	0
T72	0	4136	0	0
T129	0	2638	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1473719387	864358	0	0
T4	5383	2575	0	0
T5	13468	7777	0	0
T6	69580	0	0	0
T7	0	7727	0	0
T8	0	4970	0	0
T9	11396	0	0	0
T21	7308	0	0	0
T22	14945	0	0	0
T25	13132	7811	0	0
T29	11697	0	0	0
T30	9065	0	0	0
T31	7539	0	0	0
T36	0	2303	0	0
T70	0	8155	0	0
T71	0	4137	0	0
T72	0	4143	0	0
T129	0	2645	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1473675898	1472710675	0	0
T1	16968	16548	0	0
T2	12628	11949	0	0
T3	9583	8974	0	0
T4	5259	4321	0	0
T5	13299	12137	0	0
T17	10213	9520	0	0
T18	10801	10416	0	0
T20	8687	8155	0	0
T21	7308	6769	0	0
T22	14945	14371	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T39,T76

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T22,T29
DataWait	75	Covered	T3,T22,T29
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T25
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T22,T29
DataWait->AckPls	80	Covered	T3,T22,T29
DataWait->Disabled	107	Covered	T120,T229,T167
DataWait->Error	99	Covered	T71,T136,T230
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T23,T24
EndPointClear->Disabled	107	Covered	T227,T228,T173
EndPointClear->Error	99	Covered	T4,T70,T145
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T22,T29
Idle->Disabled	107	Covered	T21,T6,T104
Idle->Error	99	Covered	T5,T25,T36

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T22,T29
Idle	-	1	0	-	Covered	T3,T22,T29
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T22,T29
DataWait	-	-	-	0	Covered	T3,T22,T29
AckPls	-	-	-	-	Covered	T3,T22,T29
Error	-	-	-	-	Covered	T4,T5,T25
default	-	-	-	-	Covered	T15,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T25
0	1	Covered	T21,T39,T76
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	210531341	123125	0	0
FpvSecCmErrorStEscalate_A	210531341	123794	0	0
u_state_regs_A	210531341	210393452	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	123125	0	0
T4	769	374	0	0
T5	1924	1110	0	0
T6	9940	0	0	0
T7	0	1110	0	0
T8	0	709	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1122	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	328	0	0
T70	0	1164	0	0
T71	0	590	0	0
T72	0	598	0	0
T129	0	384	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	123794	0	0
T4	769	375	0	0
T5	1924	1111	0	0
T6	9940	0	0	0
T7	0	1111	0	0
T8	0	710	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1123	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	329	0	0
T70	0	1165	0	0
T71	0	591	0	0
T72	0	599	0	0
T129	0	385	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T39,T76

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T22,T29,T30
DataWait	75	Covered	T22,T29,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T25
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T22,T29,T30
DataWait->AckPls	80	Covered	T22,T29,T30
DataWait->Disabled	107	Covered	T50,T151,T231
DataWait->Error	99	Covered	T162,T180,T232
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T23,T24
EndPointClear->Disabled	107	Covered	T227,T228,T173
EndPointClear->Error	99	Covered	T4,T70,T145
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T22,T29,T30
Idle->Disabled	107	Covered	T21,T6,T104
Idle->Error	99	Covered	T5,T25,T36

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T22,T29,T30
Idle	-	1	0	-	Covered	T22,T29,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T22,T29,T30
DataWait	-	-	-	0	Covered	T22,T29,T30
AckPls	-	-	-	-	Covered	T22,T29,T30
Error	-	-	-	-	Covered	T4,T5,T25
default	-	-	-	-	Covered	T15,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T25
0	1	Covered	T21,T39,T76
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	210531341	123125	0	0
FpvSecCmErrorStEscalate_A	210531341	123794	0	0
u_state_regs_A	210531341	210393452	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	123125	0	0
T4	769	374	0	0
T5	1924	1110	0	0
T6	9940	0	0	0
T7	0	1110	0	0
T8	0	709	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1122	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	328	0	0
T70	0	1164	0	0
T71	0	590	0	0
T72	0	598	0	0
T129	0	384	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	123794	0	0
T4	769	375	0	0
T5	1924	1111	0	0
T6	9940	0	0	0
T7	0	1111	0	0
T8	0	710	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1123	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	329	0	0
T70	0	1165	0	0
T71	0	591	0	0
T72	0	599	0	0
T129	0	385	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T39,T76

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T25
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T5,T226,T233
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T108,T109,T181
DataWait->Error	99	Covered	T60,T44,T159
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T23,T24
EndPointClear->Disabled	107	Covered	T227,T228,T173
EndPointClear->Error	99	Covered	T70,T234,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T21,T6,T104
Idle->Error	99	Covered	T36,T71,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T4,T5,T25
default	-	-	-	-	Covered	T4,T25,T7

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T25
0	1	Covered	T21,T39,T76
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	210531341	120925	0	0
FpvSecCmErrorStEscalate_A	210531341	121594	0	0
u_state_regs_A	210487852	210349963	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	120925	0	0
T4	769	324	0	0
T5	1924	1110	0	0
T6	9940	0	0	0
T7	0	1060	0	0
T8	0	709	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1072	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	328	0	0
T70	0	1164	0	0
T71	0	590	0	0
T72	0	548	0	0
T129	0	334	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	121594	0	0
T4	769	325	0	0
T5	1924	1111	0	0
T6	9940	0	0	0
T7	0	1061	0	0
T8	0	710	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1073	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	329	0	0
T70	0	1165	0	0
T71	0	591	0	0
T72	0	549	0	0
T129	0	335	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210487852	210349963	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	645	511	0	0
T5	1755	1589	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T39,T76

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T17,T29
DataWait	75	Covered	T1,T17,T29
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T25
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T235
AckPls->Idle	85	Covered	T1,T17,T29
DataWait->AckPls	80	Covered	T1,T17,T29
DataWait->Disabled	107	Covered	T138,T182,T236
DataWait->Error	99	Covered	T237,T238
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T23,T24
EndPointClear->Disabled	107	Covered	T227,T228,T173
EndPointClear->Error	99	Covered	T4,T70,T145
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T17,T29
Idle->Disabled	107	Covered	T21,T6,T104
Idle->Error	99	Covered	T5,T25,T36

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T17,T29
Idle	-	1	0	-	Covered	T1,T17,T29
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T17,T29
DataWait	-	-	-	0	Covered	T1,T17,T29
AckPls	-	-	-	-	Covered	T1,T17,T29
Error	-	-	-	-	Covered	T4,T5,T25
default	-	-	-	-	Covered	T15,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T25
0	1	Covered	T21,T39,T76
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	210531341	123125	0	0
FpvSecCmErrorStEscalate_A	210531341	123794	0	0
u_state_regs_A	210531341	210393452	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	123125	0	0
T4	769	374	0	0
T5	1924	1110	0	0
T6	9940	0	0	0
T7	0	1110	0	0
T8	0	709	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1122	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	328	0	0
T70	0	1164	0	0
T71	0	590	0	0
T72	0	598	0	0
T129	0	384	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	123794	0	0
T4	769	375	0	0
T5	1924	1111	0	0
T6	9940	0	0	0
T7	0	1111	0	0
T8	0	710	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1123	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	329	0	0
T70	0	1165	0	0
T71	0	591	0	0
T72	0	599	0	0
T129	0	385	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T39,T76

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T22,T30
DataWait	75	Covered	T1,T22,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T25
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T48
AckPls->Idle	85	Covered	T1,T22,T30
DataWait->AckPls	80	Covered	T1,T22,T30
DataWait->Disabled	107	Covered	T77,T239
DataWait->Error	99	Covered	T46,T176,T240
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T23,T24
EndPointClear->Disabled	107	Covered	T227,T228,T173
EndPointClear->Error	99	Covered	T4,T70,T145
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T22,T30
Idle->Disabled	107	Covered	T21,T6,T104
Idle->Error	99	Covered	T5,T25,T36

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T22,T30
Idle	-	1	0	-	Covered	T1,T22,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T22,T30
DataWait	-	-	-	0	Covered	T1,T22,T30
AckPls	-	-	-	-	Covered	T1,T22,T30
Error	-	-	-	-	Covered	T4,T5,T25
default	-	-	-	-	Covered	T15,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T25
0	1	Covered	T21,T39,T76
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	210531341	123125	0	0
FpvSecCmErrorStEscalate_A	210531341	123794	0	0
u_state_regs_A	210531341	210393452	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	123125	0	0
T4	769	374	0	0
T5	1924	1110	0	0
T6	9940	0	0	0
T7	0	1110	0	0
T8	0	709	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1122	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	328	0	0
T70	0	1164	0	0
T71	0	590	0	0
T72	0	598	0	0
T129	0	384	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	123794	0	0
T4	769	375	0	0
T5	1924	1111	0	0
T6	9940	0	0	0
T7	0	1111	0	0
T8	0	710	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1123	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	329	0	0
T70	0	1165	0	0
T71	0	591	0	0
T72	0	599	0	0
T129	0	385	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T39,T76

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T18,T31
DataWait	75	Covered	T1,T18,T31
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T25
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T241
AckPls->Idle	85	Covered	T1,T18,T31
DataWait->AckPls	80	Covered	T1,T18,T31
DataWait->Disabled	107	Covered	T242,T113,T243
DataWait->Error	99	Covered	T116,T244,T245
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T23,T24
EndPointClear->Disabled	107	Covered	T227,T228,T173
EndPointClear->Error	99	Covered	T4,T70,T145
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T18,T31
Idle->Disabled	107	Covered	T21,T6,T104
Idle->Error	99	Covered	T5,T25,T36

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T18,T31
Idle	-	1	0	-	Covered	T1,T18,T31
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T18,T31
DataWait	-	-	-	0	Covered	T1,T18,T31
AckPls	-	-	-	-	Covered	T1,T18,T31
Error	-	-	-	-	Covered	T4,T5,T25
default	-	-	-	-	Covered	T15,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T25
0	1	Covered	T21,T39,T76
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	210531341	123125	0	0
FpvSecCmErrorStEscalate_A	210531341	123794	0	0
u_state_regs_A	210531341	210393452	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	123125	0	0
T4	769	374	0	0
T5	1924	1110	0	0
T6	9940	0	0	0
T7	0	1110	0	0
T8	0	709	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1122	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	328	0	0
T70	0	1164	0	0
T71	0	590	0	0
T72	0	598	0	0
T129	0	384	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	123794	0	0
T4	769	375	0	0
T5	1924	1111	0	0
T6	9940	0	0	0
T7	0	1111	0	0
T8	0	710	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1123	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	329	0	0
T70	0	1165	0	0
T71	0	591	0	0
T72	0	599	0	0
T129	0	385	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T39,T76

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T22,T30
DataWait	75	Covered	T1,T22,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T25
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T130
AckPls->Error	99	Covered	T246
AckPls->Idle	85	Covered	T1,T22,T30
DataWait->AckPls	80	Covered	T1,T22,T30
DataWait->Disabled	107	Covered	T152,T157,T247
DataWait->Error	99	Covered	T14,T248
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T23,T24
EndPointClear->Disabled	107	Covered	T227,T228,T173
EndPointClear->Error	99	Covered	T4,T70,T145
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T22,T30
Idle->Disabled	107	Covered	T21,T6,T104
Idle->Error	99	Covered	T5,T25,T36

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T22,T30
Idle	-	1	0	-	Covered	T1,T22,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T22,T30
DataWait	-	-	-	0	Covered	T1,T22,T30
AckPls	-	-	-	-	Covered	T1,T22,T30
Error	-	-	-	-	Covered	T4,T5,T25
default	-	-	-	-	Covered	T15,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T25
0	1	Covered	T21,T39,T76
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	210531341	123125	0	0
FpvSecCmErrorStEscalate_A	210531341	123794	0	0
u_state_regs_A	210531341	210393452	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	123125	0	0
T4	769	374	0	0
T5	1924	1110	0	0
T6	9940	0	0	0
T7	0	1110	0	0
T8	0	709	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1122	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	328	0	0
T70	0	1164	0	0
T71	0	590	0	0
T72	0	598	0	0
T129	0	384	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	123794	0	0
T4	769	375	0	0
T5	1924	1111	0	0
T6	9940	0	0	0
T7	0	1111	0	0
T8	0	710	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1123	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	329	0	0
T70	0	1165	0	0
T71	0	591	0	0
T72	0	599	0	0
T129	0	385	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0