Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_output	89.81	100.00	69.23			90.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	97.12	100.00	88.46			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	97.12	100.00	88.46			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.81	100.00	69.23			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.06	100.00	69.23			95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T9

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T48,T95,T116
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T39,T73,T88
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T9

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T9
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	631226061	494927	0	0
DepthKnown_A	631594023	631180356	0	0
RvalidKnown_A	631594023	631180356	0	0
WreadyKnown_A	631594023	631180356	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	631594023	545424	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631226061	494927	0	0
T1	7272	2057	0	0
T2	5412	30	0	0
T3	4107	29	0	0
T4	1041	73	0	0
T5	2224	2	0	0
T6	0	129	0	0
T7	0	367	0	0
T8	0	132	0	0
T9	0	952	0	0
T13	0	1095	0	0
T17	4377	4	0	0
T18	4629	4	0	0
T20	3723	3	0	0
T21	3132	50	0	0
T22	6405	22	0	0
T25	0	5	0	0
T32	0	9	0	0
T76	0	46	0	0
T81	0	1341	0	0
T84	0	2936	0	0
T117	0	4480	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631594023	631180356	0	0
T1	7272	7092	0	0
T2	5412	5121	0	0
T3	4107	3846	0	0
T4	2307	1905	0	0
T5	5772	5274	0	0
T17	4377	4080	0	0
T18	4629	4464	0	0
T20	3723	3495	0	0
T21	3132	2901	0	0
T22	6405	6159	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631594023	631180356	0	0
T1	7272	7092	0	0
T2	5412	5121	0	0
T3	4107	3846	0	0
T4	2307	1905	0	0
T5	5772	5274	0	0
T17	4377	4080	0	0
T18	4629	4464	0	0
T20	3723	3495	0	0
T21	3132	2901	0	0
T22	6405	6159	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631594023	631180356	0	0
T1	7272	7092	0	0
T2	5412	5121	0	0
T3	4107	3846	0	0
T4	2307	1905	0	0
T5	5772	5274	0	0
T17	4377	4080	0	0
T18	4629	4464	0	0
T20	3723	3495	0	0
T21	3132	2901	0	0
T22	6405	6159	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	631594023	545424	0	0
T1	7272	2057	0	0
T2	5412	30	0	0
T3	4107	29	0	0
T4	2307	604	0	0
T5	5772	2	0	0
T6	0	129	0	0
T7	0	4096	0	0
T9	0	952	0	0
T13	0	1095	0	0
T17	4377	4	0	0
T18	4629	4	0	0
T20	3723	3	0	0
T21	3132	50	0	0
T22	6405	22	0	0
T25	0	174	0	0
T32	0	9	0	0
T71	0	74	0	0
T76	0	46	0	0
T81	0	1341	0	0
T84	0	1430	0	0
T117	0	4480	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output

	Total	Covered	Percent
Conditions	26	18	69.23
Logical	26	18	69.23
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	210531341	57513	0	0
DepthKnown_A	210531341	210393452	0	0
RvalidKnown_A	210531341	210393452	0	0
WreadyKnown_A	210531341	210393452	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	210531341	57513	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	57513	0	0
T1	2424	108	0	0
T2	1804	30	0	0
T3	1369	29	0	0
T4	769	0	0	0
T5	1924	2	0	0
T6	0	129	0	0
T17	1459	4	0	0
T18	1543	4	0	0
T20	1241	3	0	0
T21	1044	4	0	0
T22	2135	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	57513	0	0
T1	2424	108	0	0
T2	1804	30	0	0
T3	1369	29	0	0
T4	769	0	0	0
T5	1924	2	0	0
T6	0	129	0	0
T17	1459	4	0	0
T18	1543	4	0	0
T20	1241	3	0	0
T21	1044	4	0	0
T22	2135	22	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T84,T12,T112

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T9,T117
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T9,T117
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T48,T95,T116
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T9

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T39,T88,T97
1	0	1	Covered	T1,T4,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T9,T13

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T84,T12,T112
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T9

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T84,T12,T112

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T84,T12,T112
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T9,T117

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T9

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	210347360	211538	0	0
DepthKnown_A	210531341	210393452	0	0
RvalidKnown_A	210531341	210393452	0	0
WreadyKnown_A	210531341	210393452	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	210531341	234686	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210347360	211538	0	0
T1	2424	972	0	0
T2	1804	0	0	0
T3	1369	0	0	0
T4	136	33	0	0
T5	150	0	0	0
T7	0	108	0	0
T8	0	132	0	0
T9	0	452	0	0
T13	0	505	0	0
T17	1459	0	0	0
T18	1543	0	0	0
T20	1241	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T77	0	1761	0	0
T81	0	1341	0	0
T84	0	1430	0	0
T117	0	4480	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	234686	0	0
T1	2424	972	0	0
T2	1804	0	0	0
T3	1369	0	0	0
T4	769	288	0	0
T5	1924	0	0	0
T7	0	1941	0	0
T8	0	774	0	0
T9	0	452	0	0
T13	0	505	0	0
T17	1459	0	0	0
T18	1543	0	0	0
T20	1241	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T77	0	1761	0	0
T81	0	1341	0	0
T84	0	1430	0	0
T117	0	4480	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T9

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T13,T7
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T13,T7
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T91,T92,T93
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T21

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T73,T90,T96
1	0	1	Covered	T1,T4,T21
1	1	0	Not Covered
1	1	1	Covered	T1,T21,T9

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T21

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T9

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T21
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T9
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T13,T7

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T21

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T21
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	210347360	225876	0	0
DepthKnown_A	210531341	210393452	0	0
RvalidKnown_A	210531341	210393452	0	0
WreadyKnown_A	210531341	210393452	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	210531341	253225	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210347360	225876	0	0
T1	2424	977	0	0
T2	1804	0	0	0
T3	1369	0	0	0
T4	136	40	0	0
T5	150	0	0	0
T7	0	259	0	0
T9	0	500	0	0
T13	0	590	0	0
T17	1459	0	0	0
T18	1543	0	0	0
T20	1241	0	0	0
T21	1044	46	0	0
T22	2135	0	0	0
T25	0	5	0	0
T32	0	9	0	0
T76	0	46	0	0
T84	0	1506	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	253225	0	0
T1	2424	977	0	0
T2	1804	0	0	0
T3	1369	0	0	0
T4	769	316	0	0
T5	1924	0	0	0
T7	0	2155	0	0
T9	0	500	0	0
T13	0	590	0	0
T17	1459	0	0	0
T18	1543	0	0	0
T20	1241	0	0	0
T21	1044	46	0	0
T22	2135	0	0	0
T25	0	174	0	0
T32	0	9	0	0
T71	0	74	0	0
T76	0	46	0	0