Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
98.53 98.53 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cs_cmds_cg 98.53 1 100 1 64 64



Group Instance : edn_cs_cmds_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
98.53 1 100 1 64 64



Summary for Group Instance edn_cs_cmds_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 19 0 19 100.00
Crosses 49 1 48 97.96


Variables for Group Instance edn_cs_cmds_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acmd 5 0 5 100.00 100 1 1 0
cp_clen 2 0 2 100.00 100 1 1 0
cp_cmd_src 5 0 5 100.00 100 1 1 0
cp_flags 2 0 2 100.00 100 1 1 0
cp_glen 2 0 2 100.00 100 1 1 0
cp_mode 3 0 3 100.00 100 1 1 0


Crosses for Group Instance edn_cs_cmds_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_generate_intended 13 0 13 100.00 100 1 1 0
cr_instantiate_intended 13 0 13 100.00 100 1 1 0
cr_reseed_intended 12 1 11 91.67 100 1 1 0
cr_update_intended 4 0 4 100.00 100 1 1 0
cr_uninstantiate_intended 2 0 2 100.00 100 1 1 0
cr_acmd_mode_cmd_src_unintended 5 0 5 100.00 100 1 1 0


Summary for Variable cp_acmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for cp_acmd

Excluded/Illegal bins
NAMECOUNTSTATUS
auto[INV] 0 Excluded
auto[GENB] 0 Excluded
auto[GENU] 0 Excluded
unused 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] 3892 1 T1 1 T2 1 T3 1
auto[RES] 839 1 T22 11 T23 1 T8 1
auto[GEN] 3656 1 T1 1 T2 1 T3 1
auto[UPD] 529 1 T22 6 T33 1 T58 1
auto[UNI] 3552 1 T1 1 T21 2 T22 41


Summary for Variable cp_clen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_clen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
some_cmd_data 4400 1 T21 1 T22 53 T23 1
no_cmd_data 8068 1 T1 3 T2 2 T3 2


Summary for Variable cp_cmd_src

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for cp_cmd_src

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_cmd_req 11459 1 T1 3 T2 2 T3 2
reseed_cmd 295 1 T8 1 T5 3 T9 1
generate_cmd 256 1 T8 1 T5 2 T9 1
boot_gen_cmd 229 1 T20 1 T4 2 T31 1
boot_ins_cmd 229 1 T20 1 T4 2 T31 1


Summary for Variable cp_flags

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_flags

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
true 4015 1 T1 1 T20 1 T4 1
false 8453 1 T1 2 T2 2 T3 2


Summary for Variable cp_glen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_glen

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
multiple 1128 1 T20 1 T4 2 T21 2
one 1832 1 T1 1 T2 1 T3 1


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_mode 10816 1 T1 3 T2 2 T3 2
boot_mode 671 1 T20 2 T4 4 T31 4
auto_mode 981 1 T17 3 T8 4 T5 6


Summary for Cross cr_generate_intended

Samples crossed: cp_acmd cp_clen cp_glen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 13 0 13 100.00
Automatically Generated Cross Bins 13 0 13 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_generate_intended

Excluded/Illegal bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[GEN] some_cmd_data multiple sw_mode sw_cmd_req 122 1 T8 1 T9 1 T32 1
auto[GEN] some_cmd_data multiple boot_mode sw_cmd_req 53 1 T31 1 T37 1 T77 1
auto[GEN] some_cmd_data multiple auto_mode generate_cmd 83 1 T8 1 T5 1 T13 2
auto[GEN] some_cmd_data one sw_mode sw_cmd_req 38 1 T24 1 T265 1 T293 1
auto[GEN] some_cmd_data one boot_mode sw_cmd_req 19 1 T294 1 T295 1 T296 1
auto[GEN] some_cmd_data one auto_mode generate_cmd 129 1 T42 1 T6 2 T80 1
auto[GEN] no_cmd_data multiple sw_mode sw_cmd_req 37 1 T21 1 T23 1 T33 1
auto[GEN] no_cmd_data multiple boot_mode sw_cmd_req 13 1 T297 1 T298 1 T299 1
auto[GEN] no_cmd_data multiple boot_mode boot_gen_cmd 66 1 T31 1 T37 1 T77 1
auto[GEN] no_cmd_data multiple auto_mode generate_cmd 15 1 T5 1 T9 1 T74 1
auto[GEN] no_cmd_data one sw_mode sw_cmd_req 1408 1 T1 1 T2 1 T3 1
auto[GEN] no_cmd_data one boot_mode sw_cmd_req 7 1 T57 1 T300 1 T301 1
auto[GEN] no_cmd_data one auto_mode generate_cmd 29 1 T80 1 T81 1 T302 1


User Defined Cross Bins for cr_generate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_gen 0 Excluded
gen_auto_wrong_src 0 Excluded
gen_boot_wrong_src 0 Excluded
gen_boot_seq_wrong_clen 0 Excluded
gen_boot_seq_wrong_glen 0 Excluded
gen_sw_wrong_src 0 Excluded


Summary for Cross cr_instantiate_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 13 0 13 100.00
Automatically Generated Cross Bins 13 0 13 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] some_cmd_data true sw_mode sw_cmd_req 809 1 T22 13 T58 2 T303 1
auto[INS] some_cmd_data true boot_mode sw_cmd_req 9 1 T77 1 T286 1 T304 1
auto[INS] some_cmd_data true auto_mode sw_cmd_req 75 1 T13 1 T38 1 T80 1
auto[INS] some_cmd_data false sw_mode sw_cmd_req 778 1 T21 1 T22 7 T23 1
auto[INS] some_cmd_data false boot_mode sw_cmd_req 12 1 T57 1 T40 1 T296 1
auto[INS] some_cmd_data false auto_mode sw_cmd_req 78 1 T9 1 T13 1 T32 1
auto[INS] no_cmd_data true sw_mode sw_cmd_req 172 1 T21 1 T22 3 T59 1
auto[INS] no_cmd_data true boot_mode sw_cmd_req 6 1 T305 1 T306 1 T307 1
auto[INS] no_cmd_data true auto_mode sw_cmd_req 61 1 T17 1 T8 1 T18 1
auto[INS] no_cmd_data false sw_mode sw_cmd_req 1618 1 T1 1 T2 1 T3 1
auto[INS] no_cmd_data false boot_mode sw_cmd_req 2 1 T308 1 T309 1 - -
auto[INS] no_cmd_data false boot_mode boot_ins_cmd 130 1 T20 1 T4 1 T15 2
auto[INS] no_cmd_data false auto_mode sw_cmd_req 43 1 T5 1 T6 1 T80 1


User Defined Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_ins 0 Excluded
ins_auto_wrong_src 0 Excluded
ins_boot_wrong_src 0 Excluded
ins_boot_seq_wrong_clen 0 Excluded
ins_boot_seq_wrong_flag0 0 Excluded
ins_sw_wrong_src 0 Excluded


Summary for Cross cr_reseed_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 12 1 11 91.67 1
Automatically Generated Cross Bins 12 1 11 91.67 1
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_reseed_intended

Uncovered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTNUMBERSTATUS
[auto[RES]] [no_cmd_data] [true] [boot_mode] [sw_cmd_req] 0 1 1


Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[RES] some_cmd_data true sw_mode sw_cmd_req 209 1 T22 6 T58 2 T99 2
auto[RES] some_cmd_data true boot_mode sw_cmd_req 13 1 T295 1 T310 1 T269 1
auto[RES] some_cmd_data true auto_mode reseed_cmd 98 1 T9 1 T6 1 T38 1
auto[RES] some_cmd_data false sw_mode sw_cmd_req 191 1 T22 3 T59 1 T99 3
auto[RES] some_cmd_data false boot_mode sw_cmd_req 13 1 T31 1 T311 1 T297 1
auto[RES] some_cmd_data false auto_mode reseed_cmd 99 1 T8 1 T13 2 T32 1
auto[RES] no_cmd_data true sw_mode sw_cmd_req 50 1 T23 1 T58 1 T106 1
auto[RES] no_cmd_data true auto_mode reseed_cmd 32 1 T5 1 T80 1 T48 1
auto[RES] no_cmd_data false sw_mode sw_cmd_req 51 1 T22 2 T99 1 T100 1
auto[RES] no_cmd_data false boot_mode sw_cmd_req 2 1 T312 1 T313 1 - -
auto[RES] no_cmd_data false auto_mode reseed_cmd 66 1 T5 2 T6 1 T74 1


User Defined Cross Bins for cr_reseed_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_res 0 Excluded
res_auto_wrong_src 0 Excluded
res_boot_wrong_src 0 Excluded
res_sw_wrong_src 0 Excluded


Summary for Cross cr_update_intended

Samples crossed: cp_acmd cp_clen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_update_intended

Excluded/Illegal bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)


Covered bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UPD] some_cmd_data sw_mode sw_cmd_req 399 1 T22 5 T58 1 T99 6
auto[UPD] some_cmd_data boot_mode sw_cmd_req 23 1 T37 1 T75 1 T294 1
auto[UPD] no_cmd_data sw_mode sw_cmd_req 77 1 T22 1 T33 1 T102 1
auto[UPD] no_cmd_data boot_mode sw_cmd_req 12 1 T101 1 T300 1 T272 1


User Defined Cross Bins for cr_update_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_upd 0 Excluded
upd_auto_wrong_src 0 Excluded
upd_boot_wrong_src 0 Excluded
upd_sw_wrong_src 0 Excluded


Summary for Cross cr_uninstantiate_intended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UNI] sw_mode sw_cmd_req 3503 1 T1 1 T21 2 T22 41
auto[UNI] boot_mode sw_cmd_req 29 1 T57 1 T77 1 T40 1


User Defined Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_uni 0 Excluded
uni_auto_wrong_src 0 Excluded
uni_boot_wrong_src 0 Excluded
uni_sw_wrong_src 0 Excluded


Summary for Cross cr_acmd_mode_cmd_src_unintended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 5 0 5 100.00
Automatically Generated Cross Bins 5 0 5 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] auto_mode sw_cmd_req 257 1 T17 1 T8 1 T5 1
auto[RES] auto_mode sw_cmd_req 15 1 T265 1 T12 1 T314 1
auto[GEN] auto_mode sw_cmd_req 120 1 T17 2 T8 1 T32 1
auto[UPD] auto_mode sw_cmd_req 18 1 T42 1 T10 1 T11 1
auto[UNI] auto_mode sw_cmd_req 20 1 T9 1 T85 1 T315 1


User Defined Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_sw_cmd 0 Excluded
not_auto_mode 0 Excluded

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