Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	623583	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5317017

1

T1

5

T2

6

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1559508	1			T1	18		T2	19		T3	16
values[0x0]	2032430	1			T1	4		T2	5		T3	9
values[0x1]	2348662	1			T1	3		T2	5		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	306335	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5634265

1

T1

10

T2

12

T3

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23184	1			T22	585		T194	1		T29	1
valid_sources[0x01]	23143	1			T22	505		T17	2		T29	5
valid_sources[0x02]	21416	1			T22	595		T30	2		T171	1
valid_sources[0x03]	22857	1			T22	477		T29	1		T171	4
valid_sources[0x04]	23464	1			T1	1		T22	548		T17	1
valid_sources[0x05]	23704	1			T21	1		T22	606		T24	1
valid_sources[0x06]	22732	1			T21	1		T22	514		T29	3
valid_sources[0x07]	22198	1			T1	1		T22	538		T29	1
valid_sources[0x08]	23392	1			T22	632		T43	7		T171	2
valid_sources[0x09]	23499	1			T22	550		T24	57		T29	4
valid_sources[0x0a]	23173	1			T22	571		T43	1		T29	1
valid_sources[0x0b]	22679	1			T21	1		T22	591		T29	3
valid_sources[0x0c]	22873	1			T3	5		T22	514		T29	4
valid_sources[0x0d]	22148	1			T21	1		T22	569		T43	1
valid_sources[0x0e]	24110	1			T22	517		T23	1		T29	2
valid_sources[0x0f]	23138	1			T22	577		T17	1		T43	14
valid_sources[0x10]	24421	1			T22	528		T43	3		T29	3
valid_sources[0x11]	24737	1			T21	1		T22	586		T29	1
valid_sources[0x12]	22695	1			T21	1		T22	450		T29	1
valid_sources[0x13]	22643	1			T4	11		T21	1		T22	690
valid_sources[0x14]	23280	1			T21	1		T22	522		T29	3
valid_sources[0x15]	23853	1			T21	1		T22	596		T29	2
valid_sources[0x16]	24254	1			T21	1		T22	635		T43	4
valid_sources[0x17]	23753	1			T21	1		T22	479		T17	1
valid_sources[0x18]	23949	1			T22	466		T172	2		T173	5
valid_sources[0x19]	22660	1			T22	568		T29	1		T30	1
valid_sources[0x1a]	22993	1			T22	547		T29	2		T30	1
valid_sources[0x1b]	22610	1			T21	1		T22	598		T17	1
valid_sources[0x1c]	22780	1			T21	1		T22	572		T29	3
valid_sources[0x1d]	22906	1			T1	1		T22	619		T43	3
valid_sources[0x1e]	22394	1			T22	509		T43	1		T29	1
valid_sources[0x1f]	23668	1			T21	1		T22	456		T173	8
valid_sources[0x20]	22850	1			T22	580		T29	3		T30	1
valid_sources[0x21]	22078	1			T22	502		T29	3		T173	6
valid_sources[0x22]	23527	1			T21	3		T22	501		T29	1
valid_sources[0x23]	22345	1			T1	1		T22	509		T25	1
valid_sources[0x24]	22800	1			T22	524		T29	1		T173	1
valid_sources[0x25]	22259	1			T22	482		T17	2		T29	3
valid_sources[0x26]	21332	1			T22	463		T29	3		T30	2
valid_sources[0x27]	23692	1			T21	1		T22	556		T29	1
valid_sources[0x28]	23872	1			T21	1		T22	533		T29	3
valid_sources[0x29]	22828	1			T21	1		T22	561		T17	2
valid_sources[0x2a]	22639	1			T22	527		T17	2		T29	1
valid_sources[0x2b]	22338	1			T21	1		T22	653		T29	2
valid_sources[0x2c]	24088	1			T1	2		T22	561		T29	3
valid_sources[0x2d]	23902	1			T22	525		T29	3		T30	2
valid_sources[0x2e]	22888	1			T22	507		T29	2		T30	3
valid_sources[0x2f]	23848	1			T22	553		T29	2		T172	3
valid_sources[0x30]	22677	1			T22	574		T194	1		T29	1
valid_sources[0x31]	23267	1			T21	1		T22	499		T29	2
valid_sources[0x32]	22114	1			T22	498		T17	2		T30	2
valid_sources[0x33]	22891	1			T22	548		T17	1		T173	1
valid_sources[0x34]	22317	1			T22	617		T43	2		T29	2
valid_sources[0x35]	23328	1			T22	561		T24	1		T29	2
valid_sources[0x36]	21930	1			T22	562		T43	19		T173	1
valid_sources[0x37]	22179	1			T22	505		T29	2		T171	2
valid_sources[0x38]	23421	1			T22	514		T25	1		T29	2
valid_sources[0x39]	22759	1			T21	1		T22	504		T17	3
valid_sources[0x3a]	24717	1			T1	1		T22	480		T29	3
valid_sources[0x3b]	22756	1			T22	574		T17	5		T43	16
valid_sources[0x3c]	22978	1			T22	599		T29	1		T171	4
valid_sources[0x3d]	22489	1			T22	524		T29	1		T30	1
valid_sources[0x3e]	24313	1			T21	1		T22	557		T17	1
valid_sources[0x3f]	22803	1			T21	1		T22	459		T29	5
valid_sources[0x40]	23399	1			T3	5		T21	1		T22	521
valid_sources[0x41]	23220	1			T22	503		T29	2		T172	2
valid_sources[0x42]	23055	1			T22	497		T29	1		T171	1
valid_sources[0x43]	22882	1			T22	496		T29	2		T30	5
valid_sources[0x44]	21255	1			T22	534		T29	3		T171	2
valid_sources[0x45]	23025	1			T1	1		T22	617		T29	3
valid_sources[0x46]	22279	1			T22	546		T29	1		T172	3
valid_sources[0x47]	22916	1			T1	1		T22	600		T29	2
valid_sources[0x48]	23346	1			T22	527		T23	1		T29	1
valid_sources[0x49]	23053	1			T22	515		T29	4		T172	2
valid_sources[0x4a]	24619	1			T22	590		T25	1		T29	4
valid_sources[0x4b]	22736	1			T22	485		T44	22		T29	1
valid_sources[0x4c]	23547	1			T21	1		T22	464		T17	1
valid_sources[0x4d]	22560	1			T22	537		T43	7		T29	1
valid_sources[0x4e]	23384	1			T22	472		T29	1		T171	2
valid_sources[0x4f]	23926	1			T21	1		T22	594		T29	1
valid_sources[0x50]	22919	1			T22	639		T17	2		T172	9
valid_sources[0x51]	23444	1			T22	551		T17	1		T43	3
valid_sources[0x52]	22968	1			T22	533		T17	1		T194	1
valid_sources[0x53]	23934	1			T22	573		T17	1		T29	1
valid_sources[0x54]	24039	1			T22	600		T29	4		T175	5
valid_sources[0x55]	22636	1			T22	522		T29	1		T30	2
valid_sources[0x56]	22980	1			T21	2		T22	559		T17	1
valid_sources[0x57]	23443	1			T21	1		T22	496		T29	2
valid_sources[0x58]	23388	1			T22	488		T43	1		T29	3
valid_sources[0x59]	22755	1			T22	537		T17	2		T30	4
valid_sources[0x5a]	23306	1			T22	532		T17	1		T29	2
valid_sources[0x5b]	24162	1			T22	555		T172	5		T173	3
valid_sources[0x5c]	23529	1			T22	525		T17	2		T43	15
valid_sources[0x5d]	22682	1			T22	571		T29	1		T30	1
valid_sources[0x5e]	24028	1			T22	590		T25	2		T29	3
valid_sources[0x5f]	21166	1			T22	492		T29	1		T30	1
valid_sources[0x60]	22827	1			T21	1		T22	674		T29	2
valid_sources[0x61]	23242	1			T22	600		T17	3		T30	3
valid_sources[0x62]	23793	1			T22	604		T30	4		T173	10
valid_sources[0x63]	22687	1			T22	583		T29	1		T30	4
valid_sources[0x64]	22791	1			T21	1		T22	477		T30	5
valid_sources[0x65]	22910	1			T22	505		T29	3		T30	4
valid_sources[0x66]	23380	1			T22	510		T45	40		T172	1
valid_sources[0x67]	24557	1			T21	1		T22	533		T29	3
valid_sources[0x68]	24020	1			T21	1		T22	571		T17	1
valid_sources[0x69]	24404	1			T22	517		T29	3		T30	3
valid_sources[0x6a]	22819	1			T1	2		T3	4		T22	512
valid_sources[0x6b]	23013	1			T22	524		T30	2		T171	1
valid_sources[0x6c]	23446	1			T22	546		T29	4		T30	2
valid_sources[0x6d]	24842	1			T21	1		T22	588		T25	2
valid_sources[0x6e]	22678	1			T22	537		T29	2		T30	3
valid_sources[0x6f]	23446	1			T21	1		T22	487		T29	2
valid_sources[0x70]	24154	1			T21	1		T22	552		T29	3
valid_sources[0x71]	22710	1			T2	2		T22	519		T29	1
valid_sources[0x72]	23812	1			T22	653		T25	1		T172	4
valid_sources[0x73]	22217	1			T22	535		T29	2		T30	12
valid_sources[0x74]	22853	1			T22	629		T29	5		T171	4
valid_sources[0x75]	22474	1			T22	621		T17	1		T29	4
valid_sources[0x76]	23387	1			T21	1		T22	584		T29	3
valid_sources[0x77]	22229	1			T21	1		T22	506		T17	1
valid_sources[0x78]	23696	1			T22	541		T194	1		T29	2
valid_sources[0x79]	23283	1			T21	2		T22	552		T25	3
valid_sources[0x7a]	22875	1			T21	1		T22	635		T17	2
valid_sources[0x7b]	22860	1			T1	1		T22	507		T30	3
valid_sources[0x7c]	22697	1			T22	448		T29	3		T171	11
valid_sources[0x7d]	23641	1			T22	457		T29	1		T171	1
valid_sources[0x7e]	23071	1			T22	547		T29	6		T30	2
valid_sources[0x7f]	23922	1			T22	557		T194	1		T30	1
valid_sources[0x80]	22382	1			T22	466		T194	1		T29	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1336322

1

T1

2

T2

2

T3

3

values[0x0]

all_enables

biggest_size

1991956

1

T1

2

T2

2

T3

6

values[0x1]

all_enables

biggest_size

1988739

1

T1

1

T2

2

T20

1