Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	100.00	1	100	1	64	64

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	0	52	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	0	52	100.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
non_zero_bins[0]	2577	1		T22	25	T23	1	T24	2
non_zero_bins[1]	1796	1		T21	1	T22	25	T24	1
zero	7851	1		T1	3	T2	2	T3	2

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	482	1		T22	6	T58	1	T37	1
uni	3385	1		T1	1	T21	2	T22	40
gen	3698	1		T1	1	T2	1	T3	1
res	794	1		T22	10	T23	1	T8	2
ins	3865	1		T1	1	T2	1	T3	1

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8190

mubi_true

4034

T20

T21

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

6092

T20

pass

6132

T20

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	0	52	100.00
Automatically Generated Cross Bins	52	0	52	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	non_zero_bins[0]	fail	mubi_false	82	1		T99	3	T100	3	T106	1
upd	non_zero_bins[0]	fail	mubi_true	59	1		T22	1	T100	1	T294	1
upd	non_zero_bins[0]	pass	mubi_false	53	1		T22	2	T58	1	T316	1
upd	non_zero_bins[0]	pass	mubi_true	59	1		T104	1	T75	1	T100	1
upd	non_zero_bins[1]	fail	mubi_false	37	1		T37	1	T99	1	T104	1
upd	non_zero_bins[1]	fail	mubi_true	31	1		T99	1	T100	1	T106	2
upd	non_zero_bins[1]	pass	mubi_false	42	1		T22	1	T99	1	T100	2
upd	non_zero_bins[1]	pass	mubi_true	36	1		T22	1	T106	2	T271	1
upd	zero	fail	mubi_false	18	1		T102	1	T103	1	T317	1
upd	zero	fail	mubi_true	24	1		T103	1	T318	1	T300	1
upd	zero	pass	mubi_false	22	1		T100	1	T317	1	T319	1
upd	zero	pass	mubi_true	19	1		T22	1	T106	1	T101	1
uni	zero	fail	mubi_false	1256	1		T21	1	T22	22	T24	2
uni	zero	fail	mubi_true	428	1		T22	6	T58	3	T60	1
uni	zero	pass	mubi_false	1222	1		T22	7	T23	1	T25	1
uni	zero	pass	mubi_true	479	1		T1	1	T21	1	T22	5
gen	non_zero_bins[0]	fail	mubi_false	226	1		T58	1	T303	1	T37	1
gen	non_zero_bins[0]	fail	mubi_true	274	1		T22	3	T8	2	T58	2
gen	non_zero_bins[0]	pass	mubi_false	232	1		T22	1	T99	2	T100	6
gen	non_zero_bins[0]	pass	mubi_true	223	1		T22	3	T8	1	T32	2
gen	non_zero_bins[1]	fail	mubi_false	152	1		T104	1	T80	1	T75	1
gen	non_zero_bins[1]	fail	mubi_true	166	1		T22	5	T24	1	T42	1
gen	non_zero_bins[1]	pass	mubi_false	162	1		T22	1	T58	2	T99	1
gen	non_zero_bins[1]	pass	mubi_true	189	1		T22	5	T42	2	T99	1
gen	zero	fail	mubi_false	846	1		T3	1	T4	1	T22	7
gen	zero	fail	mubi_true	203	1		T23	1	T17	2	T59	1
gen	zero	pass	mubi_false	821	1		T1	1	T2	1	T21	1
gen	zero	pass	mubi_true	204	1		T20	1	T22	2	T57	1
res	non_zero_bins[0]	fail	mubi_false	106	1		T22	1	T59	1	T32	1
res	non_zero_bins[0]	fail	mubi_true	96	1		T22	1	T99	2	T100	1
res	non_zero_bins[0]	pass	mubi_false	79	1		T32	1	T42	1	T99	1
res	non_zero_bins[0]	pass	mubi_true	97	1		T22	1	T81	2	T106	2
res	non_zero_bins[1]	fail	mubi_false	52	1		T22	1	T8	1	T13	1
res	non_zero_bins[1]	fail	mubi_true	67	1		T22	3	T9	1	T58	2
res	non_zero_bins[1]	pass	mubi_false	59	1		T22	1	T8	1	T99	1
res	non_zero_bins[1]	pass	mubi_true	68	1		T38	1	T100	1	T39	1
res	zero	fail	mubi_false	41	1		T22	1	T99	1	T103	1
res	zero	fail	mubi_true	44	1		T23	1	T58	1	T80	2
res	zero	pass	mubi_false	37	1		T22	1	T74	2	T100	1
res	zero	pass	mubi_true	48	1		T80	1	T106	1	T265	1
ins	non_zero_bins[0]	fail	mubi_false	231	1		T22	1	T23	1	T24	1
ins	non_zero_bins[0]	fail	mubi_true	263	1		T22	6	T13	1	T99	2
ins	non_zero_bins[0]	pass	mubi_false	254	1		T22	3	T24	1	T33	1
ins	non_zero_bins[0]	pass	mubi_true	243	1		T22	2	T99	1	T80	1
ins	non_zero_bins[1]	fail	mubi_false	170	1		T22	1	T32	1	T99	2
ins	non_zero_bins[1]	fail	mubi_true	165	1		T22	2	T58	1	T303	1
ins	non_zero_bins[1]	pass	mubi_false	197	1		T21	1	T22	2	T13	1
ins	non_zero_bins[1]	pass	mubi_true	203	1		T22	2	T58	1	T99	1
ins	zero	fail	mubi_false	892	1		T3	1	T20	1	T22	7
ins	zero	fail	mubi_true	163	1		T21	1	T22	2	T31	1
ins	zero	pass	mubi_false	901	1		T1	1	T2	1	T4	1
ins	zero	pass	mubi_true	183	1		T22	1	T17	1	T8	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded