Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_output	89.81	100.00	69.23			90.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	97.12	100.00	88.46			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	97.12	100.00	88.46			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.81	100.00	69.23			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.06	100.00	69.23			95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.31	100.00	85.94			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.31	100.00	85.94			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.31	100.00	85.94			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T5,T9

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T21,T22,T24
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T21,T22,T24
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T88,T90,T94
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T89,T96
1	0	1	Covered	T1,T2,T20
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T5,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T5,T9

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T5,T9
0	1	Covered	T1,T2,T3
0	0	Covered	T21,T22,T24

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	620160260	913153	0	0
DepthKnown_A	620503170	620063373	0	0
RvalidKnown_A	620503170	620063373	0	0
WreadyKnown_A	620503170	620063373	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	620503170	974846	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	620160260	913153	0	0
T1	1104	3	0	0
T2	869	3	0	0
T3	882	2	0	0
T4	985	12	0	0
T5	257	142	0	0
T6	0	113	0	0
T8	5120	2225	0	0
T9	2500	1806	0	0
T13	0	2209	0	0
T14	76	0	0	0
T17	1963	0	0	0
T20	2220	42	0	0
T21	2636	23	0	0
T22	1166078	654	0	0
T23	2076	14	0	0
T24	2402	28	0	0
T25	2312	3	0	0
T31	1878	37	0	0
T32	0	6712	0	0
T33	1766	0	0	0
T34	0	122	0	0
T38	0	4951	0	0
T42	0	302	0	0
T54	1458	0	0	0
T55	945	0	0	0
T57	0	37	0	0
T72	1226	0	0	0
T73	394	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	620503170	620063373	0	0
T1	3312	3057	0	0
T2	2607	2178	0	0
T3	2646	2292	0	0
T4	2649	2199	0	0
T20	3330	3096	0	0
T21	3954	3711	0	0
T22	1749117	1749084	0	0
T23	3114	2868	0	0
T24	3603	3333	0	0
T25	3468	3315	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	620503170	620063373	0	0
T1	3312	3057	0	0
T2	2607	2178	0	0
T3	2646	2292	0	0
T4	2649	2199	0	0
T20	3330	3096	0	0
T21	3954	3711	0	0
T22	1749117	1749084	0	0
T23	3114	2868	0	0
T24	3603	3333	0	0
T25	3468	3315	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	620503170	620063373	0	0
T1	3312	3057	0	0
T2	2607	2178	0	0
T3	2646	2292	0	0
T4	2649	2199	0	0
T20	3330	3096	0	0
T21	3954	3711	0	0
T22	1749117	1749084	0	0
T23	3114	2868	0	0
T24	3603	3333	0	0
T25	3468	3315	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	620503170	974846	0	0
T1	1104	3	0	0
T2	869	3	0	0
T3	882	2	0	0
T4	1766	200	0	0
T5	1481	1217	0	0
T6	0	610	0	0
T8	5120	2225	0	0
T9	2500	1806	0	0
T13	0	2209	0	0
T14	614	147	0	0
T17	1963	0	0	0
T20	2220	42	0	0
T21	2636	23	0	0
T22	1166078	654	0	0
T23	2076	14	0	0
T24	2402	28	0	0
T25	2312	3	0	0
T31	1878	37	0	0
T32	0	3309	0	0
T33	1766	0	0	0
T34	0	122	0	0
T42	0	302	0	0
T54	1458	0	0	0
T55	945	0	0	0
T57	0	37	0	0
T72	1226	0	0	0
T73	1574	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output

	Total	Covered	Percent
Conditions	26	18	69.23
Logical	26	18	69.23
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T21,T22,T24
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T21,T22,T24
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T20
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T21,T22,T24

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	206834390	57179	0	0
DepthKnown_A	206834390	206687791	0	0
RvalidKnown_A	206834390	206687791	0	0
WreadyKnown_A	206834390	206687791	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	206834390	57179	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	57179	0	0
T1	1104	3	0	0
T2	869	3	0	0
T3	882	2	0	0
T4	883	6	0	0
T20	1110	4	0	0
T21	1318	23	0	0
T22	583039	654	0	0
T23	1038	14	0	0
T24	1201	28	0	0
T25	1156	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	57179	0	0
T1	1104	3	0	0
T2	869	3	0	0
T3	882	2	0	0
T4	883	6	0	0
T20	1110	4	0	0
T21	1318	23	0	0
T22	583039	654	0	0
T23	1038	14	0	0
T24	1201	28	0	0
T25	1156	3	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T7,T39

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T8,T9,T13
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T8,T9,T13
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T88,T94,T95
1	1	0	Not Covered
1	1	1	Covered	T8,T5,T9

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3
1	0	1	Covered	T8,T5,T9
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T13

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T7,T39
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T5,T9

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T7,T39

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T8,T5,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T9,T7,T39
0	1	Covered	T1,T2,T3
0	0	Covered	T8,T9,T13

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T5,T9

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T8,T5,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	206662935	419899	0	0
DepthKnown_A	206834390	206687791	0	0
RvalidKnown_A	206834390	206687791	0	0
WreadyKnown_A	206834390	206687791	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	206834390	445646	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206662935	419899	0	0
T5	257	21	0	0
T6	0	113	0	0
T8	2560	1109	0	0
T9	2500	899	0	0
T13	0	1110	0	0
T14	76	0	0	0
T31	1878	0	0	0
T32	0	3309	0	0
T33	1766	0	0	0
T38	0	4951	0	0
T42	0	302	0	0
T54	1458	0	0	0
T55	945	0	0	0
T72	1226	0	0	0
T73	197	0	0	0
T74	0	2941	0	0
T80	0	1221	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	445646	0	0
T5	1481	522	0	0
T6	0	610	0	0
T8	2560	1109	0	0
T9	2500	899	0	0
T13	0	1110	0	0
T14	614	0	0	0
T31	1878	0	0	0
T32	0	3309	0	0
T33	1766	0	0	0
T38	0	4951	0	0
T42	0	302	0	0
T54	1458	0	0	0
T55	945	0	0	0
T72	1226	0	0	0
T73	787	0	0	0
T74	0	2941	0	0
T80	0	1221	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T5,T9

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T8,T13,T32
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T8,T13,T32
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T90,T114,T115
1	1	0	Not Covered
1	1	1	Covered	T20,T4,T8

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T89,T96,T97
1	0	1	Covered	T20,T4,T8
1	1	0	Not Covered
1	1	1	Covered	T20,T4,T8

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T5,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T20,T4,T8

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T5,T9

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T20,T4,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T5,T9
0	1	Covered	T1,T2,T3
0	0	Covered	T8,T13,T32

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T20,T4,T8

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T20,T4,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	206662935	436075	0	0
DepthKnown_A	206834390	206687791	0	0
RvalidKnown_A	206834390	206687791	0	0
WreadyKnown_A	206834390	206687791	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	206834390	472021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206662935	436075	0	0
T4	102	6	0	0
T5	0	121	0	0
T8	2560	1116	0	0
T9	0	907	0	0
T13	0	1099	0	0
T17	1963	0	0	0
T20	1110	38	0	0
T21	1318	0	0	0
T22	583039	0	0	0
T23	1038	0	0	0
T24	1201	0	0	0
T25	1156	0	0	0
T31	0	37	0	0
T32	0	3403	0	0
T34	0	122	0	0
T57	0	37	0	0
T73	197	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	472021	0	0
T4	883	194	0	0
T5	0	695	0	0
T8	2560	1116	0	0
T9	0	907	0	0
T13	0	1099	0	0
T14	0	147	0	0
T17	1963	0	0	0
T20	1110	38	0	0
T21	1318	0	0	0
T22	583039	0	0	0
T23	1038	0	0	0
T24	1201	0	0	0
T25	1156	0	0	0
T31	0	37	0	0
T34	0	122	0	0
T57	0	37	0	0
T73	787	0	0	0