Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cs_cmds_cg 100.00 1 100 1 64 64



Group Instance : edn_cs_cmds_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance edn_cs_cmds_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 19 0 19 100.00
Crosses 49 0 49 100.00


Variables for Group Instance edn_cs_cmds_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acmd 5 0 5 100.00 100 1 1 0
cp_clen 2 0 2 100.00 100 1 1 0
cp_cmd_src 5 0 5 100.00 100 1 1 0
cp_flags 2 0 2 100.00 100 1 1 0
cp_glen 2 0 2 100.00 100 1 1 0
cp_mode 3 0 3 100.00 100 1 1 0


Crosses for Group Instance edn_cs_cmds_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_generate_intended 13 0 13 100.00 100 1 1 0
cr_instantiate_intended 13 0 13 100.00 100 1 1 0
cr_reseed_intended 12 0 12 100.00 100 1 1 0
cr_update_intended 4 0 4 100.00 100 1 1 0
cr_uninstantiate_intended 2 0 2 100.00 100 1 1 0
cr_acmd_mode_cmd_src_unintended 5 0 5 100.00 100 1 1 0


Summary for Variable cp_acmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for cp_acmd

Excluded/Illegal bins
NAMECOUNTSTATUS
auto[INV] 0 Excluded
auto[GENB] 0 Excluded
auto[GENU] 0 Excluded
unused 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] 4199 1 T1 1 T2 21 T3 2
auto[RES] 921 1 T2 6 T3 1 T4 3
auto[GEN] 3947 1 T1 1 T2 17 T3 2
auto[UPD] 561 1 T1 1 T2 2 T17 1
auto[UNI] 3858 1 T1 1 T2 21 T3 1


Summary for Variable cp_clen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_clen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
some_cmd_data 4711 1 T1 3 T2 33 T3 3
no_cmd_data 8775 1 T1 1 T2 34 T3 3


Summary for Variable cp_cmd_src

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for cp_cmd_src

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_cmd_req 12472 1 T1 4 T2 67 T3 4
reseed_cmd 316 1 T3 1 T4 3 T6 3
generate_cmd 274 1 T3 1 T4 2 T6 2
boot_gen_cmd 212 1 T19 1 T27 1 T12 2
boot_ins_cmd 212 1 T19 1 T27 1 T12 2


Summary for Variable cp_flags

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_flags

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
true 4357 1 T1 2 T2 20 T3 2
false 9129 1 T1 2 T2 47 T3 4


Summary for Variable cp_glen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_glen

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
multiple 1177 1 T3 4 T18 2 T19 1
one 1989 1 T1 2 T2 5 T3 1


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_mode 11833 1 T1 4 T2 67 T3 2
boot_mode 604 1 T19 2 T27 4 T12 4
auto_mode 1049 1 T3 4 T13 3 T14 3


Summary for Cross cr_generate_intended

Samples crossed: cp_acmd cp_clen cp_glen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 13 0 13 100.00
Automatically Generated Cross Bins 13 0 13 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_generate_intended

Excluded/Illegal bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[GEN] some_cmd_data multiple sw_mode sw_cmd_req 130 1 T18 1 T46 1 T8 1
auto[GEN] some_cmd_data multiple boot_mode sw_cmd_req 46 1 T29 1 T31 1 T258 1
auto[GEN] some_cmd_data multiple auto_mode generate_cmd 113 1 T4 2 T8 1 T100 1
auto[GEN] some_cmd_data one sw_mode sw_cmd_req 47 1 T1 1 T17 1 T45 1
auto[GEN] some_cmd_data one boot_mode sw_cmd_req 18 1 T27 1 T75 1 T316 1
auto[GEN] some_cmd_data one auto_mode generate_cmd 118 1 T3 1 T6 1 T7 2
auto[GEN] no_cmd_data multiple sw_mode sw_cmd_req 31 1 T3 1 T25 1 T28 1
auto[GEN] no_cmd_data multiple boot_mode sw_cmd_req 8 1 T317 1 T277 1 T318 1
auto[GEN] no_cmd_data multiple boot_mode boot_gen_cmd 53 1 T27 1 T75 1 T29 1
auto[GEN] no_cmd_data multiple auto_mode generate_cmd 23 1 T319 1 T320 1 T153 1
auto[GEN] no_cmd_data one sw_mode sw_cmd_req 1579 1 T2 5 T44 1 T60 1
auto[GEN] no_cmd_data one boot_mode sw_cmd_req 5 1 T30 1 T321 1 T322 1
auto[GEN] no_cmd_data one auto_mode generate_cmd 20 1 T6 1 T137 1 T40 1


User Defined Cross Bins for cr_generate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_gen 0 Excluded
gen_auto_wrong_src 0 Excluded
gen_boot_wrong_src 0 Excluded
gen_boot_seq_wrong_clen 0 Excluded
gen_boot_seq_wrong_glen 0 Excluded
gen_sw_wrong_src 0 Excluded


Summary for Cross cr_instantiate_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 13 0 13 100.00
Automatically Generated Cross Bins 13 0 13 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] some_cmd_data true sw_mode sw_cmd_req 864 1 T1 1 T2 7 T17 1
auto[INS] some_cmd_data true boot_mode sw_cmd_req 8 1 T35 1 T291 1 T322 1
auto[INS] some_cmd_data true auto_mode sw_cmd_req 81 1 T3 1 T9 1 T105 1
auto[INS] some_cmd_data false sw_mode sw_cmd_req 864 1 T2 9 T5 19 T93 6
auto[INS] some_cmd_data false boot_mode sw_cmd_req 9 1 T258 1 T69 1 T323 1
auto[INS] some_cmd_data false auto_mode sw_cmd_req 76 1 T100 1 T36 1 T68 1
auto[INS] no_cmd_data true sw_mode sw_cmd_req 197 1 T18 2 T25 1 T5 3
auto[INS] no_cmd_data true boot_mode sw_cmd_req 4 1 T270 1 T324 1 T295 1
auto[INS] no_cmd_data true auto_mode sw_cmd_req 68 1 T13 1 T14 1 T15 1
auto[INS] no_cmd_data false sw_mode sw_cmd_req 1762 1 T2 5 T44 1 T60 1
auto[INS] no_cmd_data false boot_mode sw_cmd_req 5 1 T264 1 T325 1 T326 1
auto[INS] no_cmd_data false boot_mode boot_ins_cmd 102 1 T19 1 T12 1 T67 1
auto[INS] no_cmd_data false auto_mode sw_cmd_req 49 1 T3 1 T6 1 T8 1


User Defined Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_ins 0 Excluded
ins_auto_wrong_src 0 Excluded
ins_boot_wrong_src 0 Excluded
ins_boot_seq_wrong_clen 0 Excluded
ins_boot_seq_wrong_flag0 0 Excluded
ins_sw_wrong_src 0 Excluded


Summary for Cross cr_reseed_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 12 0 12 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_reseed_intended

Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[RES] some_cmd_data true sw_mode sw_cmd_req 250 1 T2 2 T5 1 T93 1
auto[RES] some_cmd_data true boot_mode sw_cmd_req 14 1 T30 1 T327 1 T277 1
auto[RES] some_cmd_data true auto_mode reseed_cmd 106 1 T8 1 T68 1 T137 1
auto[RES] some_cmd_data false sw_mode sw_cmd_req 197 1 T2 4 T5 5 T46 1
auto[RES] some_cmd_data false boot_mode sw_cmd_req 10 1 T75 1 T328 1 T321 1
auto[RES] some_cmd_data false auto_mode reseed_cmd 111 1 T3 1 T4 1 T6 2
auto[RES] no_cmd_data true sw_mode sw_cmd_req 56 1 T5 3 T26 1 T93 2
auto[RES] no_cmd_data true boot_mode sw_cmd_req 2 1 T290 1 T329 1 - -
auto[RES] no_cmd_data true auto_mode reseed_cmd 29 1 T105 1 T36 1 T11 1
auto[RES] no_cmd_data false sw_mode sw_cmd_req 54 1 T5 3 T32 1 T95 1
auto[RES] no_cmd_data false boot_mode sw_cmd_req 1 1 T31 1 - - - -
auto[RES] no_cmd_data false auto_mode reseed_cmd 70 1 T4 2 T6 1 T7 1


User Defined Cross Bins for cr_reseed_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_res 0 Excluded
res_auto_wrong_src 0 Excluded
res_boot_wrong_src 0 Excluded
res_sw_wrong_src 0 Excluded


Summary for Cross cr_update_intended

Samples crossed: cp_acmd cp_clen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_update_intended

Excluded/Illegal bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)


Covered bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UPD] some_cmd_data sw_mode sw_cmd_req 413 1 T1 1 T2 2 T17 1
auto[UPD] some_cmd_data boot_mode sw_cmd_req 18 1 T29 1 T316 1 T263 1
auto[UPD] no_cmd_data sw_mode sw_cmd_req 105 1 T5 2 T97 1 T28 1
auto[UPD] no_cmd_data boot_mode sw_cmd_req 6 1 T27 1 T330 1 T331 1


User Defined Cross Bins for cr_update_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_upd 0 Excluded
upd_auto_wrong_src 0 Excluded
upd_boot_wrong_src 0 Excluded
upd_sw_wrong_src 0 Excluded


Summary for Cross cr_uninstantiate_intended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UNI] sw_mode sw_cmd_req 3811 1 T1 1 T2 21 T3 1
auto[UNI] boot_mode sw_cmd_req 26 1 T258 1 T69 1 T35 1


User Defined Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_uni 0 Excluded
uni_auto_wrong_src 0 Excluded
uni_boot_wrong_src 0 Excluded
uni_sw_wrong_src 0 Excluded


Summary for Cross cr_acmd_mode_cmd_src_unintended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 5 0 5 100.00
Automatically Generated Cross Bins 5 0 5 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] auto_mode sw_cmd_req 274 1 T3 2 T13 1 T14 1
auto[RES] auto_mode sw_cmd_req 21 1 T9 1 T105 1 T266 1
auto[GEN] auto_mode sw_cmd_req 124 1 T13 2 T14 2 T8 1
auto[UPD] auto_mode sw_cmd_req 19 1 T319 1 T332 1 T333 1
auto[UNI] auto_mode sw_cmd_req 21 1 T100 1 T11 1 T320 1


User Defined Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_sw_cmd 0 Excluded
not_auto_mode 0 Excluded

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