Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	711065	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6150781

1

T1

34

T2

54028

T3

39

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1793695	1			T1	59		T2	15342		T3	42
values[0x0]	2351223	1			T1	18		T2	20627		T3	24
values[0x1]	2716928	1			T1	16		T2	24005		T3	17

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	347489	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6514357

1

T1

53

T2

57133

T3

53

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25746	1			T2	119		T27	1		T23	1
valid_sources[0x01]	26374	1			T2	25		T27	1		T23	1
valid_sources[0x02]	28671	1			T2	748		T25	1		T27	1
valid_sources[0x03]	27585	1			T2	299		T18	1		T44	1
valid_sources[0x04]	25329	1			T2	266		T14	3		T19	5
valid_sources[0x05]	28377	1			T2	181		T17	1		T44	1
valid_sources[0x06]	27929	1			T2	266		T18	2		T25	2
valid_sources[0x07]	25733	1			T2	39		T18	1		T14	3
valid_sources[0x08]	26750	1			T2	187		T18	2		T25	2
valid_sources[0x09]	26757	1			T1	5		T2	193		T18	1
valid_sources[0x0a]	26711	1			T1	1		T2	82		T16	5
valid_sources[0x0b]	26765	1			T2	58		T44	2		T27	1
valid_sources[0x0c]	27066	1			T2	486		T190	7		T202	1
valid_sources[0x0d]	28090	1			T2	241		T18	1		T25	1
valid_sources[0x0e]	28053	1			T2	349		T14	5		T27	1
valid_sources[0x0f]	25096	1			T2	241		T18	1		T24	1
valid_sources[0x10]	27863	1			T1	1		T2	88		T243	1
valid_sources[0x11]	26024	1			T2	173		T18	2		T14	1
valid_sources[0x12]	26006	1			T2	21		T44	1		T189	1
valid_sources[0x13]	26724	1			T2	44		T18	2		T37	1
valid_sources[0x14]	26402	1			T2	55		T4	3		T151	1
valid_sources[0x15]	27788	1			T2	59		T23	2		T24	1
valid_sources[0x16]	27044	1			T2	429		T25	1		T23	2
valid_sources[0x17]	26275	1			T1	2		T2	364		T4	6
valid_sources[0x18]	25877	1			T2	120		T25	1		T27	1
valid_sources[0x19]	27251	1			T2	294		T16	11		T17	1
valid_sources[0x1a]	26407	1			T2	235		T23	1		T24	1
valid_sources[0x1b]	27435	1			T2	378		T14	3		T187	13
valid_sources[0x1c]	26711	1			T2	14		T23	1		T24	2
valid_sources[0x1d]	27438	1			T2	33		T18	2		T4	3
valid_sources[0x1e]	28462	1			T2	394		T23	1		T24	1
valid_sources[0x1f]	25180	1			T2	253		T25	2		T187	4
valid_sources[0x20]	26343	1			T2	320		T38	5		T243	1
valid_sources[0x21]	26738	1			T2	199		T25	1		T151	2
valid_sources[0x22]	26856	1			T2	728		T18	3		T188	1
valid_sources[0x23]	27153	1			T2	58		T18	2		T25	1
valid_sources[0x24]	27167	1			T2	425		T18	1		T187	1
valid_sources[0x25]	27155	1			T2	482		T4	1		T25	1
valid_sources[0x26]	27548	1			T2	675		T17	2		T23	1
valid_sources[0x27]	27011	1			T2	336		T18	1		T27	2
valid_sources[0x28]	24987	1			T2	22		T17	1		T18	2
valid_sources[0x29]	26767	1			T2	136		T18	2		T225	3
valid_sources[0x2a]	24462	1			T2	341		T18	3		T25	1
valid_sources[0x2b]	27971	1			T2	23		T13	1		T14	2
valid_sources[0x2c]	25725	1			T1	2		T2	198		T24	2
valid_sources[0x2d]	27421	1			T2	266		T25	2		T23	1
valid_sources[0x2e]	27431	1			T2	783		T17	2		T25	1
valid_sources[0x2f]	26719	1			T1	4		T2	1140		T27	1
valid_sources[0x30]	26646	1			T2	115		T24	1		T244	8
valid_sources[0x31]	26704	1			T2	24		T44	1		T217	1
valid_sources[0x32]	26053	1			T2	268		T18	4		T44	5
valid_sources[0x33]	27010	1			T1	6		T2	318		T17	2
valid_sources[0x34]	26004	1			T2	9		T188	2		T189	1
valid_sources[0x35]	27657	1			T2	75		T23	1		T187	6
valid_sources[0x36]	26735	1			T2	465		T25	1		T37	1
valid_sources[0x37]	25788	1			T2	199		T18	1		T24	2
valid_sources[0x38]	25742	1			T2	183		T25	1		T27	2
valid_sources[0x39]	28663	1			T2	365		T13	1		T24	1
valid_sources[0x3a]	26084	1			T2	146		T18	3		T14	4
valid_sources[0x3b]	25701	1			T2	89		T18	2		T44	1
valid_sources[0x3c]	27648	1			T2	182		T18	1		T216	1
valid_sources[0x3d]	26576	1			T2	261		T44	1		T27	1
valid_sources[0x3e]	26355	1			T2	9		T17	1		T225	1
valid_sources[0x3f]	26330	1			T2	205		T18	1		T23	3
valid_sources[0x40]	27272	1			T2	239		T334	1		T219	5
valid_sources[0x41]	27419	1			T2	356		T44	1		T25	2
valid_sources[0x42]	26579	1			T2	98		T18	2		T23	2
valid_sources[0x43]	26314	1			T1	3		T2	88		T25	2
valid_sources[0x44]	26427	1			T2	128		T151	1		T187	2
valid_sources[0x45]	28164	1			T2	92		T18	1		T27	1
valid_sources[0x46]	27273	1			T2	337		T13	3		T4	2
valid_sources[0x47]	26399	1			T2	41		T23	1		T187	4
valid_sources[0x48]	25966	1			T2	17		T25	2		T27	2
valid_sources[0x49]	26586	1			T2	58		T18	1		T24	1
valid_sources[0x4a]	24961	1			T2	140		T18	1		T24	1
valid_sources[0x4b]	26671	1			T2	387		T18	1		T23	1
valid_sources[0x4c]	26135	1			T2	167		T27	1		T243	1
valid_sources[0x4d]	27407	1			T2	105		T18	2		T44	1
valid_sources[0x4e]	25700	1			T2	41		T23	3		T24	1
valid_sources[0x4f]	25991	1			T2	115		T18	4		T23	1
valid_sources[0x50]	25807	1			T2	52		T17	2		T18	3
valid_sources[0x51]	28030	1			T2	103		T27	2		T188	2
valid_sources[0x52]	27490	1			T1	2		T2	785		T17	1
valid_sources[0x53]	26291	1			T2	69		T25	1		T23	1
valid_sources[0x54]	25671	1			T2	155		T25	1		T27	1
valid_sources[0x55]	27218	1			T2	183		T18	1		T4	1
valid_sources[0x56]	27041	1			T2	218		T24	1		T243	1
valid_sources[0x57]	27679	1			T2	163		T18	2		T4	1
valid_sources[0x58]	26769	1			T2	412		T243	1		T151	1
valid_sources[0x59]	27760	1			T2	225		T14	5		T25	1
valid_sources[0x5a]	27646	1			T2	396		T23	1		T151	1
valid_sources[0x5b]	27237	1			T2	239		T17	1		T14	5
valid_sources[0x5c]	25153	1			T1	3		T2	91		T24	3
valid_sources[0x5d]	27616	1			T2	570		T23	3		T24	1
valid_sources[0x5e]	26113	1			T2	285		T18	2		T24	2
valid_sources[0x5f]	27360	1			T2	736		T18	2		T27	1
valid_sources[0x60]	26375	1			T2	70		T13	8		T18	1
valid_sources[0x61]	26822	1			T2	731		T18	2		T243	2
valid_sources[0x62]	25952	1			T2	590		T4	3		T24	1
valid_sources[0x63]	26198	1			T2	221		T18	2		T24	2
valid_sources[0x64]	27461	1			T2	44		T18	1		T24	2
valid_sources[0x65]	26438	1			T2	614		T44	1		T25	1
valid_sources[0x66]	27270	1			T2	244		T25	2		T27	1
valid_sources[0x67]	26855	1			T2	20		T18	1		T25	1
valid_sources[0x68]	26889	1			T1	3		T2	116		T14	3
valid_sources[0x69]	28137	1			T1	1		T2	654		T18	1
valid_sources[0x6a]	28361	1			T2	96		T18	2		T25	1
valid_sources[0x6b]	27265	1			T2	513		T18	1		T14	2
valid_sources[0x6c]	27749	1			T2	160		T18	2		T225	1
valid_sources[0x6d]	27449	1			T2	110		T24	1		T188	1
valid_sources[0x6e]	27311	1			T2	417		T243	1		T151	1
valid_sources[0x6f]	27587	1			T1	2		T2	263		T18	1
valid_sources[0x70]	28004	1			T1	1		T2	183		T23	1
valid_sources[0x71]	25633	1			T2	131		T27	1		T23	2
valid_sources[0x72]	25760	1			T2	23		T18	2		T23	2
valid_sources[0x73]	26019	1			T2	247		T17	7		T23	1
valid_sources[0x74]	29021	1			T2	438		T18	2		T37	3
valid_sources[0x75]	26830	1			T2	110		T18	2		T151	2
valid_sources[0x76]	27513	1			T2	37		T23	1		T24	2
valid_sources[0x77]	25501	1			T2	112		T23	2		T151	1
valid_sources[0x78]	27129	1			T2	293		T13	1		T24	1
valid_sources[0x79]	25826	1			T2	472		T45	1		T23	2
valid_sources[0x7a]	27538	1			T2	284		T23	1		T244	4
valid_sources[0x7b]	27849	1			T2	274		T17	2		T18	1
valid_sources[0x7c]	26589	1			T2	428		T23	3		T24	2
valid_sources[0x7d]	28609	1			T2	35		T27	1		T24	1
valid_sources[0x7e]	27250	1			T2	201		T18	1		T25	1
valid_sources[0x7f]	25486	1			T2	168		T18	1		T14	1
valid_sources[0x80]	25631	1			T1	4		T2	61		T18	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1543809

1

T1

2

T2

13460

T3

2

values[0x0]

all_enables

biggest_size

2305129

1

T1

17

T2

20235

T3

23

values[0x1]

all_enables

biggest_size

2301843

1

T1

15

T2

20333

T3

14