Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	100.00	1	100	1	64	64

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	0	52	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	0	52	100.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
non_zero_bins[0]	2721	1		T1	1	T2	15	T3	12
non_zero_bins[1]	1984	1		T1	2	T2	18	T18	1
zero	8577	1		T1	1	T2	34	T3	2

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	521	1		T1	1	T2	2	T17	1
uni	3715	1		T1	1	T2	21	T3	1
gen	4007	1		T1	1	T2	17	T3	10
res	859	1		T2	6	T3	2	T5	12
ins	4180	1		T1	1	T2	21	T3	1

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9022

mubi_true

4260

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

6723

pass

6559

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	0	52	100.00
Automatically Generated Cross Bins	52	0	52	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	non_zero_bins[0]	fail	mubi_false	42	1		T5	1	T95	1	T286	3
upd	non_zero_bins[0]	fail	mubi_true	55	1		T5	1	T33	1	T93	1
upd	non_zero_bins[0]	pass	mubi_false	68	1		T1	1	T17	1	T45	1
upd	non_zero_bins[0]	pass	mubi_true	55	1		T5	1	T95	1	T286	3
upd	non_zero_bins[1]	fail	mubi_false	44	1		T5	2	T92	1	T95	3
upd	non_zero_bins[1]	fail	mubi_true	53	1		T5	1	T95	3	T287	1
upd	non_zero_bins[1]	pass	mubi_false	45	1		T2	1	T5	1	T92	1
upd	non_zero_bins[1]	pass	mubi_true	53	1		T2	1	T93	1	T92	2
upd	zero	fail	mubi_false	32	1		T27	1	T92	2	T286	1
upd	zero	fail	mubi_true	25	1		T5	1	T92	1	T95	2
upd	zero	pass	mubi_false	26	1		T5	1	T97	1	T28	1
upd	zero	pass	mubi_true	23	1		T95	1	T288	1	T51	1
uni	zero	fail	mubi_false	1357	1		T1	1	T2	7	T17	1
uni	zero	fail	mubi_true	525	1		T2	2	T5	9	T66	1
uni	zero	pass	mubi_false	1340	1		T2	9	T3	1	T44	1
uni	zero	pass	mubi_true	493	1		T2	3	T18	1	T25	1
gen	non_zero_bins[0]	fail	mubi_false	246	1		T2	1	T3	6	T5	3
gen	non_zero_bins[0]	fail	mubi_true	267	1		T5	2	T93	2	T29	1
gen	non_zero_bins[0]	pass	mubi_false	285	1		T2	1	T3	3	T17	1
gen	non_zero_bins[0]	pass	mubi_true	223	1		T45	1	T5	7	T46	1
gen	non_zero_bins[1]	fail	mubi_false	202	1		T2	2	T27	1	T5	7
gen	non_zero_bins[1]	fail	mubi_true	164	1		T1	1	T2	1	T5	1
gen	non_zero_bins[1]	pass	mubi_false	213	1		T2	2	T18	1	T5	7
gen	non_zero_bins[1]	pass	mubi_true	148	1		T2	2	T93	2	T92	1
gen	zero	fail	mubi_false	969	1		T2	5	T25	1	T60	1
gen	zero	fail	mubi_true	214	1		T13	1	T14	2	T27	1
gen	zero	pass	mubi_false	894	1		T2	1	T19	1	T44	1
gen	zero	pass	mubi_true	182	1		T2	2	T3	1	T13	1
res	non_zero_bins[0]	fail	mubi_false	92	1		T2	2	T5	3	T46	1
res	non_zero_bins[0]	fail	mubi_true	125	1		T93	1	T68	3	T92	1
res	non_zero_bins[0]	pass	mubi_false	85	1		T2	2	T3	2	T5	1
res	non_zero_bins[0]	pass	mubi_true	90	1		T2	1	T8	2	T92	1
res	non_zero_bins[1]	fail	mubi_false	64	1		T9	1	T92	1	T95	1
res	non_zero_bins[1]	fail	mubi_true	71	1		T5	1	T92	2	T76	1
res	non_zero_bins[1]	pass	mubi_false	65	1		T5	1	T75	1	T93	2
res	non_zero_bins[1]	pass	mubi_true	74	1		T2	1	T30	1	T92	1
res	zero	fail	mubi_false	46	1		T5	1	T161	3	T289	2
res	zero	fail	mubi_true	46	1		T5	2	T93	1	T105	1
res	zero	pass	mubi_false	48	1		T5	2	T32	1	T95	1
res	zero	pass	mubi_true	53	1		T5	1	T26	1	T93	1
ins	non_zero_bins[0]	fail	mubi_false	263	1		T2	3	T5	7	T93	2
ins	non_zero_bins[0]	fail	mubi_true	269	1		T2	1	T3	1	T17	1
ins	non_zero_bins[0]	pass	mubi_false	265	1		T2	2	T5	3	T93	3
ins	non_zero_bins[0]	pass	mubi_true	291	1		T2	2	T5	9	T93	2
ins	non_zero_bins[1]	fail	mubi_false	190	1		T2	1	T5	6	T93	1
ins	non_zero_bins[1]	fail	mubi_true	201	1		T1	1	T2	3	T25	1
ins	non_zero_bins[1]	pass	mubi_false	218	1		T2	3	T5	3	T36	1
ins	non_zero_bins[1]	pass	mubi_true	179	1		T2	1	T5	5	T97	1
ins	zero	fail	mubi_false	947	1		T2	3	T19	1	T44	1
ins	zero	fail	mubi_true	214	1		T13	1	T18	1	T14	1
ins	zero	pass	mubi_false	976	1		T2	2	T5	17	T97	3
ins	zero	pass	mubi_true	167	1		T18	1	T25	1	T27	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded