Unified Coverage Report :: Group :: csrng_agent_pkg::device_genbits_cg

Group : csrng_agent_pkg::device_genbits_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_genbits_cg	100.00	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_genbits_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_genbits_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_genbits_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_glen	4	0	4	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_genbits_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_genbits_cross	8	0	8	100.00	100	1	1	0

Summary for Variable csrng_glen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for csrng_glen

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
glens[0]	2279	1			T1	1		T2	5		T3	9
glens[1]	44	1			T18	1		T9	1		T290	1
glens[2]	36	1			T46	1		T258	1		T291	1
glens[3]	20	1			T3	1		T32	1		T262	1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

2062

1

T1

1

T2

9

T3

6

pass

1945

1

T2

8

T3

4

T17

1

---

Summary for Cross csrng_genbits_cross

Samples crossed: csrng_glen csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for csrng_genbits_cross

Bins

csrng_glen	csrng_sts	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
glens[0]	fail	1176	1			T1	1		T2	4		T3	6
glens[0]	pass	1103	1			T2	1		T3	3		T17	1
glens[1]	fail	19	1			T292	1		T293	1		T294	1
glens[1]	pass	25	1			T18	1		T9	1		T290	1
glens[2]	fail	17	1			T258	1		T10	2		T289	1
glens[2]	pass	19	1			T46	1		T291	1		T10	2
glens[3]	fail	6	1			T262	1		T295	1		T296	1
glens[3]	pass	14	1			T3	1		T32	1		T261	1