Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.63	100.00	100.00		98.15	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	99.63	100.00	100.00		98.15	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.63	100.00	100.00		98.15	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.63	100.00	100.00		98.15	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.31	100.00	85.94			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		110	110	100.00
ALWAYS	62	3	3	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
ALWAYS	70	105	105	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	3	3
64	1	1
66	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
85	1	1
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
			MISSING_ELSE
97	1	1
98	1	1
101	1	1
102	1	1
105	1	1
106	1	1
			MISSING_ELSE
110	1	1
111	1	1
114	1	1
115	1	1
116	1	1
			MISSING_ELSE
120	1	1
121	1	1
			MISSING_ELSE
125	1	1
126	1	1
132	1	1
133	1	1
134	1	1
135	1	1
			MISSING_ELSE
139	1	1
140	1	1
141	1	1
142	1	1
			MISSING_ELSE
146	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
159	1	1
160	1	1
162	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
175	1	1
176	1	1
177	1	1
			MISSING_ELSE
181	1	1
182	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
			MISSING_ELSE
197	1	1
205	1	1
206	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
229	1	1
231	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((state_q != Idle) && (state_q != BootPulse) && (state_q != BootDone) && (state_q != SWPortMode))
             --------1--------    -----------2----------    ----------3----------    -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T19,T27,T12
1	1	0	1	Covered	T19,T27,T12
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T3,T19,T4

 LINE       66
 SUB-EXPRESSION (state_q != Idle)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != BootPulse)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != BootDone)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != SWPortMode)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       87
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T12,T62
1	1	Covered	T19,T27,T12

 LINE       89
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T3,T4,T6

 LINE       220
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T19,T4,T6

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	19	19	100.00	(Not included in score)
Transitions	54	53	98.15
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	177	Covered	T3,T8,T7
AutoCaptGenCnt	162	Covered	T3,T6,T8
AutoCaptReseedCnt	160	Covered	T3,T8,T7
AutoDispatch	142	Covered	T3,T6,T8
AutoFirstAckWait	135	Covered	T3,T6,T8
AutoLoadIns	90	Covered	T3,T4,T6
AutoSendGenCmd	170	Covered	T3,T8,T7
AutoSendReseedCmd	184	Covered	T3,T8,T9
BootCaptGenCnt	106	Covered	T19,T27,T12
BootDone	126	Covered	T19,T27,T12
BootGenAckWait	116	Covered	T19,T27,T12
BootInsAckWait	102	Covered	T19,T27,T12
BootLoadGen	98	Covered	T19,T27,T12
BootLoadIns	88	Covered	T19,T27,T12
BootPulse	121	Covered	T19,T27,T12
BootSendGenCmd	111	Covered	T19,T27,T12
Error	206	Covered	T4,T6,T12
Idle	157	Covered	T1,T2,T3
SWPortMode	93	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	149	Covered	T3,T8,T7
AutoAckWait->Error	206	Covered	T40,T153,T154
AutoAckWait->Idle	229	Covered	T68,T137,T77
AutoCaptGenCnt->AutoSendGenCmd	170	Covered	T3,T8,T7
AutoCaptGenCnt->Error	206	Covered	T6,T155
AutoCaptGenCnt->Idle	229	Covered	T114,T131,T156
AutoCaptReseedCnt->AutoSendReseedCmd	184	Covered	T3,T8,T9
AutoCaptReseedCnt->Error	206	Covered	T7
AutoCaptReseedCnt->Idle	229	Covered	T137,T157,T158
AutoDispatch->AutoCaptGenCnt	162	Covered	T3,T6,T8
AutoDispatch->AutoCaptReseedCnt	160	Covered	T3,T8,T7
AutoDispatch->Error	206	Covered	T124,T159
AutoDispatch->Idle	157	Covered	T3,T8,T9
AutoFirstAckWait->AutoDispatch	142	Covered	T3,T6,T8
AutoFirstAckWait->Error	206	Covered	T42,T116,T160
AutoFirstAckWait->Idle	229	Covered	T161,T162,T163
AutoLoadIns->AutoFirstAckWait	135	Covered	T3,T6,T8
AutoLoadIns->Error	206	Covered	T4,T164,T165
AutoLoadIns->Idle	229	Covered	T4,T6,T7
AutoSendGenCmd->AutoAckWait	177	Covered	T3,T8,T7
AutoSendGenCmd->Error	206	Covered	T166,T167,T168
AutoSendGenCmd->Idle	229	Covered	T134,T119,T126
AutoSendReseedCmd->AutoAckWait	191	Covered	T3,T8,T9
AutoSendReseedCmd->Error	206	Covered	T169
AutoSendReseedCmd->Idle	229	Covered	T68,T77,T170
BootCaptGenCnt->BootSendGenCmd	111	Covered	T19,T27,T12
BootCaptGenCnt->Error	206	Covered	T171,T172
BootCaptGenCnt->Idle	229	Covered	T130,T117
BootDone->Error	206	Covered	T12,T79,T173
BootDone->Idle	229	Covered	T136,T174,T141
BootGenAckWait->BootPulse	121	Covered	T19,T27,T12
BootGenAckWait->Error	206	Not Covered
BootGenAckWait->Idle	229	Covered	T70,T107,T111
BootInsAckWait->BootCaptGenCnt	106	Covered	T19,T27,T12
BootInsAckWait->Error	206	Covered	T175,T176,T177
BootInsAckWait->Idle	229	Covered	T12,T62,T67
BootLoadGen->BootInsAckWait	102	Covered	T19,T27,T12
BootLoadGen->Error	206	Covered	T178,T179
BootLoadGen->Idle	229	Covered	T19,T180,T113
BootLoadIns->BootLoadGen	98	Covered	T19,T27,T12
BootLoadIns->Error	206	Covered	T180,T181,T182
BootLoadIns->Idle	229	Covered	T73,T57,T183
BootPulse->BootDone	126	Covered	T19,T27,T12
BootPulse->Error	206	Covered	T128,T184,T129
BootPulse->Idle	229	Covered	T138,T56,T145
BootSendGenCmd->BootGenAckWait	116	Covered	T19,T27,T12
BootSendGenCmd->Error	206	Covered	T185
BootSendGenCmd->Idle	229	Covered	T108,T112,T186
Idle->AutoLoadIns	90	Covered	T3,T4,T6
Idle->BootLoadIns	88	Covered	T19,T27,T12
Idle->Error	206	Covered	T20,T21,T22
Idle->SWPortMode	93	Covered	T1,T2,T3
SWPortMode->Error	206	Covered	T64,T39,T78
SWPortMode->Idle	229	Covered	T2,T5,T97

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		38	38	100.00
IF	62	2	2	100.00
CASE	85	33	33	100.00
IF	205	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	62	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	85	case (state_q)
-2-:	87	if ((boot_req_mode_i && edn_enable_i))
-3-:	89	if ((auto_req_mode_i && edn_enable_i))
-4-:	91	if (edn_enable_i)
-5-:	105	if (csrng_cmd_ack_i)
-6-:	115	if (cmd_sent_i)
-7-:	120	if (csrng_cmd_ack_i)
-8-:	134	if (sw_cmd_req_load_i)
-9-:	140	if (csrng_cmd_ack_i)
-10-:	148	if (csrng_cmd_ack_i)
-11-:	155	if ((!auto_req_mode_i))
-12-:	159	if (max_reqs_cnt_zero_i)
-13-:	176	if (cmd_sent_i)
-14-:	190	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T27,T12
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T6
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T27,T12
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T27,T12
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T19,T27,T12
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T19,T27,T12
BootCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T27,T12
BootSendGenCmd	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T27,T12
BootSendGenCmd	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T12,T67,T102
BootGenAckWait	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T19,T27,T12
BootGenAckWait	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T19,T27,T12
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T27,T12
BootDone	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T27,T12
AutoLoadIns	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T6,T8
AutoLoadIns	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T3,T4,T6
AutoFirstAckWait	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T3,T6,T8
AutoFirstAckWait	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T6,T8
AutoAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T8,T7
AutoAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T3,T8,T7
AutoDispatch	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T3,T8,T9
AutoDispatch	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T3,T8,T7
AutoDispatch	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T3,T6,T8
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T8
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T8,T7
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T3,T8,T7
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T8,T7
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T8,T9
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T8,T9
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T62,T63,T65

	LineNo.	Expression
-1-:	205	if (local_escalate_i)
-2-:	220	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T12
0	1	Covered	T19,T4,T6
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	233039250	131173	0	0
FpvSecCmErrorStEscalate_A	233039250	132025	0	0
u_state_regs_A	232996250	232841449	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233039250	131173	0	0
T4	840	209	0	0
T6	1900	1072	0	0
T7	0	1112	0	0
T12	701	300	0	0
T25	2179	0	0	0
T27	1154	0	0	0
T39	0	1088	0	0
T40	0	654	0	0
T44	1558	0	0	0
T45	1491	0	0	0
T46	1274	0	0	0
T47	1444	0	0	0
T48	1783	0	0	0
T62	0	347	0	0
T63	0	478	0	0
T64	0	350	0	0
T65	0	650	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233039250	132025	0	0
T4	840	210	0	0
T6	1900	1073	0	0
T7	0	1113	0	0
T12	701	301	0	0
T25	2179	0	0	0
T27	1154	0	0	0
T39	0	1089	0	0
T40	0	655	0	0
T44	1558	0	0	0
T45	1491	0	0	0
T46	1274	0	0	0
T47	1444	0	0	0
T48	1783	0	0	0
T62	0	348	0	0
T63	0	479	0	0
T64	0	351	0	0
T65	0	651	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232996250	232841449	0	0
T1	680	626	0	0
T2	173192	173180	0	0
T3	2196	2111	0	0
T4	652	487	0	0
T13	1783	1706	0	0
T14	1385	1326	0	0
T16	1759	1680	0	0
T17	1087	1000	0	0
T18	937	853	0	0
T19	918	818	0	0