Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.94	93.94	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	93.94	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.94	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	2	19	90.48

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	2	19	90.48	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	107	1			T32	1		T30	1		T78	1
auto_req_mode	136	1			T1	1		T3	1		T10	1
sw_mode	2804	1			T29	1		T5	49		T70	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

269

1

T1

1

T10

1

T37

1

single

87

1

T3

1

T84

1

T58

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1096	1			T1	1		T37	1		T32	1
auto[2]	73	1			T29	1		T11	1		T199	1
auto[3]	136	1			T58	1		T200	1		T201	1
auto[4]	121	1			T108	10		T68	1		T202	20
auto[5]	104	1			T3	1		T203	3		T204	1
auto[6]	131	1			T34	1		T205	32		T206	1
auto[7]	1386	1			T10	1		T33	1		T30	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	2	19	90.48	2

Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	NUMBER	STATUS
[auto[2]]	[boot_req_mode]	0	1	1
[auto[4]]	[boot_req_mode]	0	1	1

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	77	1			T32	1		T78	1		T79	1
auto[1]	auto_req_mode	82	1			T1	1		T37	1		T49	1
auto[1]	sw_mode	937	1			T5	49		T70	1		T56	1
auto[2]	auto_req_mode	5	1			T11	1		T207	1		T208	1
auto[2]	sw_mode	68	1			T29	1		T199	1		T209	1
auto[3]	boot_req_mode	1	1			T210	1		-	-		-	-
auto[3]	auto_req_mode	5	1			T58	1		T200	1		T201	1
auto[3]	sw_mode	130	1			T211	1		T212	83		T213	1
auto[4]	auto_req_mode	8	1			T214	1		T215	1		T216	1
auto[4]	sw_mode	113	1			T108	10		T68	1		T202	20
auto[5]	boot_req_mode	1	1			T217	1		-	-		-	-
auto[5]	auto_req_mode	4	1			T3	1		T218	1		T219	1
auto[5]	sw_mode	99	1			T203	3		T204	1		T220	1
auto[6]	boot_req_mode	2	1			T206	1		T221	1		-	-
auto[6]	auto_req_mode	3	1			T222	1		T223	1		T224	1
auto[6]	sw_mode	126	1			T34	1		T205	32		T225	10
auto[7]	boot_req_mode	26	1			T30	1		T46	1		T45	1
auto[7]	auto_req_mode	29	1			T10	1		T40	1		T12	1
auto[7]	sw_mode	1331	1			T33	1		T39	1		T35	1