Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	558764	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4666318

1

T17

5

T18

5

T19

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1378392	1			T17	11		T18	11		T19	11
values[0x0]	1785603	1			T17	6		T18	4		T19	5
values[0x1]	2061087	1			T17	5		T18	7		T19	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	277378	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4947704

1

T17

6

T18

10

T19

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20055	1			T20	5		T23	1		T136	1
valid_sources[0x01]	19398	1			T20	2		T23	9		T141	1
valid_sources[0x02]	20569	1			T23	2		T136	1		T152	1
valid_sources[0x03]	22065	1			T20	3		T23	1		T135	8
valid_sources[0x04]	19730	1			T18	1		T20	4		T135	4
valid_sources[0x05]	21093	1			T135	6		T158	1		T155	25
valid_sources[0x06]	20541	1			T17	6		T20	1		T141	2
valid_sources[0x07]	19887	1			T20	4		T152	4		T140	1
valid_sources[0x08]	20869	1			T24	6		T136	2		T152	4
valid_sources[0x09]	19785	1			T20	3		T141	4		T136	2
valid_sources[0x0a]	21134	1			T165	1		T273	1		T227	1
valid_sources[0x0b]	19800	1			T23	2		T24	11		T134	2
valid_sources[0x0c]	20321	1			T20	1		T23	4		T24	12
valid_sources[0x0d]	21063	1			T20	1		T136	3		T152	2
valid_sources[0x0e]	20658	1			T23	8		T136	2		T137	7
valid_sources[0x0f]	20921	1			T20	2		T23	4		T142	4
valid_sources[0x10]	20166	1			T135	1		T136	8		T140	6
valid_sources[0x11]	21643	1			T23	3		T136	5		T140	4
valid_sources[0x12]	20982	1			T23	1		T141	2		T136	2
valid_sources[0x13]	18828	1			T23	1		T141	6		T136	2
valid_sources[0x14]	18905	1			T20	1		T136	6		T140	1
valid_sources[0x15]	20421	1			T20	1		T141	9		T136	4
valid_sources[0x16]	22682	1			T20	2		T134	6		T135	12
valid_sources[0x17]	20239	1			T20	1		T24	1		T136	1
valid_sources[0x18]	21500	1			T18	1		T20	2		T134	1
valid_sources[0x19]	22160	1			T20	1		T136	3		T159	1
valid_sources[0x1a]	20185	1			T20	2		T136	2		T152	3
valid_sources[0x1b]	22834	1			T20	3		T23	1		T134	1
valid_sources[0x1c]	18799	1			T21	2		T136	5		T137	9
valid_sources[0x1d]	20651	1			T18	1		T21	2		T23	4
valid_sources[0x1e]	19037	1			T19	22		T23	2		T24	2
valid_sources[0x1f]	20607	1			T21	1		T25	52		T135	33
valid_sources[0x20]	20014	1			T18	1		T20	3		T23	2
valid_sources[0x21]	20476	1			T136	1		T152	2		T140	3
valid_sources[0x22]	20352	1			T20	2		T22	3		T152	1
valid_sources[0x23]	19603	1			T20	6		T135	12		T136	1
valid_sources[0x24]	20625	1			T134	2		T136	2		T152	1
valid_sources[0x25]	20394	1			T20	5		T136	1		T152	2
valid_sources[0x26]	19826	1			T20	1		T23	1		T135	10
valid_sources[0x27]	20543	1			T20	1		T23	1		T24	1
valid_sources[0x28]	19677	1			T20	1		T22	1		T140	1
valid_sources[0x29]	19759	1			T23	4		T134	1		T136	4
valid_sources[0x2a]	22079	1			T136	5		T151	4		T155	9
valid_sources[0x2b]	20866	1			T20	2		T136	1		T140	1
valid_sources[0x2c]	19992	1			T20	1		T141	1		T152	1
valid_sources[0x2d]	18018	1			T18	1		T20	1		T23	6
valid_sources[0x2e]	22243	1			T23	2		T141	3		T142	1
valid_sources[0x2f]	20937	1			T134	4		T141	1		T136	1
valid_sources[0x30]	19934	1			T24	11		T142	4		T136	1
valid_sources[0x31]	18581	1			T23	1		T136	3		T152	2
valid_sources[0x32]	21430	1			T134	3		T136	4		T152	1
valid_sources[0x33]	20324	1			T17	2		T20	1		T23	2
valid_sources[0x34]	19151	1			T20	1		T136	3		T152	2
valid_sources[0x35]	20193	1			T20	1		T22	1		T134	1
valid_sources[0x36]	20374	1			T20	1		T24	4		T134	5
valid_sources[0x37]	21453	1			T20	3		T136	5		T152	1
valid_sources[0x38]	19379	1			T23	1		T24	4		T25	7
valid_sources[0x39]	22192	1			T136	1		T151	11		T137	2
valid_sources[0x3a]	19729	1			T20	1		T141	2		T136	2
valid_sources[0x3b]	19850	1			T20	4		T134	1		T136	1
valid_sources[0x3c]	21302	1			T20	3		T23	2		T141	1
valid_sources[0x3d]	21975	1			T20	3		T152	2		T165	3
valid_sources[0x3e]	22120	1			T20	3		T137	12		T165	2
valid_sources[0x3f]	21793	1			T134	3		T135	8		T136	1
valid_sources[0x40]	21902	1			T23	2		T24	1		T141	6
valid_sources[0x41]	22384	1			T20	2		T21	2		T24	2
valid_sources[0x42]	21671	1			T141	1		T135	15		T136	2
valid_sources[0x43]	20223	1			T136	4		T151	2		T137	2
valid_sources[0x44]	19318	1			T20	1		T136	2		T169	6
valid_sources[0x45]	20344	1			T18	1		T20	3		T136	1
valid_sources[0x46]	19528	1			T20	1		T141	2		T136	3
valid_sources[0x47]	21653	1			T20	1		T23	5		T138	1
valid_sources[0x48]	19695	1			T18	2		T20	1		T21	1
valid_sources[0x49]	20313	1			T20	1		T134	1		T136	4
valid_sources[0x4a]	20086	1			T134	4		T136	3		T152	1
valid_sources[0x4b]	21673	1			T20	1		T23	3		T134	2
valid_sources[0x4c]	19507	1			T20	1		T23	1		T134	1
valid_sources[0x4d]	18911	1			T136	3		T152	2		T137	9
valid_sources[0x4e]	19174	1			T20	1		T135	8		T136	1
valid_sources[0x4f]	18472	1			T20	1		T152	5		T137	20
valid_sources[0x50]	21831	1			T20	1		T24	1		T136	1
valid_sources[0x51]	22799	1			T20	5		T134	1		T142	1
valid_sources[0x52]	19516	1			T20	3		T136	2		T152	2
valid_sources[0x53]	20885	1			T22	1		T134	2		T136	1
valid_sources[0x54]	20488	1			T18	1		T141	1		T136	1
valid_sources[0x55]	19143	1			T20	3		T22	1		T136	2
valid_sources[0x56]	22436	1			T20	4		T22	1		T136	2
valid_sources[0x57]	21405	1			T141	1		T161	25		T169	9
valid_sources[0x58]	21161	1			T134	3		T136	5		T152	2
valid_sources[0x59]	20410	1			T134	5		T136	4		T152	1
valid_sources[0x5a]	20657	1			T17	2		T135	17		T142	1
valid_sources[0x5b]	22512	1			T20	1		T21	2		T23	1
valid_sources[0x5c]	18550	1			T142	1		T136	3		T138	1
valid_sources[0x5d]	20642	1			T22	1		T23	1		T136	5
valid_sources[0x5e]	20639	1			T24	3		T136	3		T169	7
valid_sources[0x5f]	19381	1			T24	1		T141	1		T136	3
valid_sources[0x60]	21034	1			T20	3		T23	4		T152	1
valid_sources[0x61]	22333	1			T20	3		T23	3		T136	1
valid_sources[0x62]	20327	1			T20	3		T152	5		T137	9
valid_sources[0x63]	19556	1			T20	1		T22	1		T24	3
valid_sources[0x64]	19763	1			T136	1		T152	1		T140	9
valid_sources[0x65]	20431	1			T23	6		T142	16		T152	1
valid_sources[0x66]	21133	1			T20	1		T24	12		T137	1
valid_sources[0x67]	19965	1			T23	1		T136	6		T140	1
valid_sources[0x68]	20510	1			T20	1		T136	2		T152	5
valid_sources[0x69]	19562	1			T134	5		T136	4		T152	2
valid_sources[0x6a]	19602	1			T20	1		T135	8		T152	1
valid_sources[0x6b]	22186	1			T20	2		T136	3		T152	1
valid_sources[0x6c]	20162	1			T24	1		T141	1		T136	2
valid_sources[0x6d]	22034	1			T20	1		T136	3		T151	5
valid_sources[0x6e]	19976	1			T20	1		T23	1		T24	7
valid_sources[0x6f]	19209	1			T20	1		T24	3		T142	1
valid_sources[0x70]	20157	1			T20	1		T134	3		T136	2
valid_sources[0x71]	20631	1			T136	1		T152	2		T140	1
valid_sources[0x72]	19337	1			T20	1		T23	1		T142	3
valid_sources[0x73]	18968	1			T20	3		T22	2		T141	5
valid_sources[0x74]	21786	1			T20	1		T141	1		T136	1
valid_sources[0x75]	17865	1			T20	1		T142	3		T136	1
valid_sources[0x76]	20701	1			T20	1		T24	2		T141	1
valid_sources[0x77]	20010	1			T18	1		T20	1		T21	2
valid_sources[0x78]	22535	1			T23	1		T143	12		T136	1
valid_sources[0x79]	21248	1			T20	3		T23	1		T141	1
valid_sources[0x7a]	20110	1			T22	1		T151	1		T165	1
valid_sources[0x7b]	20522	1			T20	2		T141	1		T136	3
valid_sources[0x7c]	20230	1			T20	2		T23	3		T136	2
valid_sources[0x7d]	19235	1			T20	1		T23	2		T25	7
valid_sources[0x7e]	21613	1			T134	1		T143	9		T152	4
valid_sources[0x7f]	19402	1			T20	1		T21	4		T136	1
valid_sources[0x80]	20238	1			T17	1		T23	1		T142	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1172674

1

T17

5

T18

2

T19

6

values[0x0]

all_enables

biggest_size

1748910

1

T18

2

T20

54

T21

3

values[0x1]

all_enables

biggest_size

1744734

1

T18

1

T19

2

T20

60