Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	100.00	1	100	1	64	64

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	0	52	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	0	52	100.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
non_zero_bins[0]	2472	1		T1	3	T3	2	T37	2
non_zero_bins[1]	1734	1		T1	8	T3	1	T10	5
zero	7764	1		T1	1	T2	3	T37	1

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	458	1		T29	1	T5	8	T33	1
uni	3352	1		T1	1	T29	1	T5	60
gen	3540	1		T1	8	T2	2	T3	1
res	787	1		T1	2	T3	1	T10	2
ins	3833	1		T1	1	T2	1	T3	1

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8109

T10

mubi_true

3861

T10

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

5927

T10

pass

6043

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	0	52	100.00
Automatically Generated Cross Bins	52	0	52	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	non_zero_bins[0]	fail	mubi_false	75	1		T5	2	T61	2	T66	3
upd	non_zero_bins[0]	fail	mubi_true	45	1		T33	1	T83	1	T228	1
upd	non_zero_bins[0]	pass	mubi_false	49	1		T5	1	T66	1	T229	1
upd	non_zero_bins[0]	pass	mubi_true	52	1		T108	1	T61	3	T68	1
upd	non_zero_bins[1]	fail	mubi_false	37	1		T5	1	T66	1	T230	1
upd	non_zero_bins[1]	fail	mubi_true	38	1		T61	1	T89	1	T231	1
upd	non_zero_bins[1]	pass	mubi_false	46	1		T5	2	T66	1	T231	1
upd	non_zero_bins[1]	pass	mubi_true	28	1		T5	1	T83	1	T38	1
upd	zero	fail	mubi_false	11	1		T84	1	T66	1	T232	3
upd	zero	fail	mubi_true	19	1		T66	2	T205	1	T233	1
upd	zero	pass	mubi_false	30	1		T29	1	T83	1	T231	1
upd	zero	pass	mubi_true	28	1		T5	1	T61	1	T66	1
uni	zero	fail	mubi_false	1230	1		T5	22	T70	2	T33	1
uni	zero	fail	mubi_true	464	1		T5	9	T108	1	T234	1
uni	zero	pass	mubi_false	1192	1		T1	1	T29	1	T5	22
uni	zero	pass	mubi_true	466	1		T5	7	T71	1	T108	1
gen	non_zero_bins[0]	fail	mubi_false	202	1		T5	4	T108	2	T46	1
gen	non_zero_bins[0]	fail	mubi_true	217	1		T5	5	T31	3	T34	1
gen	non_zero_bins[0]	pass	mubi_false	205	1		T3	1	T5	2	T108	3
gen	non_zero_bins[0]	pass	mubi_true	242	1		T5	3	T49	1	T83	4
gen	non_zero_bins[1]	fail	mubi_false	162	1		T1	3	T29	1	T5	1
gen	non_zero_bins[1]	fail	mubi_true	149	1		T49	1	T33	1	T83	1
gen	non_zero_bins[1]	pass	mubi_false	147	1		T1	5	T5	5	T108	1
gen	non_zero_bins[1]	pass	mubi_true	170	1		T10	2	T5	3	T49	2
gen	zero	fail	mubi_false	813	1		T32	2	T5	13	T30	1
gen	zero	fail	mubi_true	181	1		T2	2	T4	1	T5	1
gen	zero	pass	mubi_false	894	1		T5	11	T6	1	T56	1
gen	zero	pass	mubi_true	158	1		T5	1	T15	1	T46	1
res	non_zero_bins[0]	fail	mubi_false	97	1		T1	1	T37	1	T5	2
res	non_zero_bins[0]	fail	mubi_true	87	1		T108	1	T57	3	T109	1
res	non_zero_bins[0]	pass	mubi_false	85	1		T1	1	T37	1	T49	2
res	non_zero_bins[0]	pass	mubi_true	100	1		T3	1	T5	3	T31	2
res	non_zero_bins[1]	fail	mubi_false	63	1		T10	1	T5	1	T63	2
res	non_zero_bins[1]	fail	mubi_true	65	1		T5	1	T36	1	T109	1
res	non_zero_bins[1]	pass	mubi_false	69	1		T10	1	T108	1	T110	2
res	non_zero_bins[1]	pass	mubi_true	52	1		T5	1	T235	1	T111	2
res	zero	fail	mubi_false	54	1		T5	1	T80	1	T236	2
res	zero	fail	mubi_true	39	1		T66	1	T12	1	T237	2
res	zero	pass	mubi_false	51	1		T5	1	T58	2	T80	1
res	zero	pass	mubi_true	25	1		T108	1	T86	1	T12	1
ins	non_zero_bins[0]	fail	mubi_false	262	1		T1	1	T29	1	T5	5
ins	non_zero_bins[0]	fail	mubi_true	242	1		T5	5	T34	1	T39	1
ins	non_zero_bins[0]	pass	mubi_false	258	1		T5	9	T34	1	T108	2
ins	non_zero_bins[0]	pass	mubi_true	254	1		T5	6	T108	2	T238	1
ins	non_zero_bins[1]	fail	mubi_false	160	1		T10	1	T37	1	T5	2
ins	non_zero_bins[1]	fail	mubi_true	189	1		T33	1	T108	1	T83	2
ins	non_zero_bins[1]	pass	mubi_false	168	1		T5	3	T70	1	T86	1
ins	non_zero_bins[1]	pass	mubi_true	191	1		T3	1	T5	3	T11	1
ins	zero	fail	mubi_false	855	1		T4	1	T5	9	T6	1
ins	zero	fail	mubi_true	171	1		T37	1	T32	1	T5	4
ins	zero	pass	mubi_false	894	1		T4	1	T5	13	T56	1
ins	zero	pass	mubi_true	189	1		T2	1	T32	1	T5	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded