Unified Coverage Report :: Group :: csrng_agent_pkg::device_genbits_cg

Group : csrng_agent_pkg::device_genbits_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_genbits_cg	100.00	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_genbits_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_genbits_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_genbits_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_glen	4	0	4	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_genbits_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_genbits_cross	8	0	8	100.00	100	1	1	0

Summary for Variable csrng_glen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for csrng_glen

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
glens[0]	2000	1			T1	7		T2	2		T32	2
glens[1]	26	1			T209	1		T200	1		T214	1
glens[2]	24	1			T1	1		T46	1		T235	1
glens[3]	16	1			T84	1		T110	3		T77	1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

1724

1

T1

3

T2

2

T32

2

pass

1816

1

T1

5

T3

1

T10

2

---

Summary for Cross csrng_genbits_cross

Samples crossed: csrng_glen csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for csrng_genbits_cross

Bins

csrng_glen	csrng_sts	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
glens[0]	fail	984	1			T1	3		T2	2		T32	2
glens[0]	pass	1016	1			T1	4		T5	9		T49	3
glens[1]	fail	14	1			T200	1		T239	1		T240	1
glens[1]	pass	12	1			T209	1		T214	1		T220	1
glens[2]	fail	12	1			T46	1		T241	1		T242	1
glens[2]	pass	12	1			T1	1		T235	1		T243	1
glens[3]	fail	4	1			T84	1		T77	1		T208	1
glens[3]	pass	12	1			T110	3		T88	2		T244	1