Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	605900	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4996068

1

T24

26

T25

8

T26

150

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1491289	1			T24	31		T25	10		T26	85
values[0x0]	1908337	1			T24	13		T25	4		T26	55
values[0x1]	2202342	1			T24	11		T25	6		T26	49

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	303803	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5298165

1

T24

32

T25

12

T26

163

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22916	1			T26	3		T30	1		T178	1
valid_sources[0x01]	23151	1			T26	1		T177	3		T178	2
valid_sources[0x02]	22818	1			T29	1		T145	1		T160	1
valid_sources[0x03]	18876	1			T26	1		T29	8		T30	2
valid_sources[0x04]	22829	1			T26	1		T29	2		T177	3
valid_sources[0x05]	20602	1			T24	2		T51	1		T30	1
valid_sources[0x06]	21160	1			T26	2		T27	1		T51	1
valid_sources[0x07]	22714	1			T25	1		T27	1		T85	1
valid_sources[0x08]	22524	1			T26	1		T29	1		T178	1
valid_sources[0x09]	22503	1			T26	3		T50	1		T177	9
valid_sources[0x0a]	21338	1			T26	2		T85	1		T199	1
valid_sources[0x0b]	21054	1			T26	5		T85	1		T152	1
valid_sources[0x0c]	22423	1			T26	2		T30	1		T145	2
valid_sources[0x0d]	24047	1			T26	1		T30	1		T145	1
valid_sources[0x0e]	22589	1			T199	2		T145	3		T146	16
valid_sources[0x0f]	22693	1			T85	2		T199	1		T179	5
valid_sources[0x10]	23529	1			T29	2		T30	1		T199	2
valid_sources[0x11]	22984	1			T85	1		T152	1		T161	1
valid_sources[0x12]	22723	1			T152	1		T30	3		T199	1
valid_sources[0x13]	22139	1			T26	6		T199	1		T172	1
valid_sources[0x14]	21744	1			T30	1		T199	1		T145	1
valid_sources[0x15]	23448	1			T26	1		T85	1		T30	1
valid_sources[0x16]	21124	1			T26	3		T85	2		T145	1
valid_sources[0x17]	20256	1			T26	4		T29	5		T199	1
valid_sources[0x18]	22285	1			T29	6		T85	2		T86	2
valid_sources[0x19]	23216	1			T85	1		T177	6		T30	2
valid_sources[0x1a]	21620	1			T26	1		T85	1		T30	2
valid_sources[0x1b]	20647	1			T30	1		T199	1		T146	3
valid_sources[0x1c]	21362	1			T26	7		T29	11		T30	4
valid_sources[0x1d]	22607	1			T26	4		T177	2		T199	1
valid_sources[0x1e]	19575	1			T26	1		T152	1		T30	1
valid_sources[0x1f]	22068	1			T27	1		T85	2		T199	1
valid_sources[0x20]	22832	1			T29	1		T199	3		T145	2
valid_sources[0x21]	20522	1			T152	1		T199	1		T170	25
valid_sources[0x22]	23282	1			T85	1		T30	1		T199	2
valid_sources[0x23]	22902	1			T26	2		T30	1		T178	4
valid_sources[0x24]	21218	1			T26	2		T85	1		T86	3
valid_sources[0x25]	24018	1			T85	1		T177	2		T30	2
valid_sources[0x26]	20813	1			T29	8		T199	2		T145	1
valid_sources[0x27]	21059	1			T50	1		T30	2		T160	1
valid_sources[0x28]	20312	1			T26	1		T27	1		T51	2
valid_sources[0x29]	21477	1			T85	2		T30	1		T199	2
valid_sources[0x2a]	21574	1			T199	1		T145	2		T148	2
valid_sources[0x2b]	22604	1			T25	1		T26	1		T178	1
valid_sources[0x2c]	21308	1			T29	5		T86	8		T199	1
valid_sources[0x2d]	21848	1			T27	1		T85	1		T177	9
valid_sources[0x2e]	20684	1			T26	3		T29	5		T85	1
valid_sources[0x2f]	21498	1			T30	1		T199	1		T146	1
valid_sources[0x30]	21968	1			T27	1		T51	1		T30	1
valid_sources[0x31]	20790	1			T26	2		T152	1		T149	1
valid_sources[0x32]	21005	1			T26	2		T29	3		T85	2
valid_sources[0x33]	21382	1			T51	1		T30	1		T199	1
valid_sources[0x34]	22757	1			T50	1		T145	2		T172	2
valid_sources[0x35]	23250	1			T29	2		T85	2		T30	1
valid_sources[0x36]	21826	1			T27	1		T85	2		T199	1
valid_sources[0x37]	20404	1			T26	2		T86	3		T30	2
valid_sources[0x38]	22212	1			T26	1		T30	1		T199	2
valid_sources[0x39]	23679	1			T25	3		T85	2		T152	1
valid_sources[0x3a]	20405	1			T85	1		T30	1		T199	1
valid_sources[0x3b]	21828	1			T26	2		T85	1		T199	3
valid_sources[0x3c]	21876	1			T85	1		T50	2		T30	1
valid_sources[0x3d]	22333	1			T26	1		T29	1		T85	1
valid_sources[0x3e]	21384	1			T26	1		T30	5		T199	1
valid_sources[0x3f]	23373	1			T199	1		T172	4		T162	3
valid_sources[0x40]	20435	1			T29	3		T30	2		T199	1
valid_sources[0x41]	21246	1			T199	2		T178	3		T172	1
valid_sources[0x42]	23526	1			T26	1		T145	1		T146	1
valid_sources[0x43]	21223	1			T26	2		T29	1		T30	1
valid_sources[0x44]	21485	1			T26	1		T27	1		T29	2
valid_sources[0x45]	23206	1			T27	1		T85	2		T199	1
valid_sources[0x46]	21826	1			T85	1		T30	1		T199	2
valid_sources[0x47]	22044	1			T85	1		T86	10		T30	1
valid_sources[0x48]	20948	1			T85	1		T30	1		T145	1
valid_sources[0x49]	20986	1			T24	3		T29	1		T30	2
valid_sources[0x4a]	21158	1			T152	1		T30	1		T199	1
valid_sources[0x4b]	22066	1			T24	5		T27	1		T85	1
valid_sources[0x4c]	21670	1			T26	1		T50	3		T30	1
valid_sources[0x4d]	21459	1			T26	1		T27	1		T85	1
valid_sources[0x4e]	22229	1			T26	1		T27	1		T199	1
valid_sources[0x4f]	22123	1			T26	1		T29	1		T85	1
valid_sources[0x50]	20940	1			T27	1		T85	1		T30	1
valid_sources[0x51]	22065	1			T85	1		T30	1		T199	1
valid_sources[0x52]	20625	1			T26	3		T30	2		T199	1
valid_sources[0x53]	22549	1			T26	1		T85	1		T30	2
valid_sources[0x54]	23067	1			T27	1		T85	2		T145	4
valid_sources[0x55]	21742	1			T26	3		T27	1		T152	1
valid_sources[0x56]	19844	1			T26	1		T152	1		T30	1
valid_sources[0x57]	21862	1			T24	7		T199	1		T161	3
valid_sources[0x58]	21462	1			T26	1		T85	1		T30	1
valid_sources[0x59]	23019	1			T26	1		T27	1		T85	1
valid_sources[0x5a]	21489	1			T85	1		T50	2		T30	1
valid_sources[0x5b]	22094	1			T27	1		T30	2		T199	1
valid_sources[0x5c]	21857	1			T29	4		T85	1		T51	1
valid_sources[0x5d]	22700	1			T25	1		T26	5		T29	1
valid_sources[0x5e]	20193	1			T29	7		T85	1		T177	9
valid_sources[0x5f]	22064	1			T199	2		T179	8		T148	13
valid_sources[0x60]	21170	1			T27	2		T29	9		T30	1
valid_sources[0x61]	20868	1			T26	4		T29	12		T152	1
valid_sources[0x62]	21938	1			T145	4		T146	10		T162	16
valid_sources[0x63]	22306	1			T85	2		T30	1		T199	1
valid_sources[0x64]	21209	1			T24	1		T152	1		T178	2
valid_sources[0x65]	20726	1			T29	2		T152	1		T145	1
valid_sources[0x66]	20562	1			T27	1		T177	8		T30	1
valid_sources[0x67]	20814	1			T24	15		T26	3		T50	1
valid_sources[0x68]	19529	1			T27	1		T199	3		T149	1
valid_sources[0x69]	23341	1			T50	1		T145	2		T172	1
valid_sources[0x6a]	21402	1			T29	2		T85	1		T30	1
valid_sources[0x6b]	20671	1			T85	2		T50	1		T30	1
valid_sources[0x6c]	21801	1			T26	2		T177	45		T30	1
valid_sources[0x6d]	21663	1			T29	3		T177	7		T30	1
valid_sources[0x6e]	22182	1			T29	6		T85	1		T146	32
valid_sources[0x6f]	22478	1			T29	1		T85	2		T51	1
valid_sources[0x70]	22426	1			T26	1		T27	1		T85	1
valid_sources[0x71]	23048	1			T29	1		T85	1		T145	2
valid_sources[0x72]	20899	1			T85	1		T177	15		T199	1
valid_sources[0x73]	20398	1			T26	2		T27	2		T85	1
valid_sources[0x74]	22046	1			T26	3		T199	1		T145	2
valid_sources[0x75]	20200	1			T30	1		T199	1		T149	1
valid_sources[0x76]	22231	1			T26	2		T86	4		T30	1
valid_sources[0x77]	20685	1			T26	2		T152	1		T148	22
valid_sources[0x78]	21417	1			T85	1		T30	1		T199	1
valid_sources[0x79]	22603	1			T26	1		T30	1		T199	2
valid_sources[0x7a]	21602	1			T199	1		T145	1		T174	3
valid_sources[0x7b]	21835	1			T51	1		T152	1		T30	1
valid_sources[0x7c]	21364	1			T29	4		T85	2		T30	2
valid_sources[0x7d]	23429	1			T24	3		T26	1		T30	1
valid_sources[0x7e]	20357	1			T27	1		T85	3		T199	1
valid_sources[0x7f]	22776	1			T26	3		T85	1		T30	1
valid_sources[0x80]	23722	1			T29	1		T85	1		T30	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1258239

1

T24

14

T25

5

T26

53

values[0x0]

all_enables

biggest_size

1870144

1

T24

9

T25

2

T26

51

values[0x1]

all_enables

biggest_size

1867685

1

T24

3

T25

1

T26

46