Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	100.00	1	100	1	64	64

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	0	52	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	0	52	100.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
non_zero_bins[0]	2645	1		T2	8	T3	2	T6	2
non_zero_bins[1]	1825	1		T2	6	T3	1	T4	18
zero	7761	1		T2	19	T6	2	T31	3

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	529	1		T2	2	T4	4	T37	1
uni	3407	1		T2	10	T6	1	T31	1
gen	3630	1		T2	9	T3	1	T6	1
res	810	1		T2	2	T3	1	T6	1
ins	3855	1		T2	10	T3	1	T6	1

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8251

mubi_true

3980

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

6099

pass

6132

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	0	52	100.00
Automatically Generated Cross Bins	52	0	52	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	non_zero_bins[0]	fail	mubi_false	53	1		T2	1	T101	2	T110	1
upd	non_zero_bins[0]	fail	mubi_true	74	1		T2	1	T4	1	T64	1
upd	non_zero_bins[0]	pass	mubi_false	61	1		T115	1	T217	3	T218	1
upd	non_zero_bins[0]	pass	mubi_true	54	1		T101	1	T217	1	T136	1
upd	non_zero_bins[1]	fail	mubi_false	44	1		T37	1	T101	2	T107	1
upd	non_zero_bins[1]	fail	mubi_true	52	1		T60	1	T101	1	T103	1
upd	non_zero_bins[1]	pass	mubi_false	46	1		T4	1	T109	1	T217	1
upd	non_zero_bins[1]	pass	mubi_true	39	1		T83	2	T101	3	T109	1
upd	zero	fail	mubi_false	26	1		T4	1	T219	1	T101	2
upd	zero	fail	mubi_true	21	1		T107	2	T217	2	T220	2
upd	zero	pass	mubi_false	30	1		T221	1	T217	1	T222	1
upd	zero	pass	mubi_true	29	1		T4	1	T101	1	T217	1
uni	zero	fail	mubi_false	1302	1		T2	2	T4	10	T52	1
uni	zero	fail	mubi_true	439	1		T4	9	T124	1	T83	3
uni	zero	pass	mubi_false	1215	1		T2	7	T6	1	T32	1
uni	zero	pass	mubi_true	451	1		T2	1	T31	1	T4	13
gen	non_zero_bins[0]	fail	mubi_false	268	1		T32	1	T4	1	T114	1
gen	non_zero_bins[0]	fail	mubi_true	222	1		T4	3	T34	1	T10	2
gen	non_zero_bins[0]	pass	mubi_false	281	1		T2	1	T3	1	T4	3
gen	non_zero_bins[0]	pass	mubi_true	217	1		T2	1	T6	1	T4	2
gen	non_zero_bins[1]	fail	mubi_false	163	1		T4	2	T41	1	T42	1
gen	non_zero_bins[1]	fail	mubi_true	157	1		T2	2	T4	3	T101	1
gen	non_zero_bins[1]	pass	mubi_false	156	1		T2	1	T4	1	T126	1
gen	non_zero_bins[1]	pass	mubi_true	159	1		T4	1	T101	5	T223	1
gen	zero	fail	mubi_false	829	1		T2	4	T4	12	T34	1
gen	zero	fail	mubi_true	182	1		T17	1	T18	2	T80	1
gen	zero	pass	mubi_false	798	1		T31	1	T4	14	T52	1
gen	zero	pass	mubi_true	198	1		T17	1	T4	1	T106	1
res	non_zero_bins[0]	fail	mubi_false	92	1		T10	1	T63	1	T101	1
res	non_zero_bins[0]	fail	mubi_true	87	1		T32	1	T125	1	T11	1
res	non_zero_bins[0]	pass	mubi_false	97	1		T2	2	T10	2	T63	1
res	non_zero_bins[0]	pass	mubi_true	106	1		T4	1	T11	1	T224	2
res	non_zero_bins[1]	fail	mubi_false	64	1		T12	2	T217	2	T13	2
res	non_zero_bins[1]	fail	mubi_true	67	1		T3	1	T34	1	T62	1
res	non_zero_bins[1]	pass	mubi_false	70	1		T33	1	T48	1	T114	1
res	non_zero_bins[1]	pass	mubi_true	62	1		T42	2	T62	1	T64	1
res	zero	fail	mubi_false	41	1		T6	1	T41	2	T102	1
res	zero	fail	mubi_true	43	1		T225	1	T104	1	T217	1
res	zero	pass	mubi_false	44	1		T4	1	T83	1	T103	1
res	zero	pass	mubi_true	37	1		T64	1	T101	1	T225	1
ins	non_zero_bins[0]	fail	mubi_false	238	1		T2	1	T38	1	T83	2
ins	non_zero_bins[0]	fail	mubi_true	260	1		T4	4	T10	2	T125	1
ins	non_zero_bins[0]	pass	mubi_false	261	1		T6	1	T4	4	T37	1
ins	non_zero_bins[0]	pass	mubi_true	274	1		T2	1	T3	1	T4	8
ins	non_zero_bins[1]	fail	mubi_false	161	1		T2	1	T4	3	T33	1
ins	non_zero_bins[1]	fail	mubi_true	199	1		T2	1	T4	2	T126	1
ins	non_zero_bins[1]	pass	mubi_false	212	1		T4	4	T35	1	T114	1
ins	non_zero_bins[1]	pass	mubi_true	174	1		T2	1	T4	1	T126	1
ins	zero	fail	mubi_false	841	1		T2	2	T4	18	T124	1
ins	zero	fail	mubi_true	174	1		T34	2	T108	2	T106	1
ins	zero	pass	mubi_false	858	1		T2	3	T31	1	T32	1
ins	zero	pass	mubi_true	203	1		T17	1	T4	1	T106	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded