Module Definition
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Module : prim_subreg_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_sw_cmd_sts_cmd_reg_rdy.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_sw_cmd_sts_cmd_rdy.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_sw_cmd_sts_cmd_sts.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_sw_cmd_sts_cmd_ack.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_err_code_sfifo_rescmd_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_err_code_sfifo_gencmd_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_err_code_sfifo_output_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_err_code_edn_ack_sm_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_err_code_edn_main_sm_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_err_code_edn_cntr_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_err_code_fifo_write_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_err_code_fifo_read_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_err_code_fifo_state_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_main_sm_state.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_intr_state_edn_cmd_req_done.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_edn_fatal_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_edn_cmd_req_done.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_edn_fatal_err.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_regwen.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_edn_enable.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_boot_req_mode.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_auto_req_mode.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_cmd_fifo_rst.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_boot_ins_cmd.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_boot_gen_cmd.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_num_reqs_between_reseeds.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_recov_alert_sts_edn_enable_field_alert.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_recov_alert_sts_boot_req_mode_field_alert.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_recov_alert_sts_auto_req_mode_field_alert.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_recov_alert_sts_cmd_fifo_rst_field_alert.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_recov_alert_sts_edn_bus_cmp_alert.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_err_code_test.wr_en_data_arb 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_edn_cmd_req_done.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_edn_fatal_err.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
110 1 1

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=4,SwAccess=0,Mubi=1 + DW=32,SwAccess=0,Mubi=0 + DW=5,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_edn_cmd_req_done.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_edn_fatal_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_edn_enable.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_boot_req_mode.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_auto_req_mode.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_cmd_fifo_rst.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_boot_ins_cmd.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_boot_gen_cmd.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_num_reqs_between_reseeds.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_err_code_test.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_regwen.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_recov_alert_sts_edn_enable_field_alert.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_recov_alert_sts_boot_req_mode_field_alert.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_recov_alert_sts_auto_req_mode_field_alert.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_recov_alert_sts_cmd_fifo_rst_field_alert.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_recov_alert_sts_edn_bus_cmp_alert.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 + DW=9,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
50.00 50.00
tb.dut.u_reg.u_sw_cmd_sts_cmd_reg_rdy.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_sw_cmd_sts_cmd_rdy.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_sw_cmd_sts_cmd_sts.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_sw_cmd_sts_cmd_ack.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_err_code_sfifo_rescmd_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_err_code_sfifo_gencmd_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_err_code_sfifo_output_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_err_code_edn_ack_sm_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_err_code_edn_main_sm_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_err_code_edn_cntr_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_err_code_fifo_write_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_err_code_fifo_read_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_err_code_fifo_state_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_main_sm_state.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 1 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Cond Coverage for Module : prim_subreg_arb ( parameter DW=5,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_err_code_test.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT24,T25,T26
01Unreachable
10CoveredT2,T31,T17 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT2,T31,T17 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT2,T31,T17
Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_edn_cmd_req_done.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_edn_fatal_err.wr_en_data_arb

TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT24,T25,T27
10CoveredT25,T28,T51 

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT25,T28,T51
11CoveredT24,T25,T27 

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT24,T25,T27 

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT25,T28,T51
Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_edn_cmd_req_done.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_edn_fatal_err.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT24,T25,T26
01Unreachable
10CoveredT24,T25,T26 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT24,T25,T26 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT24,T25,T26
Cond Coverage for Module : prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_edn_enable.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_boot_req_mode.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_auto_req_mode.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_cmd_fifo_rst.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT24,T25,T26
01Unreachable
10CoveredT2,T3,T6 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT2,T3,T6 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT2,T3,T6
Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_regwen.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_alert_sts_edn_enable_field_alert.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_alert_sts_boot_req_mode_field_alert.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_alert_sts_auto_req_mode_field_alert.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_alert_sts_cmd_fifo_rst_field_alert.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_alert_sts_edn_bus_cmp_alert.wr_en_data_arb

TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT17,T18,T19
10CoveredT24,T26,T27 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT29,T84,T177
11CoveredT24,T25,T26 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT17,T18,T19 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT24,T26,T27
Cond Coverage for Module : prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_boot_ins_cmd.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_boot_gen_cmd.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_num_reqs_between_reseeds.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT24,T25,T26
01Unreachable
10CoveredT24,T26,T27 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT24,T26,T27 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT24,T25,T26
1CoveredT24,T26,T27
Branch Coverage for Module : prim_subreg_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T24,T25,T26

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%