Unified Coverage Report :: Cond split page

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 LINE       294
 EXPRESSION (csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)
             ------------1------------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T3,T34,T10
1	1	Covered	T2,T3,T6

 LINE       299
 EXPRESSION (edn_cntr_err_sum || edn_main_sm_err_sum || edn_ack_sm_err_sum)
             --------1-------    ---------2---------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T8,T78,T79
0	1	0	Covered	T75,T76,T77
1	0	0	Covered	T7,T15,T16

 LINE       304
 EXPRESSION ((edn_enable_fo[FatalErr] && (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum || sfifo_output_err_sum)) || fatal_loc_events)
             -------------------------------------------------1-------------------------------------------------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T75,T8
1	0	Covered	T5,T23,T87

 LINE       304
 SUB-EXPRESSION (edn_enable_fo[FatalErr] && (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum || sfifo_output_err_sum))
                 -----------1-----------    -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T23,T87
1	0	Covered	T2,T3,T6
1	1	Covered	T5,T23,T87

 LINE       304
 SUB-EXPRESSION (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum || sfifo_output_err_sum)
                 ----------1---------    ----------2---------    ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T23,T88,T89
1	0	0	Covered	T5,T87,T90

 LINE       311
 EXPRESSION (((|sfifo_rescmd_err)) || err_code_test_bit[0])
             ----------1----------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T5,T87,T90

 LINE       313
 EXPRESSION (((|sfifo_gencmd_err)) || err_code_test_bit[1])
             ----------1----------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T23,T88,T89

 LINE       315
 EXPRESSION (((|sfifo_output_err)) || err_code_test_bit[2])
             ----------1----------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       317
 EXPRESSION (((|edn_ack_sm_err)) || err_code_test_bit[20])
             ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T7,T75,T8

 LINE       319
 EXPRESSION (edn_main_sm_err || err_code_test_bit[21])
             -------1-------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T7,T75,T8

 LINE       321
 EXPRESSION (edn_cntr_err || err_code_test_bit[22])
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T7,T15,T16

 LINE       324
 EXPRESSION (sfifo_rescmd_err[2] || sfifo_gencmd_err[2] || sfifo_output_err[2] || err_code_test_bit[28])
             ---------1---------    ---------2---------    ---------3---------    ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Covered	T91,T92,T93
1	0	0	0	Covered	T94,T95,T96

 LINE       329
 EXPRESSION (sfifo_rescmd_err[1] || sfifo_gencmd_err[1] || sfifo_output_err[1] || err_code_test_bit[29])
             ---------1---------    ---------2---------    ---------3---------    ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Covered	T88,T97,T98
1	0	0	0	Covered	T5,T90

 LINE       334
 EXPRESSION (sfifo_rescmd_err[0] || sfifo_gencmd_err[0] || sfifo_output_err[0] || err_code_test_bit[30])
             ---------1---------    ---------2---------    ---------3---------    ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Covered	T23,T89,T91
1	0	0	0	Covered	T87,T99,T100

 LINE       343
 EXPRESSION (edn_enable_fo[ReseedCmdErr] && sfifo_rescmd_err_sum)
             -------------1-------------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T5,T87,T90
1	0	Covered	T2,T3,T6
1	1	Covered	T5,T87,T90

 LINE       346
 EXPRESSION (edn_enable_fo[GenCmdErr] && sfifo_gencmd_err_sum)
             ------------1-----------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T23,T89,T91
1	0	Covered	T2,T3,T6
1	1	Covered	T23,T88,T89

 LINE       349
 EXPRESSION (edn_enable_fo[OutputErr] && sfifo_output_err_sum)
             ------------1-----------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T6
1	1	Not Covered

 LINE       366
 EXPRESSION (edn_enable_fo[FifoWrErr] && fifo_write_err_sum)
             ------------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T91,T92,T94
1	0	Covered	T2,T3,T6
1	1	Covered	T91,T92,T94

 LINE       369
 EXPRESSION (edn_enable_fo[FifoRdErr] && fifo_read_err_sum)
             ------------1-----------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T5,T90,T97
1	0	Covered	T2,T3,T6
1	1	Covered	T5,T88,T90

 LINE       372
 EXPRESSION (edn_enable_fo[FifoStErr] && fifo_status_err_sum)
             ------------1-----------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T23,T87,T99
1	0	Covered	T2,T3,T6
1	1	Covered	T23,T87,T99

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 0) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 1) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Not Covered
1	1	Not Covered

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 1)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 2) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Not Covered
1	1	Not Covered

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 2)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 3) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T4,T83,T101
1	1	Covered	T4,T83,T101

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 3)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T83,T101

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 4) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T11,T101,T102
1	1	Covered	T11,T101,T102

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 4)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T101,T102

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 5) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T101,T103,T104
1	1	Covered	T101,T103,T104

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 5)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T101,T103,T104

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 6) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T4,T101,T105
1	1	Covered	T4,T101,T105

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 6)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T101,T105

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 7) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T4,T36,T8
1	1	Covered	T4,T36,T8

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 7)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T36,T8

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 8) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T2,T106,T107
1	1	Covered	T2,T106,T107

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 8)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T106,T107

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 9) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T4,T5,T62
1	1	Covered	T4,T5,T62

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 9)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T62

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 10) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T4,T33,T18
1	1	Covered	T4,T33,T18

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 10)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T33,T18

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 11) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T4
1	0	Covered	T17,T10,T108
1	1	Covered	T17,T10,T108

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 11)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T10,T108

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 12) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T2,T4,T60
1	1	Covered	T2,T4,T60

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 12)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T60

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 13) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T4,T64,T101
1	1	Covered	T4,T64,T101

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 13)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T64,T101

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 14) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T4,T8,T101
1	1	Covered	T4,T8,T101

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 14)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T101

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 15) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T4,T81,T61
1	1	Covered	T4,T81,T61

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 15)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T81,T61

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 16) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T2,T4,T82
1	1	Covered	T2,T4,T82

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 16)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T82

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 17) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T4,T79,T109
1	1	Covered	T4,T79,T109

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 17)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T79,T109

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 18) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T2,T64,T65
1	1	Covered	T2,T64,T65

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 18)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T64,T65

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 19) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T10,T11,T101
1	1	Covered	T10,T11,T101

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 19)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T101

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 20) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Not Covered
1	1	Not Covered

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 20)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 21) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Not Covered
1	1	Not Covered

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 21)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 22) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Not Covered
1	1	Not Covered

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 22)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 23) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T4,T35,T80
1	1	Covered	T4,T35,T80

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 23)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T35,T80

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 24) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T4,T101,T107
1	1	Covered	T4,T101,T107

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 24)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T101,T107

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 25) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 25)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 26) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T4,T101,T110
1	1	Covered	T4,T101,T110

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 26)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T101,T110

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 27) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Covered	T2,T4,T111
1	1	Covered	T2,T4,T111

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 27)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T111

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 28) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Not Covered
1	1	Not Covered

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 28)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 29) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Not Covered
1	1	Not Covered

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 29)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       377
 EXPRESSION ((reg2hw.err_code_test.q == 30) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T31,T17
1	0	Not Covered
1	1	Not Covered

 LINE       377
 SUB-EXPRESSION (reg2hw.err_code_test.q == 30)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       385
 SUB-EXPRESSION (reg2hw.alert_test.recov_alert.q && reg2hw.alert_test.recov_alert.qe)
                 ---------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T112,T113
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T112,T113

 LINE       389
 SUB-EXPRESSION (reg2hw.alert_test.fatal_alert.q && reg2hw.alert_test.fatal_alert.qe)
                 ---------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T112,T113
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T112,T113

 LINE       465
 EXPRESSION (reg2hw.sw_cmd_req.qe && cmd_reg_rdy_q)
             ----------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T3,T114,T41
1	1	Covered	T2,T3,T6

 LINE       477
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReq])) ? '0 : (boot_wr_cmd_reg ? boot_ins_cmd : (sw_cmd_req_load ? sw_cmd_req_bus : (boot_wr_cmd_uni ? 32'b00000000000000000000000000000101 : cs_cmd_req_q))))

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       477
 SUB-EXPRESSION (boot_wr_cmd_reg ? boot_ins_cmd : (sw_cmd_req_load ? sw_cmd_req_bus : (boot_wr_cmd_uni ? 32'b00000000000000000000000000000101 : cs_cmd_req_q)))
                 -------1-------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T34,T108,T106

 LINE       477
 SUB-EXPRESSION (sw_cmd_req_load ? sw_cmd_req_bus : (boot_wr_cmd_uni ? 32'b00000000000000000000000000000101 : cs_cmd_req_q))
                 -------1-------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T3,T6

 LINE       477
 SUB-EXPRESSION (boot_wr_cmd_uni ? 32'b00000000000000000000000000000101 : cs_cmd_req_q)
                 -------1-------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T34,T39,T115

 LINE       484
 EXPRESSION (((!edn_enable_fo[CsrngCmdReqValid])) ? '0 : (sw_cmd_req_load || boot_wr_cmd_reg || boot_wr_cmd_uni))
             ------------------1-----------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       484
 SUB-EXPRESSION (sw_cmd_req_load || boot_wr_cmd_reg || boot_wr_cmd_uni)
                 -------1-------    -------2-------    -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T2,T3,T6
0	0	1	Covered	T34,T39,T115
0	1	0	Covered	T34,T108,T106
1	0	0	Covered	T2,T3,T6

 LINE       488
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqOut])) ? '0 : (send_rescmd ? sfifo_rescmd_rdata : ((send_gencmd || boot_send_gencmd) ? sfifo_gencmd_rdata : cs_cmd_req_q)))

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       488
 SUB-EXPRESSION (send_rescmd ? sfifo_rescmd_rdata : ((send_gencmd || boot_send_gencmd) ? sfifo_gencmd_rdata : cs_cmd_req_q))
                 -----1-----

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T3,T10,T11

 LINE       488
 SUB-EXPRESSION ((send_gencmd || boot_send_gencmd) ? sfifo_gencmd_rdata : cs_cmd_req_q)
                 ----------------1----------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T3,T34,T10

 LINE       488
 SUB-EXPRESSION (send_gencmd || boot_send_gencmd)
                 -----1-----    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T34,T108,T106
1	0	Covered	T3,T10,T11

 LINE       494
 EXPRESSION (((!edn_enable_fo[CsrngCmdReqValidOut])) ? '0 : ((send_rescmd || send_gencmd || (boot_send_gencmd && cmd_sent)) ? 1'b1 : cs_cmd_req_vld_q))
             -------------------1-------------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       494
 SUB-EXPRESSION ((send_rescmd || send_gencmd || (boot_send_gencmd && cmd_sent)) ? 1'b1 : cs_cmd_req_vld_q)
                 -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T3,T34,T10

 LINE       494
 SUB-EXPRESSION (send_rescmd || send_gencmd || (boot_send_gencmd && cmd_sent))
                 -----1-----    -----2-----    ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T2,T3,T6
0	0	1	Covered	T34,T108,T106
0	1	0	Covered	T3,T10,T11
1	0	0	Covered	T3,T10,T11

 LINE       494
 SUB-EXPRESSION (boot_send_gencmd && cmd_sent)
                 --------1-------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Not Covered
1	1	Covered	T34,T108,T106

 LINE       504
 EXPRESSION (((!sw_cmd_req_load)) && cmd_rdy_q && cmd_reg_rdy_d)
             ----------1---------    ----2----    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T6
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T2,T3,T6

 LINE       508
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (((!sw_cmd_valid)) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)))))

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       508
 SUB-EXPRESSION (((!sw_cmd_valid)) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q))))
                 --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T3,T34,T10

 LINE       508
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)))
                 -------1-------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T3,T6

 LINE       508
 SUB-EXPRESSION (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q))
                 ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T3,T6

 LINE       508
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T3,T6

 LINE       519
 EXPRESSION (((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (((!sw_cmd_valid)) ? 1'b0 : sfifo_output_rdy))
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       519
 SUB-EXPRESSION (((!sw_cmd_valid)) ? 1'b0 : sfifo_output_rdy)
                 --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T3,T34,T10

 LINE       524
 EXPRESSION (((!sfifo_output_full)) && ( ! ((sfifo_output_depth == (OutputFifoDepth - 1)) && (sfifo_output_push || sw_cmd_req_load)) ))
             -----------1----------    -----------------------------------------------2-----------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       524
 SUB-EXPRESSION ( ! ((sfifo_output_depth == (OutputFifoDepth - 1)) && (sfifo_output_push || sw_cmd_req_load)) )
                    --------------------------------------------1--------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       524
 SUB-EXPRESSION ((sfifo_output_depth == (OutputFifoDepth - 1)) && (sfifo_output_push || sw_cmd_req_load))
                 ----------------------1----------------------    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Not Covered
1	1	Not Covered

 LINE       524
 SUB-EXPRESSION (sfifo_output_depth == (OutputFifoDepth - 1))
                ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       524
 SUB-EXPRESSION (sfifo_output_push || sw_cmd_req_load)
                 --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6

 LINE       530
 EXPRESSION (((!edn_enable_fo[SwCmdSts])) ? 1'b0 : ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? csrng_cmd_i.csrng_rsp_sts : csrng_cmd_sts_q))
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       530
 SUB-EXPRESSION ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? csrng_cmd_i.csrng_rsp_sts : csrng_cmd_sts_q)
                 ---------------------1---------------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T3,T6

 LINE       530
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)
                 ------------1------------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T3,T34,T10
1	1	Covered	T2,T3,T6

 LINE       538
 EXPRESSION (((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? 1'b1 : csrng_cmd_ack_q)))
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       538
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? 1'b1 : csrng_cmd_ack_q))
                 -------1-------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T3,T6

 LINE       538
 SUB-EXPRESSION ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? 1'b1 : csrng_cmd_ack_q)
                 ---------------------1---------------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T3,T6

 LINE       538
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)
                 ------------1------------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T3,T34,T10
1	1	Covered	T2,T3,T6

 LINE       567
 EXPRESSION ((send_rescmd_q & edn_enable_fo[SendReseedCmd]) ? 1'b1 : reseed_cmd_load)
             -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T11

 LINE       567
 SUB-EXPRESSION (send_rescmd_q & edn_enable_fo[SendReseedCmd])
                 ------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T116,T117,T118
1	1	Covered	T3,T10,T11

 LINE       571
 EXPRESSION (auto_req_mode_busy ? cs_cmd_req_out_q : reseed_cmd_bus)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T11

 LINE       577
 EXPRESSION (cmd_fifo_rst_fo[1] || main_sm_done_pulse)
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T3,T17,T10

 LINE       579
 SUB-EXPRESSION (sfifo_rescmd_push && sfifo_rescmd_full)
                 --------1--------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T10,T119,T87
1	0	Covered	T3,T10,T11
1	1	Covered	T94,T95,T96

 LINE       579
 SUB-EXPRESSION (sfifo_rescmd_pop && ((!sfifo_rescmd_not_empty)))
                 --------1-------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T11
1	1	Covered	T5,T90

 LINE       579
 SUB-EXPRESSION (sfifo_rescmd_full && ((!sfifo_rescmd_not_empty)))
                 --------1--------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T119,T14
1	1	Covered	T87,T99,T100

 LINE       607
 EXPRESSION ((boot_wr_cmd_genfifo & edn_enable_fo[SendGenCmd]) ? 1'b1 : ((send_gencmd_q & edn_enable_fo[SendGenCmd]) ? 1'b1 : generate_cmd_load))
             ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T34,T108,T106

 LINE       607
 SUB-EXPRESSION (boot_wr_cmd_genfifo & edn_enable_fo[SendGenCmd])
                 ---------1---------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Not Covered
1	1	Covered	T34,T108,T106

 LINE       607
 SUB-EXPRESSION ((send_gencmd_q & edn_enable_fo[SendGenCmd]) ? 1'b1 : generate_cmd_load)
                 ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T11

 LINE       607
 SUB-EXPRESSION (send_gencmd_q & edn_enable_fo[SendGenCmd])
                 ------1------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Not Covered
1	1	Covered	T3,T10,T11

 LINE       612
 EXPRESSION (boot_wr_cmd_genfifo ? boot_gen_cmd : (auto_req_mode_busy ? cs_cmd_req_out_q : generate_cmd_bus))
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T34,T108,T106

 LINE       612
 SUB-EXPRESSION (auto_req_mode_busy ? cs_cmd_req_out_q : generate_cmd_bus)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T11

 LINE       617
 EXPRESSION (send_gencmd || boot_send_gencmd)
             -----1-----    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T34,T108,T106
1	0	Covered	T3,T10,T11

 LINE       619
 EXPRESSION (cmd_fifo_rst_fo[2] || main_sm_done_pulse)
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T3,T17,T10

 LINE       621
 SUB-EXPRESSION (sfifo_gencmd_push && sfifo_gencmd_full)
                 --------1--------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T3,T34,T10
1	1	Covered	T91,T92,T93

 LINE       621
 SUB-EXPRESSION (sfifo_gencmd_pop && ((!sfifo_gencmd_not_empty)))
                 --------1-------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T34,T10
1	1	Covered	T88,T97,T98

 LINE       621
 SUB-EXPRESSION (sfifo_gencmd_full && ((!sfifo_gencmd_not_empty)))
                 --------1--------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T11
1	1	Covered	T23,T89,T91

 LINE       653
 EXPRESSION (sfifo_output_not_empty && csrng_cmd_i.csrng_req_ready)
             -----------1----------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       655
 SUB-EXPRESSION (sfifo_output_push && sfifo_output_full)
                 --------1--------    --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T6
1	1	Not Covered

 LINE       655
 SUB-EXPRESSION (sfifo_output_pop && ((!sfifo_output_not_empty)))
                 --------1-------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Not Covered

 LINE       655
 SUB-EXPRESSION (sfifo_output_full && ((!sfifo_output_not_empty)))
                 --------1--------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       697
 EXPRESSION (send_gencmd && cmd_sent)
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T34,T10
1	0	Covered	T3,T10,T11
1	1	Covered	T3,T10,T11

 LINE       712
 EXPRESSION (max_reqs_between_reseed_load || (send_rescmd && cmd_sent) || main_sm_done_pulse)
             --------------1-------------    ------------2------------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T6
0	1	0	Covered	T3,T10,T11
1	0	0	Covered	T3,T10,T11

 LINE       712
 SUB-EXPRESSION (send_rescmd && cmd_sent)
                 -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T34,T10
1	0	Covered	T3,T10,T11
1	1	Covered	T3,T10,T11

 LINE       716
 EXPRESSION (max_reqs_cnt == '0)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       719
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CmdFifoCnt])) ? '0 : ((cmd_fifo_rst_fo[3] || main_sm_done_pulse) ? '0 : (capt_gencmd_fifo_cnt ? sfifo_gencmd_depth : (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((send_gencmd || boot_send_gencmd || send_rescmd) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q)))))

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       719
 SUB-EXPRESSION 
 Number  Term
      1  (cmd_fifo_rst_fo[3] || main_sm_done_pulse) ? '0 : (capt_gencmd_fifo_cnt ? sfifo_gencmd_depth : (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((send_gencmd || boot_send_gencmd || send_rescmd) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q))))

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T3,T6

 LINE       719
 SUB-EXPRESSION (cmd_fifo_rst_fo[3] || main_sm_done_pulse)
                 ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Covered	T17,T18,T19

 LINE       719
 SUB-EXPRESSION 
 Number  Term
      1  capt_gencmd_fifo_cnt ? sfifo_gencmd_depth : (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((send_gencmd || boot_send_gencmd || send_rescmd) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q)))

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T3,T34,T10

 LINE       719
 SUB-EXPRESSION (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((send_gencmd || boot_send_gencmd || send_rescmd) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q))
                 ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T3,T10,T11

 LINE       719
 SUB-EXPRESSION ((send_gencmd || boot_send_gencmd || send_rescmd) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q)
                 ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T3,T34,T10

 LINE       719
 SUB-EXPRESSION (send_gencmd || boot_send_gencmd || send_rescmd)
                 -----1-----    --------2-------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T2,T3,T6
0	0	1	Covered	T3,T10,T11
0	1	0	Covered	T34,T108,T106
1	0	0	Covered	T3,T10,T11

 LINE       727
 EXPRESSION (cmd_fifo_cnt_q == 4'(1))
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T34,T10

 LINE       773
 EXPRESSION (((!packer_ep_rvalid[0])) && edn_i[0].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T31
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T31

 LINE       773
 EXPRESSION (((!packer_ep_rvalid[1])) && edn_i[1].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T6,T32,T33
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T32,T33

 LINE       773
 EXPRESSION (((!packer_ep_rvalid[2])) && edn_i[2].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T17,T32,T34
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T32,T34

 LINE       773
 EXPRESSION (((!packer_ep_rvalid[3])) && edn_i[3].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T35
1	0	Covered	T1,T2,T3
1	1	Covered	T33,T34,T35

 LINE       773
 EXPRESSION (((!packer_ep_rvalid[4])) && edn_i[4].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T18,T5,T36
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T5,T36

 LINE       773
 EXPRESSION (((!packer_ep_rvalid[5])) && edn_i[5].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T33,T37,T35
1	0	Covered	T1,T2,T3
1	1	Covered	T33,T37,T35

 LINE       773
 EXPRESSION (((!packer_ep_rvalid[6])) && edn_i[6].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T33,T37,T38
1	0	Covered	T1,T2,T3
1	1	Covered	T33,T37,T38

 LINE       804
 EXPRESSION (((!edn_enable_fo[CsrngFipsEn])) ? 1'b0 : ((packer_cs_push && packer_cs_wready) ? csrng_cmd_i.genbits_fips : csrng_fips_q))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       804
 SUB-EXPRESSION ((packer_cs_push && packer_cs_wready) ? csrng_cmd_i.genbits_fips : csrng_fips_q)
                 ------------------1-----------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T3,T6

 LINE       804
 SUB-EXPRESSION (packer_cs_push && packer_cs_wready)
                 -------1------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       819
 EXPRESSION (packer_cs_rvalid && packer_cs_rready)
             --------1-------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T3,T17,T32
1	1	Covered	T2,T3,T6

 LINE       821
 EXPRESSION (cs_rdata_capt_vld ? packer_cs_rdata[63:0] : cs_rdata_capt_q)
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       823
 EXPRESSION (((!edn_enable_fo[CsrngDataVld])) ? 1'b0 : (cs_rdata_capt_vld ? 1'b1 : cs_rdata_capt_vld_q))
             ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       823
 SUB-EXPRESSION (cs_rdata_capt_vld ? 1'b1 : cs_rdata_capt_vld_q)
                 --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T3,T6

 LINE       829
 EXPRESSION (cs_rdata_capt_vld && cs_rdata_capt_vld_q && (cs_rdata_capt_q == packer_cs_rdata[63:0]))
             --------1--------    ---------2---------    ---------------------3--------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T6
1	0	1	Not Covered
1	1	0	Covered	T2,T3,T32
1	1	1	Covered	T17,T18,T19

 LINE       829
 SUB-EXPRESSION (cs_rdata_capt_q == packer_cs_rdata[63:0])
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       872
 EXPRESSION (packer_arb_valid && packer_ep_wready[0] && packer_arb_gnt[0])
             --------1-------    ---------2---------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T2,T3,T6
1	1	1	Covered	T2,T3,T31

 LINE       872
 EXPRESSION (packer_arb_valid && packer_ep_wready[1] && packer_arb_gnt[1])
             --------1-------    ---------2---------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T2,T3,T6
1	1	1	Covered	T6,T32,T33

 LINE       872
 EXPRESSION (packer_arb_valid && packer_ep_wready[2] && packer_arb_gnt[2])
             --------1-------    ---------2---------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T2,T3,T6
1	1	1	Covered	T17,T32,T34

 LINE       872
 EXPRESSION (packer_arb_valid && packer_ep_wready[3] && packer_arb_gnt[3])
             --------1-------    ---------2---------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T2,T3,T6
1	1	1	Covered	T33,T34,T35

 LINE       872
 EXPRESSION (packer_arb_valid && packer_ep_wready[4] && packer_arb_gnt[4])
             --------1-------    ---------2---------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T2,T3,T6
1	1	1	Covered	T18,T5,T36