Unified Coverage Report :: Module :: edn_core

Module : edn_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.13	100.00	85.39			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core	95.13	100.00	85.39			100.00

---

Module Instance : tb.dut.u_edn_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.13	100.00	85.39			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.18	99.92	89.15	70.79	89.24	99.08	98.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
gen_ep_blk[0].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[1].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[2].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[3].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[4].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
gen_ep_blk[5].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
gen_ep_blk[6].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
u_edn_main_sm	97.55	100.00	100.00		90.00	97.73	100.00
u_intr_hw_edn_cmd_req_done	100.00	100.00	100.00			100.00	100.00
u_intr_hw_edn_fatal_err	100.00	100.00	100.00			100.00	100.00
u_prim_arbiter_ppc_packer_arb	95.16	95.00	92.31			100.00	93.33
u_prim_count_max_reqs_cntr	70.79			70.79
u_prim_edge_detector_recov_alert	88.89	100.00	66.67			100.00
u_prim_fifo_sync_gencmd	97.12	100.00	88.46			100.00	100.00
u_prim_fifo_sync_output	91.06	100.00	69.23			95.00	100.00
u_prim_fifo_sync_rescmd	97.12	100.00	88.46			100.00	100.00
u_prim_mubi4_sync_auto_req_mode	100.00	100.00					100.00
u_prim_mubi4_sync_boot_req_mode	100.00	100.00					100.00
u_prim_mubi4_sync_cmd_fifo_rst	100.00	100.00					100.00
u_prim_mubi4_sync_edn_enable	100.00	100.00					100.00
u_prim_packer_fifo_cs	95.24	100.00	95.24			85.71	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_core

	Line No.	Total	Covered	Percent
TOTAL		240	240	100.00
ALWAYS	224	31	31	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	329	1	1	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	360	1	1	100.00
CONT_ASSIGN	361	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	448	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	565	1	1	100.00
CONT_ASSIGN	567	1	1	100.00
CONT_ASSIGN	571	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	607	1	1	100.00
CONT_ASSIGN	612	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	619	1	1	100.00
CONT_ASSIGN	621	1	1	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	648	1	1	100.00
CONT_ASSIGN	650	1	1	100.00
CONT_ASSIGN	651	1	1	100.00
CONT_ASSIGN	652	1	1	100.00
CONT_ASSIGN	653	1	1	100.00
CONT_ASSIGN	655	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	716	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	727	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	733	1	1	100.00
CONT_ASSIGN	734	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	773	1	1	100.00
CONT_ASSIGN	773	1	1	100.00
CONT_ASSIGN	773	1	1	100.00
CONT_ASSIGN	773	1	1	100.00
CONT_ASSIGN	773	1	1	100.00
CONT_ASSIGN	773	1	1	100.00
CONT_ASSIGN	773	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	798	1	1	100.00
CONT_ASSIGN	799	1	1	100.00
CONT_ASSIGN	800	1	1	100.00
CONT_ASSIGN	801	1	1	100.00
CONT_ASSIGN	802	1	1	100.00
CONT_ASSIGN	804	1	1	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	821	1	1	100.00
CONT_ASSIGN	823	1	1	100.00
CONT_ASSIGN	829	1	1	100.00
CONT_ASSIGN	847	1	1	100.00
CONT_ASSIGN	848	1	1	100.00
CONT_ASSIGN	872	1	1	100.00
CONT_ASSIGN	872	1	1	100.00
CONT_ASSIGN	872	1	1	100.00
CONT_ASSIGN	872	1	1	100.00
CONT_ASSIGN	872	1	1	100.00
CONT_ASSIGN	872	1	1	100.00
CONT_ASSIGN	872	1	1	100.00
CONT_ASSIGN	873	1	1	100.00
CONT_ASSIGN	873	1	1	100.00
CONT_ASSIGN	873	1	1	100.00
CONT_ASSIGN	873	1	1	100.00
CONT_ASSIGN	873	1	1	100.00
CONT_ASSIGN	873	1	1	100.00
CONT_ASSIGN	873	1	1	100.00
CONT_ASSIGN	876	1	1	100.00
CONT_ASSIGN	876	1	1	100.00
CONT_ASSIGN	876	1	1	100.00
CONT_ASSIGN	876	1	1	100.00
CONT_ASSIGN	876	1	1	100.00
CONT_ASSIGN	876	1	1	100.00
CONT_ASSIGN	876	1	1	100.00
CONT_ASSIGN	879	1	1	100.00
CONT_ASSIGN	879	1	1	100.00
CONT_ASSIGN	879	1	1	100.00
CONT_ASSIGN	879	1	1	100.00
CONT_ASSIGN	879	1	1	100.00
CONT_ASSIGN	879	1	1	100.00
CONT_ASSIGN	879	1	1	100.00
CONT_ASSIGN	882	1	1	100.00
CONT_ASSIGN	882	1	1	100.00
CONT_ASSIGN	882	1	1	100.00
CONT_ASSIGN	882	1	1	100.00
CONT_ASSIGN	882	1	1	100.00
CONT_ASSIGN	882	1	1	100.00
CONT_ASSIGN	882	1	1	100.00
CONT_ASSIGN	883	1	1	100.00
CONT_ASSIGN	883	1	1	100.00
CONT_ASSIGN	883	1	1	100.00
CONT_ASSIGN	883	1	1	100.00
CONT_ASSIGN	883	1	1	100.00
CONT_ASSIGN	883	1	1	100.00
CONT_ASSIGN	883	1	1	100.00
CONT_ASSIGN	903	1	1	100.00
CONT_ASSIGN	909	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
253	1	1
254	1	1
255	1	1
294	1	1
299	1	1
304	1	1
311	1	1
313	1	1
315	1	1
317	1	1
319	1	1
321	1	1
324	1	1
329	1	1
334	1	1
343	1	1
346	1	1
349	1	1
352	1	1
355	1	1
358	1	1
360	1	1
361	1	1
366	1	1
369	1	1
372	1	1
377	31	31
382	1	1
385	1	1
389	1	1
398	1	1
399	1	1
400	1	1
401	1	1
404	21	21
419	1	1
420	1	1
421	1	1
422	1	1
425	3	3
439	1	1
446	1	1
447	1	1
448	1	1
449	1	1
450	1	1
465	1	1
466	1	1
468	1	1
469	1	1
471	1	1
472	1	1
474	1	1
475	1	1
477	1	1
484	1	1
488	1	1
494	1	1
503	1	1
504	1	1
508	1	1
518	1	1
519	1	1
524	1	1
529	1	1
530	1	1
537	1	1
538	1	1
565	1	1
567	1	1
571	1	1
575	1	1
577	1	1
579	1	1
605	1	1
607	1	1
612	1	1
617	1	1
619	1	1
621	1	1
647	1	1
648	1	1
650	1	1
651	1	1
652	1	1
653	1	1
655	1	1
712	1	1
716	1	1
719	1	1
727	1	1
731	1	1
732	1	1
733	1	1
734	1	1
737	1	1
773	7	7
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
804	1	1
819	1	1
821	1	1
823	1	1
829	1	1
847	1	1
848	1	1
872	7	7
873	7	7
876	7	7
879	7	7
882	7	7
883	7	7
903	1	1
909	1	1

---

Cond Coverage for Module : edn_core

	Total	Covered	Percent
Conditions	527	450	85.39
Logical	527	450	85.39
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
294-872	85.87
872-909	81.67

---

Branch Coverage for Module : edn_core

	Line No.	Total	Covered	Percent
Branches		77	77	100.00
TERNARY	477	5	5	100.00
TERNARY	484	2	2	100.00
TERNARY	488	4	4	100.00
TERNARY	494	3	3	100.00
TERNARY	508	6	6	100.00
TERNARY	519	3	3	100.00
TERNARY	530	3	3	100.00
TERNARY	538	4	4	100.00
TERNARY	567	2	2	100.00
TERNARY	571	2	2	100.00
TERNARY	607	3	3	100.00
TERNARY	612	3	3	100.00
TERNARY	719	6	6	100.00
TERNARY	804	3	3	100.00
TERNARY	821	2	2	100.00
TERNARY	823	3	3	100.00
TERNARY	876	3	3	100.00
TERNARY	876	3	3	100.00
TERNARY	876	3	3	100.00
TERNARY	876	3	3	100.00
TERNARY	876	3	3	100.00
TERNARY	876	3	3	100.00
TERNARY	876	3	3	100.00
IF	224	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	477	((!edn_enable_fo[CsrngCmdReq])) ? 
-2-:	477	(boot_wr_cmd_reg) ? 
-3-:	477	(sw_cmd_req_load) ? 
-4-:	477	(boot_wr_cmd_uni) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T34,T108,T106
0	0	1	-	Covered	T2,T3,T6
0	0	0	1	Covered	T34,T39,T115
0	0	0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	484	((!edn_enable_fo[CsrngCmdReqValid])) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	488	((!edn_enable_fo[CsrngCmdReqOut])) ? 
-2-:	488	(send_rescmd) ? 
-3-:	488	((send_gencmd || boot_send_gencmd)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T10,T11
0	0	1	Covered	T3,T34,T10
0	0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	494	((!edn_enable_fo[CsrngCmdReqValidOut])) ? 
-2-:	494	(((send_rescmd || send_gencmd) || (boot_send_gencmd && cmd_sent))) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T34,T10
0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	508	((!edn_enable_fo[SwCmdSts])) ? 
-2-:	508	((!sw_cmd_valid)) ? 
-3-:	508	(sw_cmd_req_load) ? 
-4-:	508	(accept_sw_cmds_pulse) ? 
-5-:	508	(csrng_cmd_i.csrng_rsp_ack) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T3,T34,T10
0	0	1	-	-	Covered	T2,T3,T6
0	0	0	1	-	Covered	T2,T3,T6
0	0	0	0	1	Covered	T2,T3,T6
0	0	0	0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	519	((!edn_enable_fo[SwCmdSts])) ? 
-2-:	519	((!sw_cmd_valid)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T34,T10
0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	530	((!edn_enable_fo[SwCmdSts])) ? 
-2-:	530	((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	538	((!edn_enable_fo[SwCmdSts])) ? 
-2-:	538	(sw_cmd_req_load) ? 
-3-:	538	((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T6
0	0	1	Covered	T2,T3,T6
0	0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	567	((send_rescmd_q & edn_enable_fo[SendReseedCmd])) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	571	(auto_req_mode_busy) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	607	((boot_wr_cmd_genfifo & edn_enable_fo[SendGenCmd])) ? 
-2-:	607	((send_gencmd_q & edn_enable_fo[SendGenCmd])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T34,T108,T106
0	1	Covered	T3,T10,T11
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	612	(boot_wr_cmd_genfifo) ? 
-2-:	612	(auto_req_mode_busy) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T34,T108,T106
0	1	Covered	T3,T10,T11
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	719	((!edn_enable_fo[CmdFifoCnt])) ? 
-2-:	719	((cmd_fifo_rst_fo[3] || main_sm_done_pulse)) ? 
-3-:	719	(capt_gencmd_fifo_cnt) ? 
-4-:	719	(capt_rescmd_fifo_cnt) ? 
-5-:	719	(((send_gencmd || boot_send_gencmd) || send_rescmd)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T2,T3,T6
0	0	1	-	-	Covered	T3,T34,T10
0	0	0	1	-	Covered	T3,T10,T11
0	0	0	0	1	Covered	T3,T34,T10
0	0	0	0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	804	((!edn_enable_fo[CsrngFipsEn])) ? 
-2-:	804	((packer_cs_push && packer_cs_wready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	821	(cs_rdata_capt_vld) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	823	((!edn_enable_fo[CsrngDataVld])) ? 
-2-:	823	(cs_rdata_capt_vld) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	876	(packer_ep_clr[0]) ? 
-2-:	876	((packer_ep_push[0] && packer_ep_wready[0])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T6
0	1	Covered	T2,T3,T31
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	876	(packer_ep_clr[1]) ? 
-2-:	876	((packer_ep_push[1] && packer_ep_wready[1])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T6
0	1	Covered	T6,T32,T33
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	876	(packer_ep_clr[2]) ? 
-2-:	876	((packer_ep_push[2] && packer_ep_wready[2])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T6
0	1	Covered	T17,T32,T34
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	876	(packer_ep_clr[3]) ? 
-2-:	876	((packer_ep_push[3] && packer_ep_wready[3])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T6
0	1	Covered	T33,T34,T35
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	876	(packer_ep_clr[4]) ? 
-2-:	876	((packer_ep_push[4] && packer_ep_wready[4])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T6
0	1	Covered	T18,T5,T36
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	876	(packer_ep_clr[5]) ? 
-2-:	876	((packer_ep_push[5] && packer_ep_wready[5])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T6
0	1	Covered	T33,T37,T35
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	876	(packer_ep_clr[6]) ? 
-2-:	876	((packer_ep_push[6] && packer_ep_wready[6])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T6
0	1	Covered	T33,T37,T38
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3