Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	148	1			T1	1		T29	1		T37	1
auto_req_mode	135	1			T9	1		T10	1		T14	1
sw_mode	3020	1			T3	1		T50	1		T4	64

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

305

1

T1

1

T29

1

T37

1

single

93

1

T9

1

T10

1

T42

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1415	1			T1	1		T3	1		T50	1
auto[2]	107	1			T168	1		T295	1		T296	66
auto[3]	52	1			T38	1		T297	1		T269	1
auto[4]	419	1			T167	1		T91	32		T175	1
auto[5]	87	1			T30	1		T35	1		T36	1
auto[6]	20	1			T32	1		T12	1		T43	1
auto[7]	1203	1			T29	1		T4	64		T9	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	90	1			T1	1		T37	1		T73	1
auto[1]	auto_req_mode	83	1			T10	1		T42	1		T40	1
auto[1]	sw_mode	1242	1			T3	1		T50	1		T5	48
auto[2]	boot_req_mode	2	1			T168	1		T298	1		-	-
auto[2]	auto_req_mode	3	1			T299	1		T300	1		T301	1
auto[2]	sw_mode	102	1			T295	1		T296	66		T302	1
auto[3]	boot_req_mode	3	1			T303	1		T304	1		T305	1
auto[3]	auto_req_mode	3	1			T38	1		T297	1		T306	1
auto[3]	sw_mode	46	1			T269	1		T307	1		T308	43
auto[4]	boot_req_mode	3	1			T176	1		T309	1		T310	1
auto[4]	auto_req_mode	4	1			T311	1		T312	1		T313	1
auto[4]	sw_mode	412	1			T167	1		T91	32		T175	1
auto[5]	boot_req_mode	4	1			T30	1		T36	1		T314	1
auto[5]	auto_req_mode	2	1			T39	1		T315	1		-	-
auto[5]	sw_mode	81	1			T35	1		T316	1		T317	4
auto[6]	boot_req_mode	6	1			T43	1		T318	1		T319	1
auto[6]	auto_req_mode	6	1			T32	1		T12	1		T320	1
auto[6]	sw_mode	8	1			T321	1		T322	1		T323	1
auto[7]	boot_req_mode	40	1			T29	1		T41	1		T45	1
auto[7]	auto_req_mode	34	1			T9	1		T14	1		T11	1
auto[7]	sw_mode	1129	1			T4	64		T31	1		T170	2