Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	686512	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5770394

1

T1

27

T2

10

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1708980	1			T1	65		T2	43		T3	56
values[0x0]	2201375	1			T1	19		T2	5		T3	3
values[0x1]	2546551	1			T1	10		T2	7		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	340080	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6116826

1

T1

46

T2

15

T3

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23903	1			T25	5		T47	6		T221	1
valid_sources[0x01]	27633	1			T3	1		T25	3		T189	3
valid_sources[0x02]	25362	1			T1	2		T25	5		T192	1
valid_sources[0x03]	26273	1			T25	1		T47	1		T193	3
valid_sources[0x04]	25930	1			T1	2		T25	1		T47	3
valid_sources[0x05]	23823	1			T190	71		T221	1		T211	6
valid_sources[0x06]	26414	1			T1	2		T3	1		T25	1
valid_sources[0x07]	25365	1			T25	4		T28	6		T194	1
valid_sources[0x08]	25880	1			T3	3		T194	1		T211	29
valid_sources[0x09]	23999	1			T3	3		T25	2		T28	11
valid_sources[0x0a]	25795	1			T3	1		T25	1		T26	1
valid_sources[0x0b]	25375	1			T25	2		T189	5		T191	1
valid_sources[0x0c]	25204	1			T25	1		T28	1		T47	5
valid_sources[0x0d]	24863	1			T25	1		T48	6		T221	1
valid_sources[0x0e]	22971	1			T1	2		T25	1		T193	3
valid_sources[0x0f]	23949	1			T1	1		T25	3		T192	1
valid_sources[0x10]	24909	1			T27	3		T25	2		T189	1
valid_sources[0x11]	26846	1			T25	2		T28	2		T47	1
valid_sources[0x12]	23620	1			T194	4		T192	2		T193	2
valid_sources[0x13]	23424	1			T25	2		T221	1		T189	1
valid_sources[0x14]	24962	1			T47	4		T189	1		T211	10
valid_sources[0x15]	26049	1			T27	1		T25	2		T28	1
valid_sources[0x16]	24813	1			T25	3		T221	1		T192	1
valid_sources[0x17]	25080	1			T25	2		T190	26		T192	4
valid_sources[0x18]	25511	1			T25	3		T26	41		T47	1
valid_sources[0x19]	26693	1			T25	1		T193	1		T218	3
valid_sources[0x1a]	25516	1			T25	6		T26	14		T194	2
valid_sources[0x1b]	25001	1			T25	6		T26	52		T47	2
valid_sources[0x1c]	24988	1			T27	4		T25	1		T221	2
valid_sources[0x1d]	25998	1			T25	1		T190	36		T211	4
valid_sources[0x1e]	26654	1			T27	1		T25	3		T26	61
valid_sources[0x1f]	23133	1			T25	2		T47	6		T194	2
valid_sources[0x20]	24543	1			T3	1		T25	6		T190	10
valid_sources[0x21]	23961	1			T25	5		T189	2		T260	1
valid_sources[0x22]	24212	1			T25	2		T192	2		T218	1
valid_sources[0x23]	25618	1			T47	3		T48	1		T194	1
valid_sources[0x24]	25514	1			T1	2		T25	1		T26	2
valid_sources[0x25]	25481	1			T27	1		T25	1		T189	2
valid_sources[0x26]	24384	1			T1	4		T3	1		T25	2
valid_sources[0x27]	25165	1			T194	4		T221	1		T192	1
valid_sources[0x28]	27108	1			T25	2		T192	3		T195	4
valid_sources[0x29]	28516	1			T25	2		T189	4		T192	1
valid_sources[0x2a]	23334	1			T25	6		T192	1		T207	1
valid_sources[0x2b]	23442	1			T192	2		T212	1		T218	3
valid_sources[0x2c]	23607	1			T25	1		T221	2		T192	2
valid_sources[0x2d]	24956	1			T25	2		T28	3		T47	2
valid_sources[0x2e]	25787	1			T25	2		T192	4		T218	2
valid_sources[0x2f]	25512	1			T25	3		T28	4		T47	2
valid_sources[0x30]	25340	1			T25	3		T47	8		T192	5
valid_sources[0x31]	24468	1			T25	6		T47	5		T189	2
valid_sources[0x32]	24579	1			T25	3		T194	3		T191	2
valid_sources[0x33]	24482	1			T25	7		T189	3		T191	1
valid_sources[0x34]	23083	1			T221	1		T192	4		T193	5
valid_sources[0x35]	27999	1			T1	1		T3	1		T25	1
valid_sources[0x36]	23821	1			T194	3		T188	1		T211	19
valid_sources[0x37]	24575	1			T25	2		T189	3		T192	1
valid_sources[0x38]	26014	1			T25	4		T47	8		T193	3
valid_sources[0x39]	24346	1			T1	1		T3	1		T26	15
valid_sources[0x3a]	25109	1			T211	13		T192	1		T212	1
valid_sources[0x3b]	25186	1			T25	1		T47	3		T221	1
valid_sources[0x3c]	24916	1			T25	6		T221	1		T211	6
valid_sources[0x3d]	23890	1			T192	1		T193	3		T213	2
valid_sources[0x3e]	26425	1			T194	2		T221	3		T192	2
valid_sources[0x3f]	25110	1			T25	1		T26	5		T47	11
valid_sources[0x40]	24897	1			T25	3		T26	10		T191	1
valid_sources[0x41]	26181	1			T25	1		T221	2		T211	4
valid_sources[0x42]	26676	1			T3	1		T25	2		T47	1
valid_sources[0x43]	25803	1			T221	1		T192	1		T193	3
valid_sources[0x44]	23368	1			T1	1		T47	3		T194	1
valid_sources[0x45]	24231	1			T25	1		T26	10		T48	1
valid_sources[0x46]	23946	1			T1	4		T3	1		T25	1
valid_sources[0x47]	24334	1			T25	2		T189	4		T192	2
valid_sources[0x48]	25687	1			T3	2		T25	3		T26	15
valid_sources[0x49]	24902	1			T3	1		T25	1		T194	2
valid_sources[0x4a]	24798	1			T25	3		T211	12		T192	2
valid_sources[0x4b]	24843	1			T1	1		T25	1		T48	2
valid_sources[0x4c]	25237	1			T3	1		T25	3		T221	3
valid_sources[0x4d]	24877	1			T25	4		T189	3		T191	1
valid_sources[0x4e]	23457	1			T25	1		T28	2		T47	4
valid_sources[0x4f]	26065	1			T3	1		T25	1		T221	1
valid_sources[0x50]	25267	1			T2	16		T47	6		T194	1
valid_sources[0x51]	24960	1			T26	62		T28	1		T221	3
valid_sources[0x52]	28916	1			T25	1		T194	4		T221	1
valid_sources[0x53]	23424	1			T1	1		T25	5		T26	15
valid_sources[0x54]	25112	1			T27	1		T25	3		T221	4
valid_sources[0x55]	23963	1			T25	2		T28	6		T49	6
valid_sources[0x56]	25389	1			T25	5		T47	2		T194	1
valid_sources[0x57]	25417	1			T3	1		T25	2		T47	9
valid_sources[0x58]	24419	1			T25	2		T189	3		T211	28
valid_sources[0x59]	25423	1			T25	3		T26	39		T189	7
valid_sources[0x5a]	24663	1			T27	3		T25	2		T47	2
valid_sources[0x5b]	24964	1			T25	7		T192	3		T193	3
valid_sources[0x5c]	23553	1			T3	3		T25	2		T47	1
valid_sources[0x5d]	24921	1			T3	1		T25	2		T26	36
valid_sources[0x5e]	24195	1			T25	1		T28	1		T221	1
valid_sources[0x5f]	26896	1			T28	1		T189	1		T211	9
valid_sources[0x60]	23614	1			T25	1		T189	3		T211	2
valid_sources[0x61]	24204	1			T1	4		T189	5		T207	1
valid_sources[0x62]	25049	1			T25	1		T47	6		T221	1
valid_sources[0x63]	25691	1			T3	1		T25	3		T194	2
valid_sources[0x64]	22957	1			T25	3		T194	2		T192	1
valid_sources[0x65]	26752	1			T25	3		T191	2		T193	8
valid_sources[0x66]	24302	1			T25	3		T189	12		T191	1
valid_sources[0x67]	25645	1			T25	3		T189	1		T192	2
valid_sources[0x68]	23818	1			T1	1		T25	3		T28	9
valid_sources[0x69]	24368	1			T191	1		T193	1		T223	27
valid_sources[0x6a]	25550	1			T3	4		T25	3		T194	3
valid_sources[0x6b]	26587	1			T27	7		T211	17		T192	1
valid_sources[0x6c]	26443	1			T47	4		T221	1		T189	2
valid_sources[0x6d]	24688	1			T3	1		T47	7		T190	27
valid_sources[0x6e]	26317	1			T3	1		T25	2		T26	20
valid_sources[0x6f]	25729	1			T1	1		T3	2		T25	2
valid_sources[0x70]	25110	1			T1	1		T3	1		T25	1
valid_sources[0x71]	26699	1			T1	1		T25	2		T47	3
valid_sources[0x72]	24414	1			T194	1		T192	2		T204	1
valid_sources[0x73]	25855	1			T3	1		T25	4		T221	1
valid_sources[0x74]	26245	1			T2	1		T25	3		T194	1
valid_sources[0x75]	23838	1			T221	1		T189	5		T192	3
valid_sources[0x76]	25027	1			T1	3		T3	1		T25	6
valid_sources[0x77]	24423	1			T25	1		T47	1		T194	3
valid_sources[0x78]	26426	1			T25	1		T189	2		T211	28
valid_sources[0x79]	25575	1			T25	2		T190	42		T221	2
valid_sources[0x7a]	25524	1			T47	1		T194	1		T190	14
valid_sources[0x7b]	24342	1			T25	2		T28	2		T189	2
valid_sources[0x7c]	24812	1			T25	1		T211	12		T192	4
valid_sources[0x7d]	24762	1			T1	3		T25	1		T47	1
valid_sources[0x7e]	24057	1			T47	7		T194	1		T189	3
valid_sources[0x7f]	24897	1			T25	2		T211	1		T260	1
valid_sources[0x80]	26247	1			T25	1		T47	1		T189	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1452583

1

T1

2

T2

3

T3

5

values[0x0]

all_enables

biggest_size

2158294

1

T1

17

T2

2

T3

1

values[0x1]

all_enables

biggest_size

2159517

1

T1

8

T2

5

T3

2