Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	100.00	1	100	1	64	64

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	0	52	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	0	52	100.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
non_zero_bins[0]	2612	1		T29	1	T4	38	T5	30
non_zero_bins[1]	1853	1		T1	1	T29	1	T4	22
zero	8525	1		T1	3	T2	2	T3	3

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	506	1		T29	1	T4	12	T5	10
uni	3690	1		T1	1	T3	1	T29	2
gen	3836	1		T1	1	T2	1	T3	1
res	810	1		T4	13	T5	8	T51	1
ins	4148	1		T1	2	T2	1	T3	1

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8812

mubi_true

4178

T29

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

6364

pass

6626

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	0	52	100.00
Automatically Generated Cross Bins	52	0	52	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	non_zero_bins[0]	fail	mubi_false	49	1		T4	1	T5	1	T51	1
upd	non_zero_bins[0]	fail	mubi_true	64	1		T29	1	T5	2	T31	1
upd	non_zero_bins[0]	pass	mubi_false	53	1		T4	2	T51	1	T168	1
upd	non_zero_bins[0]	pass	mubi_true	66	1		T5	2	T51	1	T91	1
upd	non_zero_bins[1]	fail	mubi_false	47	1		T4	1	T5	1	T51	1
upd	non_zero_bins[1]	fail	mubi_true	46	1		T4	2	T30	1	T92	1
upd	non_zero_bins[1]	pass	mubi_false	46	1		T5	2	T89	1	T92	2
upd	non_zero_bins[1]	pass	mubi_true	41	1		T4	1	T89	2	T91	2
upd	zero	fail	mubi_false	18	1		T4	2	T92	1	T261	1
upd	zero	fail	mubi_true	21	1		T4	2	T35	1	T92	1
upd	zero	pass	mubi_false	25	1		T5	1	T262	1	T263	1
upd	zero	pass	mubi_true	30	1		T4	1	T5	1	T176	1
uni	zero	fail	mubi_false	1349	1		T1	1	T29	2	T50	1
uni	zero	fail	mubi_true	501	1		T4	11	T5	7	T93	1
uni	zero	pass	mubi_false	1322	1		T3	1	T4	23	T5	19
uni	zero	pass	mubi_true	518	1		T4	11	T5	4	T89	14
gen	non_zero_bins[0]	fail	mubi_false	230	1		T4	4	T5	3	T51	1
gen	non_zero_bins[0]	fail	mubi_true	219	1		T4	2	T5	1	T9	1
gen	non_zero_bins[0]	pass	mubi_false	232	1		T4	5	T5	4	T51	2
gen	non_zero_bins[0]	pass	mubi_true	240	1		T4	4	T5	2	T10	2
gen	non_zero_bins[1]	fail	mubi_false	163	1		T4	1	T5	2	T89	4
gen	non_zero_bins[1]	fail	mubi_true	151	1		T5	3	T89	2	T91	2
gen	non_zero_bins[1]	pass	mubi_false	162	1		T29	1	T4	2	T5	2
gen	non_zero_bins[1]	pass	mubi_true	164	1		T4	2	T51	1	T89	1
gen	zero	fail	mubi_false	902	1		T2	1	T3	1	T4	18
gen	zero	fail	mubi_true	203	1		T29	1	T4	1	T5	2
gen	zero	pass	mubi_false	950	1		T50	1	T4	23	T5	16
gen	zero	pass	mubi_true	220	1		T1	1	T4	1	T5	1
res	non_zero_bins[0]	fail	mubi_false	82	1		T4	2	T89	2	T264	1
res	non_zero_bins[0]	fail	mubi_true	108	1		T4	1	T42	1	T89	3
res	non_zero_bins[0]	pass	mubi_false	98	1		T4	3	T5	2	T89	1
res	non_zero_bins[0]	pass	mubi_true	101	1		T4	2	T42	1	T91	2
res	non_zero_bins[1]	fail	mubi_false	57	1		T5	3	T265	1	T266	1
res	non_zero_bins[1]	fail	mubi_true	61	1		T5	1	T9	2	T10	1
res	non_zero_bins[1]	pass	mubi_false	70	1		T4	1	T92	2	T263	1
res	non_zero_bins[1]	pass	mubi_true	67	1		T4	1	T5	1	T51	1
res	zero	fail	mubi_false	48	1		T4	1	T5	1	T32	2
res	zero	fail	mubi_true	39	1		T4	1	T14	2	T89	2
res	zero	pass	mubi_false	39	1		T89	1	T261	2	T265	1
res	zero	pass	mubi_true	40	1		T4	1	T92	2	T267	2
ins	non_zero_bins[0]	fail	mubi_false	252	1		T4	2	T5	7	T51	2
ins	non_zero_bins[0]	fail	mubi_true	263	1		T4	4	T51	1	T9	1
ins	non_zero_bins[0]	pass	mubi_false	285	1		T4	2	T5	2	T51	3
ins	non_zero_bins[0]	pass	mubi_true	270	1		T4	4	T5	4	T42	1
ins	non_zero_bins[1]	fail	mubi_false	200	1		T4	4	T5	1	T35	1
ins	non_zero_bins[1]	fail	mubi_true	184	1		T4	3	T5	2	T89	4
ins	non_zero_bins[1]	pass	mubi_false	212	1		T1	1	T4	2	T5	3
ins	non_zero_bins[1]	pass	mubi_true	182	1		T4	2	T5	5	T89	5
ins	zero	fail	mubi_false	927	1		T29	1	T50	1	T4	20
ins	zero	fail	mubi_true	180	1		T29	1	T4	2	T15	1
ins	zero	pass	mubi_false	994	1		T2	1	T3	1	T4	21
ins	zero	pass	mubi_true	199	1		T1	1	T4	1	T5	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded