Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	228567620	10549854	0	0
boot_gen_cmd_rd_A	228567620	67502	0	0
boot_ins_cmd_rd_A	228567620	77943	0	0
ctrl_rd_A	228567620	66743	0	0
err_code_test_rd_A	228567620	65529	0	0
intr_enable_rd_A	228567620	75553	0	0
max_num_reqs_between_reseeds_rd_A	228567620	78523	0	0
regwen_rd_A	228567620	77440	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228567620	10549854	0	0
T25	9651	9	0	0
T26	15955	6	0	0
T28	1755	41	0	0
T47	4005	6	0	0
T188	1808	193	0	0
T189	2369	98	0	0
T190	8054	11	0	0
T191	1020	5	0	0
T192	7471	658	0	0
T193	4134	992	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228567620	67502	0	0
T28	1755	1	0	0
T193	4134	0	0	0
T194	2246	36	0	0
T195	2210	44	0	0
T196	0	17	0	0
T197	0	7	0	0
T198	0	38	0	0
T199	0	19	0	0
T200	0	10	0	0
T201	0	21	0	0
T202	0	15	0	0
T203	847	0	0	0
T204	1222	0	0	0
T205	1099	0	0	0
T206	1077	0	0	0
T207	1295	0	0	0
T208	1384	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228567620	77943	0	0
T28	1755	5	0	0
T191	1020	1	0	0
T193	4134	0	0	0
T194	2246	46	0	0
T195	2210	46	0	0
T196	0	13	0	0
T197	0	22	0	0
T198	0	31	0	0
T199	0	7	0	0
T200	0	1	0	0
T202	0	22	0	0
T203	847	0	0	0
T204	1222	0	0	0
T205	1099	0	0	0
T206	1077	0	0	0
T207	1295	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228567620	66743	0	0
T191	1020	4	0	0
T193	4134	0	0	0
T194	2246	58	0	0
T195	2210	12	0	0
T196	0	8	0	0
T197	0	17	0	0
T198	0	28	0	0
T199	0	36	0	0
T200	0	6	0	0
T201	0	8	0	0
T203	847	0	0	0
T204	1222	0	0	0
T205	1099	0	0	0
T206	1077	0	0	0
T207	1295	0	0	0
T208	1384	0	0	0
T209	0	2	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228567620	65529	0	0
T28	1755	8	0	0
T191	1020	3	0	0
T193	4134	0	0	0
T194	2246	47	0	0
T195	2210	7	0	0
T196	0	7	0	0
T197	0	36	0	0
T198	0	35	0	0
T199	0	27	0	0
T200	0	4	0	0
T203	847	0	0	0
T204	1222	0	0	0
T205	1099	0	0	0
T206	1077	0	0	0
T207	1295	0	0	0
T209	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228567620	75553	0	0
T27	1334	12	0	0
T28	1755	17	0	0
T191	1020	9	0	0
T194	2246	28	0	0
T195	2210	44	0	0
T203	847	0	0	0
T204	1222	18	0	0
T205	0	16	0	0
T210	1372	19	0	0
T211	13177	263	0	0
T212	931	17	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228567620	78523	0	0
T28	1755	17	0	0
T191	1020	1	0	0
T194	2246	47	0	0
T195	2210	11	0	0
T196	0	18	0	0
T197	0	27	0	0
T203	847	0	0	0
T204	1222	0	0	0
T205	1099	0	0	0
T206	1077	0	0	0
T207	1295	0	0	0
T211	13177	196	0	0
T213	0	38	0	0
T214	0	5	0	0
T215	0	9	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228567620	77440	0	0
T28	1755	2	0	0
T193	4134	0	0	0
T194	2246	30	0	0
T195	2210	38	0	0
T196	0	25	0	0
T197	0	34	0	0
T198	0	30	0	0
T203	847	0	0	0
T204	1222	0	0	0
T205	1099	0	0	0
T206	1077	0	0	0
T207	1295	0	0	0
T211	13177	202	0	0
T213	0	61	0	0
T214	0	12	0	0
T215	0	4	0	0