Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.19	100.00	100.00		88.33	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.19	100.00	100.00		88.33	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.19	100.00	100.00		88.33	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.21	100.00	100.00		88.33	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.13	100.00	85.39			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		109	109	100.00
ALWAYS	60	3	3	100.00
CONT_ASSIGN	62	1	1	100.00
ALWAYS	65	105	105	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	3	3
62	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
77	1	1
78	1	1
79	1	1
81	1	1
82	1	1
83	1	1
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
			MISSING_ELSE
95	1	1
96	1	1
99	1	1
100	1	1
103	1	1
104	1	1
			MISSING_ELSE
108	1	1
109	1	1
112	1	1
113	1	1
114	1	1
			==> MISSING_ELSE
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
127	1	1
128	1	1
			MISSING_ELSE
132	1	1
133	1	1
136	1	1
137	1	1
			MISSING_ELSE
142	1	1
143	1	1
144	1	1
			MISSING_ELSE
148	1	1
149	1	1
150	1	1
			MISSING_ELSE
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
163	1	1
165	1	1
166	1	1
168	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
180	1	1
181	1	1
			MISSING_ELSE
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
			MISSING_ELSE
197	1	1
200	1	1
208	1	1
209	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T37,T15,T58
1	1	Covered	T1,T29,T37

 LINE       83
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T6,T42
1	1	Covered	T9,T10,T6

 LINE       222
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, BootLoadUni, BootUniAckWait, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T37,T15

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	21	21	100.00	(Not included in score)
Transitions	60	53	88.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	181	Covered	T9,T10,T14
AutoCaptGenCnt	168	Covered	T9,T10,T14
AutoCaptReseedCnt	166	Covered	T9,T10,T14
AutoDispatch	150	Covered	T9,T10,T14
AutoFirstAckWait	144	Covered	T9,T10,T14
AutoLoadIns	86	Covered	T9,T10,T6
AutoSendGenCmd	175	Covered	T9,T10,T14
AutoSendReseedCmd	187	Covered	T9,T10,T14
BootCaptGenCnt	104	Covered	T1,T29,T37
BootDone	124	Covered	T1,T29,T37
BootGenAckWait	114	Covered	T1,T29,T37
BootInsAckWait	100	Covered	T1,T29,T37
BootLoadGen	96	Covered	T1,T29,T37
BootLoadIns	82	Covered	T1,T29,T37
BootLoadUni	128	Covered	T1,T29,T73
BootPulse	119	Covered	T1,T29,T37
BootSendGenCmd	109	Covered	T1,T29,T37
BootUniAckWait	133	Covered	T1,T29,T73
Error	209	Covered	T2,T24,T15
Idle	137	Covered	T1,T2,T3
SWPortMode	91	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	156	Covered	T9,T10,T14
AutoAckWait->Error	209	Not Covered
AutoAckWait->Idle	231	Covered	T10,T42,T40
AutoCaptGenCnt->AutoSendGenCmd	175	Covered	T9,T10,T14
AutoCaptGenCnt->Error	209	Covered	T7,T100,T101
AutoCaptGenCnt->Idle	231	Covered	T102,T103,T104
AutoCaptReseedCnt->AutoSendReseedCmd	187	Covered	T9,T10,T14
AutoCaptReseedCnt->Error	209	Not Covered
AutoCaptReseedCnt->Idle	231	Covered	T105,T106,T107
AutoDispatch->AutoCaptGenCnt	168	Covered	T9,T10,T14
AutoDispatch->AutoCaptReseedCnt	166	Covered	T9,T10,T14
AutoDispatch->Error	209	Covered	T108,T109,T110
AutoDispatch->Idle	163	Covered	T9,T10,T14
AutoFirstAckWait->AutoDispatch	150	Covered	T9,T10,T14
AutoFirstAckWait->Error	209	Covered	T111,T112,T113
AutoFirstAckWait->Idle	231	Covered	T114,T115,T116
AutoLoadIns->AutoFirstAckWait	144	Covered	T9,T10,T14
AutoLoadIns->Error	209	Covered	T6,T8,T55
AutoLoadIns->Idle	231	Covered	T6,T7,T8
AutoSendGenCmd->AutoAckWait	181	Covered	T9,T10,T14
AutoSendGenCmd->Error	209	Covered	T84
AutoSendGenCmd->Idle	231	Covered	T117
AutoSendReseedCmd->AutoAckWait	193	Covered	T9,T10,T14
AutoSendReseedCmd->Error	209	Not Covered
AutoSendReseedCmd->Idle	231	Covered	T118,T119,T120
BootCaptGenCnt->BootSendGenCmd	109	Covered	T1,T29,T37
BootCaptGenCnt->Error	209	Covered	T15,T121,T122
BootCaptGenCnt->Idle	231	Covered	T123,T124,T125
BootDone->BootLoadUni	128	Covered	T1,T29,T73
BootDone->Error	209	Covered	T126,T127,T128
BootDone->Idle	231	Covered	T129,T130,T131
BootGenAckWait->BootPulse	119	Covered	T1,T29,T37
BootGenAckWait->Error	209	Covered	T132,T133
BootGenAckWait->Idle	231	Covered	T134,T126,T135
BootInsAckWait->BootCaptGenCnt	104	Covered	T1,T29,T37
BootInsAckWait->Error	209	Covered	T53,T136,T135
BootInsAckWait->Idle	231	Covered	T15,T53,T137
BootLoadGen->BootInsAckWait	100	Covered	T1,T29,T37
BootLoadGen->Error	209	Covered	T58
BootLoadGen->Idle	231	Covered	T58,T33,T132
BootLoadIns->BootLoadGen	96	Covered	T1,T29,T37
BootLoadIns->Error	209	Covered	T138,T139,T140
BootLoadIns->Idle	231	Covered	T37,T88,T141
BootLoadUni->BootUniAckWait	133	Covered	T1,T29,T73
BootLoadUni->Error	209	Not Covered
BootLoadUni->Idle	231	Not Covered
BootPulse->BootDone	124	Covered	T1,T29,T37
BootPulse->Error	209	Covered	T142
BootPulse->Idle	231	Covered	T46,T34,T143
BootSendGenCmd->BootGenAckWait	114	Covered	T1,T29,T37
BootSendGenCmd->Error	209	Not Covered
BootSendGenCmd->Idle	231	Covered	T144,T145,T146
BootUniAckWait->Error	209	Not Covered
BootUniAckWait->Idle	137	Covered	T1,T29,T73
Idle->AutoLoadIns	86	Covered	T9,T10,T6
Idle->BootLoadIns	82	Covered	T1,T29,T37
Idle->Error	209	Covered	T20,T21,T22
Idle->SWPortMode	91	Covered	T1,T2,T3
SWPortMode->Error	209	Covered	T16,T54,T74
SWPortMode->Idle	231	Covered	T4,T5,T51

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	60	2	2	100.00
CASE	79	37	36	97.30
IF	208	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	79	case (state_q)
-2-:	81	if ((boot_req_mode_i && edn_enable_i))
-3-:	83	if ((auto_req_mode_i && edn_enable_i))
-4-:	87	if (edn_enable_i)
-5-:	103	if (csrng_cmd_ack_i)
-6-:	113	if (cmd_sent_i)
-7-:	118	if (csrng_cmd_ack_i)
-8-:	127	if ((!boot_req_mode_i))
-9-:	136	if (csrng_cmd_ack_i)
-10-:	143	if (sw_cmd_req_load_i)
-11-:	149	if (csrng_cmd_ack_i)
-12-:	155	if (csrng_cmd_ack_i)
-13-:	161	if ((!auto_req_mode_i))
-14-:	165	if (max_reqs_cnt_zero_i)
-15-:	180	if (cmd_sent_i)
-16-:	192	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T29,T37
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T6
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T29,T37
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T29,T37
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T29,T37
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T29,T37
BootCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T29,T37
BootSendGenCmd	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T29,T37
BootSendGenCmd	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Not Covered
BootGenAckWait	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T29,T37
BootGenAckWait	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T29,T37
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T29,T37
BootDone	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T29,T73
BootDone	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T37,T15,T58
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T29,T73
BootUniAckWait	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T29,T73
BootUniAckWait	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T29,T73
AutoLoadIns	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T9,T10,T14
AutoLoadIns	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T9,T10,T6
AutoFirstAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T9,T10,T14
AutoFirstAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T9,T10,T14
AutoAckWait	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T9,T10,T14
AutoAckWait	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T9,T10,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T9,T14,T32
AutoDispatch	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T9,T10,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T9,T10,T14
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T9,T10,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T10,T42,T32
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T10,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T9,T10,T42
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T24,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T24,T60

	LineNo.	Expression
-1-:	208	if (local_escalate_i)
-2-:	222	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, BootLoadUni, BootUniAckWait, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T24,T15
0	1	Covered	T23,T37,T15
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	228092357	122896	0	0
FpvSecCmErrorStEscalate_A	228092357	123734	0	0
u_state_regs_A	228057214	227904929	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228092357	122896	0	0
T2	1947	1058	0	0
T3	998	0	0	0
T6	1637	647	0	0
T10	2233	0	0	0
T15	1852	1131	0	0
T16	0	391	0	0
T24	920	469	0	0
T33	0	880	0	0
T53	0	1126	0	0
T54	0	598	0	0
T58	671	350	0	0
T59	1460	0	0	0
T60	0	550	0	0
T72	1255	0	0	0
T73	1742	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228092357	123734	0	0
T2	1947	1059	0	0
T3	998	0	0	0
T6	1637	648	0	0
T10	2233	0	0	0
T15	1852	1132	0	0
T16	0	392	0	0
T24	920	470	0	0
T33	0	881	0	0
T53	0	1127	0	0
T54	0	599	0	0
T58	671	351	0	0
T59	1460	0	0	0
T60	0	551	0	0
T72	1255	0	0	0
T73	1742	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228057214	227904929	0	0
T1	1528	1453	0	0
T2	1835	1675	0	0
T3	998	923	0	0
T4	801900	801889	0	0
T5	766025	766012	0	0
T23	1554	1406	0	0
T29	2169	2070	0	0
T50	1070	1020	0	0
T51	16743	16036	0	0
T52	1217	1134	0	0