Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.19	98.73	93.82	90.97	89.47	98.16	96.56	98.58

Total test records in report: 964

T764	/workspace/coverage/default/37.edn_alert.2735952451	Feb 07 12:48:52 PM PST 24	Feb 07 12:48:54 PM PST 24	47976614 ps
T765	/workspace/coverage/default/91.edn_genbits.3257536328	Feb 07 12:49:43 PM PST 24	Feb 07 12:49:46 PM PST 24	76137741 ps
T766	/workspace/coverage/default/33.edn_genbits.944569360	Feb 07 12:48:48 PM PST 24	Feb 07 12:48:51 PM PST 24	36374489 ps
T767	/workspace/coverage/default/214.edn_genbits.3560950870	Feb 07 12:50:00 PM PST 24	Feb 07 12:50:03 PM PST 24	86647402 ps
T768	/workspace/coverage/default/12.edn_smoke.1955997440	Feb 07 12:48:23 PM PST 24	Feb 07 12:48:35 PM PST 24	23826611 ps
T769	/workspace/coverage/default/95.edn_err.759657495	Feb 07 12:49:28 PM PST 24	Feb 07 12:49:30 PM PST 24	28979412 ps
T228	/workspace/coverage/default/25.edn_alert.3196866186	Feb 07 12:48:43 PM PST 24	Feb 07 12:48:47 PM PST 24	58726913 ps
T770	/workspace/coverage/default/278.edn_genbits.157728122	Feb 07 12:50:21 PM PST 24	Feb 07 12:50:23 PM PST 24	32549150 ps
T771	/workspace/coverage/default/3.edn_intr.732673662	Feb 07 12:47:50 PM PST 24	Feb 07 12:47:51 PM PST 24	26939515 ps
T772	/workspace/coverage/default/202.edn_genbits.750856864	Feb 07 12:50:05 PM PST 24	Feb 07 12:50:07 PM PST 24	288330148 ps
T773	/workspace/coverage/default/44.edn_intr.2090867168	Feb 07 12:49:14 PM PST 24	Feb 07 12:49:20 PM PST 24	20786871 ps
T774	/workspace/coverage/default/244.edn_genbits.1196559636	Feb 07 12:49:58 PM PST 24	Feb 07 12:50:00 PM PST 24	49948908 ps
T775	/workspace/coverage/default/28.edn_stress_all_with_rand_reset.3936538048	Feb 07 12:48:37 PM PST 24	Feb 07 12:59:37 PM PST 24	100976001275 ps
T55	/workspace/coverage/default/0.edn_sec_cm.84466939	Feb 07 12:47:47 PM PST 24	Feb 07 12:47:54 PM PST 24	369644745 ps
T776	/workspace/coverage/default/10.edn_smoke.640726488	Feb 07 12:48:05 PM PST 24	Feb 07 12:48:07 PM PST 24	39625191 ps
T777	/workspace/coverage/default/2.edn_stress_all.3804486128	Feb 07 12:47:47 PM PST 24	Feb 07 12:47:52 PM PST 24	777167099 ps
T778	/workspace/coverage/default/27.edn_intr.815144155	Feb 07 12:48:33 PM PST 24	Feb 07 12:48:39 PM PST 24	60559205 ps
T779	/workspace/coverage/default/109.edn_genbits.979860816	Feb 07 12:49:43 PM PST 24	Feb 07 12:49:46 PM PST 24	48798589 ps
T780	/workspace/coverage/default/16.edn_alert_test.3384709634	Feb 07 12:48:19 PM PST 24	Feb 07 12:48:27 PM PST 24	25751867 ps
T781	/workspace/coverage/default/44.edn_alert_test.2539261534	Feb 07 12:49:06 PM PST 24	Feb 07 12:49:09 PM PST 24	17503609 ps
T782	/workspace/coverage/default/13.edn_alert_test.2957450301	Feb 07 12:48:14 PM PST 24	Feb 07 12:48:16 PM PST 24	67302788 ps
T783	/workspace/coverage/default/133.edn_genbits.1372737479	Feb 07 12:49:38 PM PST 24	Feb 07 12:49:43 PM PST 24	65829078 ps
T784	/workspace/coverage/default/8.edn_alert_test.1463788216	Feb 07 12:48:02 PM PST 24	Feb 07 12:48:04 PM PST 24	46659070 ps
T785	/workspace/coverage/default/36.edn_disable.1733428940	Feb 07 12:48:52 PM PST 24	Feb 07 12:48:54 PM PST 24	27609478 ps
T786	/workspace/coverage/default/20.edn_stress_all_with_rand_reset.1350271431	Feb 07 12:48:41 PM PST 24	Feb 07 12:56:11 PM PST 24	19794105201 ps
T787	/workspace/coverage/default/5.edn_stress_all.3799097421	Feb 07 12:47:57 PM PST 24	Feb 07 12:48:02 PM PST 24	1633389403 ps
T788	/workspace/coverage/default/4.edn_alert.3247253514	Feb 07 12:47:58 PM PST 24	Feb 07 12:48:00 PM PST 24	21476865 ps
T72	/workspace/coverage/default/1.edn_intr.2877278527	Feb 07 12:47:47 PM PST 24	Feb 07 12:47:49 PM PST 24	101051257 ps
T789	/workspace/coverage/default/56.edn_genbits.2436092851	Feb 07 12:49:26 PM PST 24	Feb 07 12:49:28 PM PST 24	52494406 ps
T790	/workspace/coverage/default/30.edn_err.1990859836	Feb 07 12:48:37 PM PST 24	Feb 07 12:48:44 PM PST 24	27386651 ps
T791	/workspace/coverage/default/63.edn_genbits.883292738	Feb 07 12:49:30 PM PST 24	Feb 07 12:49:33 PM PST 24	240895697 ps
T792	/workspace/coverage/default/42.edn_smoke.3456270098	Feb 07 12:49:08 PM PST 24	Feb 07 12:49:14 PM PST 24	20744629 ps
T70	/workspace/coverage/default/42.edn_intr.1249311172	Feb 07 12:48:56 PM PST 24	Feb 07 12:48:58 PM PST 24	20565416 ps
T793	/workspace/coverage/default/201.edn_genbits.569457769	Feb 07 12:50:06 PM PST 24	Feb 07 12:50:09 PM PST 24	71630634 ps
T794	/workspace/coverage/default/178.edn_genbits.2045911501	Feb 07 12:49:37 PM PST 24	Feb 07 12:49:42 PM PST 24	27816990 ps
T795	/workspace/coverage/default/257.edn_genbits.4032951434	Feb 07 12:50:09 PM PST 24	Feb 07 12:50:12 PM PST 24	50455695 ps
T796	/workspace/coverage/default/70.edn_genbits.3351964781	Feb 07 12:49:28 PM PST 24	Feb 07 12:49:30 PM PST 24	149040777 ps
T797	/workspace/coverage/default/102.edn_genbits.2975707020	Feb 07 12:49:28 PM PST 24	Feb 07 12:49:31 PM PST 24	31333055 ps
T798	/workspace/coverage/default/15.edn_disable_auto_req_mode.1719781842	Feb 07 12:48:18 PM PST 24	Feb 07 12:48:27 PM PST 24	63628219 ps
T799	/workspace/coverage/default/35.edn_err.1418633107	Feb 07 12:48:44 PM PST 24	Feb 07 12:48:48 PM PST 24	31676888 ps
T800	/workspace/coverage/default/9.edn_smoke.1275201121	Feb 07 12:48:17 PM PST 24	Feb 07 12:48:19 PM PST 24	192789815 ps
T801	/workspace/coverage/default/46.edn_smoke.2609556755	Feb 07 12:49:17 PM PST 24	Feb 07 12:49:21 PM PST 24	16351676 ps
T802	/workspace/coverage/default/95.edn_genbits.2397105375	Feb 07 12:49:26 PM PST 24	Feb 07 12:49:29 PM PST 24	229503760 ps
T803	/workspace/coverage/default/32.edn_stress_all.819664498	Feb 07 12:48:44 PM PST 24	Feb 07 12:48:52 PM PST 24	268313346 ps
T804	/workspace/coverage/default/175.edn_genbits.3964196557	Feb 07 12:49:41 PM PST 24	Feb 07 12:49:45 PM PST 24	23810841 ps
T805	/workspace/coverage/default/235.edn_genbits.2673018018	Feb 07 12:49:55 PM PST 24	Feb 07 12:49:58 PM PST 24	39627144 ps
T806	/workspace/coverage/default/296.edn_genbits.3810974405	Feb 07 12:50:10 PM PST 24	Feb 07 12:50:13 PM PST 24	288715897 ps
T807	/workspace/coverage/default/243.edn_genbits.1948867205	Feb 07 12:49:49 PM PST 24	Feb 07 12:49:52 PM PST 24	26811088 ps
T808	/workspace/coverage/default/122.edn_genbits.3695383770	Feb 07 12:49:42 PM PST 24	Feb 07 12:49:47 PM PST 24	68950840 ps
T809	/workspace/coverage/default/48.edn_stress_all.4201474079	Feb 07 12:49:17 PM PST 24	Feb 07 12:49:22 PM PST 24	105733608 ps
T810	/workspace/coverage/default/6.edn_err.1553855054	Feb 07 12:47:59 PM PST 24	Feb 07 12:48:01 PM PST 24	46774283 ps
T811	/workspace/coverage/default/70.edn_err.3843150718	Feb 07 12:49:34 PM PST 24	Feb 07 12:49:37 PM PST 24	30025586 ps
T194	/workspace/coverage/default/2.edn_genbits.320753285	Feb 07 12:47:47 PM PST 24	Feb 07 12:47:51 PM PST 24	104424383 ps
T812	/workspace/coverage/default/4.edn_stress_all.3999355032	Feb 07 12:47:55 PM PST 24	Feb 07 12:47:57 PM PST 24	160234150 ps
T813	/workspace/coverage/default/47.edn_smoke.855770358	Feb 07 12:49:13 PM PST 24	Feb 07 12:49:16 PM PST 24	16651494 ps
T814	/workspace/coverage/default/135.edn_genbits.2641175453	Feb 07 12:49:42 PM PST 24	Feb 07 12:49:45 PM PST 24	136220140 ps
T815	/workspace/coverage/default/1.edn_genbits.2406212673	Feb 07 12:47:45 PM PST 24	Feb 07 12:47:47 PM PST 24	47026253 ps
T816	/workspace/coverage/default/35.edn_stress_all.3376647147	Feb 07 12:48:40 PM PST 24	Feb 07 12:48:46 PM PST 24	128338061 ps
T817	/workspace/coverage/default/17.edn_stress_all_with_rand_reset.2327887537	Feb 07 12:48:20 PM PST 24	Feb 07 01:15:17 PM PST 24	71539907747 ps
T188	/workspace/coverage/default/203.edn_genbits.3504680992	Feb 07 12:49:45 PM PST 24	Feb 07 12:49:49 PM PST 24	48041137 ps
T818	/workspace/coverage/default/17.edn_err.3386074062	Feb 07 12:48:18 PM PST 24	Feb 07 12:48:27 PM PST 24	87582720 ps
T819	/workspace/coverage/default/49.edn_genbits.1204716889	Feb 07 12:49:26 PM PST 24	Feb 07 12:49:28 PM PST 24	43926011 ps
T820	/workspace/coverage/default/22.edn_alert_test.527452570	Feb 07 12:48:37 PM PST 24	Feb 07 12:48:44 PM PST 24	16217006 ps
T821	/workspace/coverage/default/211.edn_genbits.2416800690	Feb 07 12:49:51 PM PST 24	Feb 07 12:49:53 PM PST 24	96445333 ps
T822	/workspace/coverage/default/20.edn_disable_auto_req_mode.2527435833	Feb 07 12:48:29 PM PST 24	Feb 07 12:48:38 PM PST 24	88503651 ps
T823	/workspace/coverage/default/0.edn_smoke.1849290524	Feb 07 12:47:42 PM PST 24	Feb 07 12:47:44 PM PST 24	41594465 ps
T824	/workspace/coverage/default/23.edn_alert_test.3300130131	Feb 07 12:48:39 PM PST 24	Feb 07 12:48:45 PM PST 24	35110359 ps
T825	/workspace/coverage/default/39.edn_alert.2650045444	Feb 07 12:48:57 PM PST 24	Feb 07 12:48:59 PM PST 24	75339314 ps
T227	/workspace/coverage/default/12.edn_alert.1132568487	Feb 07 12:48:19 PM PST 24	Feb 07 12:48:27 PM PST 24	24944890 ps
T826	/workspace/coverage/default/12.edn_genbits.77770761	Feb 07 12:48:18 PM PST 24	Feb 07 12:48:27 PM PST 24	54342699 ps
T827	/workspace/coverage/default/65.edn_genbits.3613149397	Feb 07 12:49:42 PM PST 24	Feb 07 12:49:46 PM PST 24	108898430 ps
T828	/workspace/coverage/default/17.edn_alert.2035514794	Feb 07 12:48:20 PM PST 24	Feb 07 12:48:27 PM PST 24	123720506 ps
T829	/workspace/coverage/default/31.edn_stress_all.193740057	Feb 07 12:48:43 PM PST 24	Feb 07 12:48:48 PM PST 24	137623846 ps
T830	/workspace/coverage/default/18.edn_disable.4208307052	Feb 07 12:48:22 PM PST 24	Feb 07 12:48:27 PM PST 24	20675572 ps
T831	/workspace/coverage/default/13.edn_smoke.502890029	Feb 07 12:48:29 PM PST 24	Feb 07 12:48:37 PM PST 24	32782403 ps
T832	/workspace/coverage/default/42.edn_stress_all.4160189507	Feb 07 12:49:09 PM PST 24	Feb 07 12:49:20 PM PST 24	310477918 ps
T833	/workspace/coverage/default/28.edn_genbits.2511847471	Feb 07 12:48:41 PM PST 24	Feb 07 12:48:46 PM PST 24	58884411 ps
T834	/workspace/coverage/default/16.edn_alert.605129700	Feb 07 12:48:21 PM PST 24	Feb 07 12:48:27 PM PST 24	23700563 ps
T835	/workspace/coverage/default/116.edn_genbits.3053580785	Feb 07 12:49:36 PM PST 24	Feb 07 12:49:40 PM PST 24	58081726 ps
T836	/workspace/coverage/default/27.edn_stress_all.1349162106	Feb 07 12:48:37 PM PST 24	Feb 07 12:48:48 PM PST 24	471530419 ps
T837	/workspace/coverage/default/36.edn_intr.2322314708	Feb 07 12:48:48 PM PST 24	Feb 07 12:48:50 PM PST 24	30116490 ps
T838	/workspace/coverage/default/22.edn_smoke.1426796246	Feb 07 12:48:35 PM PST 24	Feb 07 12:48:42 PM PST 24	60531753 ps
T839	/workspace/coverage/default/1.edn_smoke.3528778295	Feb 07 12:47:45 PM PST 24	Feb 07 12:47:47 PM PST 24	18534462 ps
T233	/workspace/coverage/default/23.edn_alert.3205130872	Feb 07 12:48:29 PM PST 24	Feb 07 12:48:38 PM PST 24	46904322 ps
T840	/workspace/coverage/default/289.edn_genbits.1674329215	Feb 07 12:50:20 PM PST 24	Feb 07 12:50:22 PM PST 24	46627272 ps
T841	/workspace/coverage/default/37.edn_stress_all_with_rand_reset.4190525434	Feb 07 12:48:49 PM PST 24	Feb 07 01:07:50 PM PST 24	43613734786 ps
T842	/workspace/coverage/default/285.edn_genbits.2798292913	Feb 07 12:50:20 PM PST 24	Feb 07 12:50:22 PM PST 24	32285765 ps
T843	/workspace/coverage/default/3.edn_disable.1651517659	Feb 07 12:47:49 PM PST 24	Feb 07 12:47:51 PM PST 24	18448137 ps
T844	/workspace/coverage/default/288.edn_genbits.3516623659	Feb 07 12:50:01 PM PST 24	Feb 07 12:50:05 PM PST 24	42484093 ps
T845	/workspace/coverage/default/231.edn_genbits.3355170807	Feb 07 12:49:53 PM PST 24	Feb 07 12:49:57 PM PST 24	226744405 ps
T846	/workspace/coverage/default/29.edn_err.120318567	Feb 07 12:48:35 PM PST 24	Feb 07 12:48:40 PM PST 24	21529533 ps
T847	/workspace/coverage/default/88.edn_err.2208937842	Feb 07 12:49:38 PM PST 24	Feb 07 12:49:42 PM PST 24	18503239 ps
T848	/workspace/coverage/default/212.edn_genbits.1918681531	Feb 07 12:49:57 PM PST 24	Feb 07 12:50:00 PM PST 24	48422304 ps
T849	/workspace/coverage/default/4.edn_alert_test.3689397220	Feb 07 12:47:56 PM PST 24	Feb 07 12:47:58 PM PST 24	20087070 ps
T850	/workspace/coverage/default/23.edn_intr.2985327754	Feb 07 12:48:35 PM PST 24	Feb 07 12:48:42 PM PST 24	22335349 ps
T851	/workspace/coverage/default/173.edn_genbits.2431128923	Feb 07 12:49:44 PM PST 24	Feb 07 12:49:47 PM PST 24	63944212 ps
T852	/workspace/coverage/default/11.edn_stress_all.1853084630	Feb 07 12:48:05 PM PST 24	Feb 07 12:48:07 PM PST 24	39233715 ps
T853	/workspace/coverage/default/6.edn_intr.872770249	Feb 07 12:47:57 PM PST 24	Feb 07 12:47:59 PM PST 24	20511468 ps
T854	/workspace/coverage/default/45.edn_genbits.3895940495	Feb 07 12:49:21 PM PST 24	Feb 07 12:49:25 PM PST 24	136907169 ps
T222	/workspace/coverage/default/49.edn_alert.3693136577	Feb 07 12:49:16 PM PST 24	Feb 07 12:49:20 PM PST 24	48844935 ps
T855	/workspace/coverage/default/137.edn_genbits.473374820	Feb 07 12:49:50 PM PST 24	Feb 07 12:49:53 PM PST 24	194374616 ps
T856	/workspace/coverage/default/15.edn_err.1462581392	Feb 07 12:48:22 PM PST 24	Feb 07 12:48:27 PM PST 24	36823825 ps
T857	/workspace/coverage/default/59.edn_genbits.3973763449	Feb 07 12:49:32 PM PST 24	Feb 07 12:49:35 PM PST 24	311163793 ps
T858	/workspace/coverage/default/10.edn_stress_all_with_rand_reset.1085477436	Feb 07 12:48:05 PM PST 24	Feb 07 01:07:08 PM PST 24	220078956996 ps
T108	/workspace/coverage/default/0.edn_disable.367640931	Feb 07 12:47:39 PM PST 24	Feb 07 12:47:42 PM PST 24	13282342 ps
T116	/workspace/coverage/default/29.edn_disable.4156591558	Feb 07 12:48:40 PM PST 24	Feb 07 12:48:45 PM PST 24	21849806 ps
T859	/workspace/coverage/default/49.edn_err.3340310579	Feb 07 12:49:29 PM PST 24	Feb 07 12:49:32 PM PST 24	45723877 ps
T860	/workspace/coverage/default/14.edn_smoke.2789837456	Feb 07 12:48:17 PM PST 24	Feb 07 12:48:22 PM PST 24	18618096 ps
T861	/workspace/coverage/default/24.edn_stress_all_with_rand_reset.1046783506	Feb 07 12:48:26 PM PST 24	Feb 07 01:04:05 PM PST 24	120008570188 ps
T862	/workspace/coverage/default/46.edn_stress_all_with_rand_reset.1450704568	Feb 07 12:49:15 PM PST 24	Feb 07 12:56:22 PM PST 24	19046576618 ps
T863	/workspace/coverage/default/47.edn_disable.292405214	Feb 07 12:49:22 PM PST 24	Feb 07 12:49:24 PM PST 24	11170792 ps
T864	/workspace/coverage/default/8.edn_alert.3135803574	Feb 07 12:48:04 PM PST 24	Feb 07 12:48:06 PM PST 24	21248096 ps
T865	/workspace/coverage/default/51.edn_err.3492538568	Feb 07 12:49:24 PM PST 24	Feb 07 12:49:26 PM PST 24	33457397 ps
T866	/workspace/coverage/default/19.edn_smoke.3555715613	Feb 07 12:48:24 PM PST 24	Feb 07 12:48:35 PM PST 24	47884270 ps
T867	/workspace/coverage/default/49.edn_intr.1770780598	Feb 07 12:49:22 PM PST 24	Feb 07 12:49:24 PM PST 24	22200325 ps
T868	/workspace/coverage/default/13.edn_alert.2282866046	Feb 07 12:48:19 PM PST 24	Feb 07 12:48:27 PM PST 24	30198021 ps
T869	/workspace/coverage/default/48.edn_err.2728668479	Feb 07 12:49:21 PM PST 24	Feb 07 12:49:23 PM PST 24	25732828 ps
T870	/workspace/coverage/default/258.edn_genbits.548835461	Feb 07 12:50:14 PM PST 24	Feb 07 12:50:16 PM PST 24	177719113 ps
T871	/workspace/coverage/default/39.edn_stress_all_with_rand_reset.3750763464	Feb 07 12:48:54 PM PST 24	Feb 07 12:56:52 PM PST 24	85032869890 ps
T872	/workspace/coverage/default/54.edn_genbits.2401203193	Feb 07 12:49:30 PM PST 24	Feb 07 12:49:33 PM PST 24	71741183 ps
T873	/workspace/coverage/default/274.edn_genbits.1697935772	Feb 07 12:50:13 PM PST 24	Feb 07 12:50:16 PM PST 24	54066907 ps
T874	/workspace/coverage/default/4.edn_disable.3882718400	Feb 07 12:47:53 PM PST 24	Feb 07 12:47:54 PM PST 24	73746683 ps
T875	/workspace/coverage/default/11.edn_disable_auto_req_mode.3018100408	Feb 07 12:48:18 PM PST 24	Feb 07 12:48:27 PM PST 24	32647466 ps
T876	/workspace/coverage/default/226.edn_genbits.2304516293	Feb 07 12:49:54 PM PST 24	Feb 07 12:49:56 PM PST 24	57987734 ps
T877	/workspace/coverage/default/49.edn_stress_all.2694596302	Feb 07 12:49:14 PM PST 24	Feb 07 12:49:21 PM PST 24	270697960 ps
T878	/workspace/coverage/default/187.edn_genbits.701244764	Feb 07 12:49:51 PM PST 24	Feb 07 12:49:53 PM PST 24	85722659 ps
T879	/workspace/coverage/default/41.edn_stress_all.2426558841	Feb 07 12:49:07 PM PST 24	Feb 07 12:49:14 PM PST 24	515317321 ps
T880	/workspace/coverage/default/222.edn_genbits.3782284136	Feb 07 12:49:45 PM PST 24	Feb 07 12:49:49 PM PST 24	47702944 ps
T881	/workspace/coverage/default/282.edn_genbits.551102300	Feb 07 12:50:11 PM PST 24	Feb 07 12:50:14 PM PST 24	87441215 ps
T882	/workspace/coverage/default/43.edn_smoke.2892450770	Feb 07 12:49:09 PM PST 24	Feb 07 12:49:15 PM PST 24	33237752 ps
T883	/workspace/coverage/default/42.edn_alert.736357649	Feb 07 12:49:06 PM PST 24	Feb 07 12:49:09 PM PST 24	39277048 ps
T182	/workspace/coverage/default/254.edn_genbits.3686889569	Feb 07 12:50:03 PM PST 24	Feb 07 12:50:06 PM PST 24	39832346 ps
T884	/workspace/coverage/default/74.edn_genbits.1605686583	Feb 07 12:49:30 PM PST 24	Feb 07 12:49:32 PM PST 24	319716759 ps
T885	/workspace/coverage/default/43.edn_stress_all.1265700174	Feb 07 12:49:01 PM PST 24	Feb 07 12:49:07 PM PST 24	1348101754 ps
T886	/workspace/coverage/default/1.edn_stress_all_with_rand_reset.812486978	Feb 07 12:47:46 PM PST 24	Feb 07 01:14:38 PM PST 24	62091407545 ps
T887	/workspace/coverage/default/27.edn_alert.2579952387	Feb 07 12:48:31 PM PST 24	Feb 07 12:48:39 PM PST 24	31572144 ps
T888	/workspace/coverage/default/20.edn_smoke.3453388198	Feb 07 12:48:23 PM PST 24	Feb 07 12:48:28 PM PST 24	45505959 ps
T889	/workspace/coverage/default/26.edn_disable_auto_req_mode.1033691603	Feb 07 12:48:34 PM PST 24	Feb 07 12:48:40 PM PST 24	120306767 ps
T890	/workspace/coverage/default/36.edn_disable_auto_req_mode.2868671409	Feb 07 12:48:49 PM PST 24	Feb 07 12:48:52 PM PST 24	75208186 ps
T891	/workspace/coverage/default/3.edn_stress_all_with_rand_reset.1017018988	Feb 07 12:47:47 PM PST 24	Feb 07 01:02:14 PM PST 24	194463004454 ps
T892	/workspace/coverage/default/298.edn_genbits.3884941750	Feb 07 12:50:22 PM PST 24	Feb 07 12:50:24 PM PST 24	42051706 ps
T893	/workspace/coverage/default/67.edn_genbits.1230527424	Feb 07 12:49:33 PM PST 24	Feb 07 12:49:36 PM PST 24	57862088 ps
T894	/workspace/coverage/default/38.edn_alert.855792084	Feb 07 12:49:03 PM PST 24	Feb 07 12:49:05 PM PST 24	35007243 ps
T895	/workspace/coverage/default/78.edn_genbits.1878236163	Feb 07 12:49:36 PM PST 24	Feb 07 12:49:40 PM PST 24	73388317 ps
T896	/workspace/coverage/default/19.edn_err.3441771248	Feb 07 12:48:30 PM PST 24	Feb 07 12:48:38 PM PST 24	21453878 ps
T897	/workspace/coverage/default/37.edn_alert_test.1065524949	Feb 07 12:48:51 PM PST 24	Feb 07 12:48:53 PM PST 24	53082450 ps
T898	/workspace/coverage/default/12.edn_disable_auto_req_mode.2240051746	Feb 07 12:48:15 PM PST 24	Feb 07 12:48:17 PM PST 24	157105204 ps
T899	/workspace/coverage/default/248.edn_genbits.4081989228	Feb 07 12:50:16 PM PST 24	Feb 07 12:50:18 PM PST 24	71737907 ps
T900	/workspace/coverage/default/18.edn_genbits.1650957094	Feb 07 12:48:26 PM PST 24	Feb 07 12:48:37 PM PST 24	58579289 ps
T901	/workspace/coverage/default/27.edn_disable_auto_req_mode.3948594502	Feb 07 12:48:36 PM PST 24	Feb 07 12:48:43 PM PST 24	52283834 ps
T229	/workspace/coverage/default/26.edn_alert.2748588327	Feb 07 12:48:39 PM PST 24	Feb 07 12:48:45 PM PST 24	21032232 ps
T902	/workspace/coverage/default/195.edn_genbits.2223044635	Feb 07 12:50:13 PM PST 24	Feb 07 12:50:16 PM PST 24	64956831 ps
T903	/workspace/coverage/default/29.edn_alert_test.4180119559	Feb 07 12:48:40 PM PST 24	Feb 07 12:48:45 PM PST 24	47594775 ps
T904	/workspace/coverage/default/188.edn_genbits.1266675736	Feb 07 12:49:36 PM PST 24	Feb 07 12:49:40 PM PST 24	218191895 ps
T905	/workspace/coverage/default/111.edn_genbits.3363937506	Feb 07 12:49:38 PM PST 24	Feb 07 12:49:42 PM PST 24	72142309 ps
T906	/workspace/coverage/default/48.edn_genbits.2246569268	Feb 07 12:49:17 PM PST 24	Feb 07 12:49:21 PM PST 24	65747220 ps
T907	/workspace/coverage/default/45.edn_alert_test.2388308071	Feb 07 12:49:04 PM PST 24	Feb 07 12:49:06 PM PST 24	70088267 ps
T908	/workspace/coverage/default/0.edn_genbits.235157000	Feb 07 12:47:54 PM PST 24	Feb 07 12:47:56 PM PST 24	71300370 ps
T909	/workspace/coverage/default/156.edn_genbits.3329600457	Feb 07 12:49:52 PM PST 24	Feb 07 12:49:55 PM PST 24	73836644 ps
T910	/workspace/coverage/default/33.edn_alert.3382575514	Feb 07 12:48:48 PM PST 24	Feb 07 12:48:50 PM PST 24	23390861 ps
T911	/workspace/coverage/default/45.edn_disable.187063159	Feb 07 12:49:10 PM PST 24	Feb 07 12:49:15 PM PST 24	36434032 ps
T912	/workspace/coverage/default/28.edn_intr.262647102	Feb 07 12:48:37 PM PST 24	Feb 07 12:48:43 PM PST 24	37426952 ps
T913	/workspace/coverage/default/92.edn_genbits.2609814855	Feb 07 12:49:39 PM PST 24	Feb 07 12:49:45 PM PST 24	256276126 ps
T914	/workspace/coverage/default/33.edn_smoke.1143900099	Feb 07 12:48:44 PM PST 24	Feb 07 12:48:48 PM PST 24	43402102 ps
T915	/workspace/coverage/default/20.edn_genbits.873845943	Feb 07 12:48:35 PM PST 24	Feb 07 12:48:40 PM PST 24	30785507 ps
T916	/workspace/coverage/default/31.edn_alert_test.2435644201	Feb 07 12:48:55 PM PST 24	Feb 07 12:48:57 PM PST 24	77568631 ps
T917	/workspace/coverage/default/146.edn_genbits.1858473450	Feb 07 12:49:46 PM PST 24	Feb 07 12:49:49 PM PST 24	25611567 ps
T918	/workspace/coverage/default/36.edn_stress_all_with_rand_reset.2029010436	Feb 07 12:48:46 PM PST 24	Feb 07 01:07:31 PM PST 24	74990153018 ps
T919	/workspace/coverage/default/38.edn_err.2281978585	Feb 07 12:48:53 PM PST 24	Feb 07 12:48:55 PM PST 24	19664398 ps
T920	/workspace/coverage/default/21.edn_intr.159927032	Feb 07 12:48:33 PM PST 24	Feb 07 12:48:39 PM PST 24	33183509 ps
T921	/workspace/coverage/default/49.edn_disable_auto_req_mode.2608319798	Feb 07 12:49:24 PM PST 24	Feb 07 12:49:26 PM PST 24	75360582 ps
T922	/workspace/coverage/default/17.edn_smoke.272469557	Feb 07 12:48:21 PM PST 24	Feb 07 12:48:27 PM PST 24	15723684 ps
T923	/workspace/coverage/default/3.edn_disable_auto_req_mode.1735709546	Feb 07 12:47:50 PM PST 24	Feb 07 12:47:52 PM PST 24	39320996 ps
T924	/workspace/coverage/default/30.edn_intr.3123680310	Feb 07 12:48:39 PM PST 24	Feb 07 12:48:45 PM PST 24	22385789 ps
T925	/workspace/coverage/default/14.edn_stress_all.3072009492	Feb 07 12:48:18 PM PST 24	Feb 07 12:48:27 PM PST 24	788011264 ps
T926	/workspace/coverage/default/11.edn_alert_test.1418678857	Feb 07 12:48:15 PM PST 24	Feb 07 12:48:17 PM PST 24	32147636 ps
T927	/workspace/coverage/default/275.edn_genbits.592218006	Feb 07 12:50:12 PM PST 24	Feb 07 12:50:15 PM PST 24	45424621 ps
T928	/workspace/coverage/default/19.edn_genbits.3799944125	Feb 07 12:48:37 PM PST 24	Feb 07 12:48:44 PM PST 24	69891245 ps
T929	/workspace/coverage/default/94.edn_genbits.1390545205	Feb 07 12:49:26 PM PST 24	Feb 07 12:49:28 PM PST 24	41182825 ps
T930	/workspace/coverage/default/46.edn_disable.1216911175	Feb 07 12:49:23 PM PST 24	Feb 07 12:49:25 PM PST 24	14027775 ps
T931	/workspace/coverage/default/144.edn_genbits.839076557	Feb 07 12:49:46 PM PST 24	Feb 07 12:49:49 PM PST 24	87715382 ps
T932	/workspace/coverage/default/0.edn_regwen.4680722	Feb 07 12:47:40 PM PST 24	Feb 07 12:47:42 PM PST 24	24081327 ps
T933	/workspace/coverage/default/44.edn_stress_all_with_rand_reset.2269978236	Feb 07 12:49:14 PM PST 24	Feb 07 01:03:46 PM PST 24	133278475196 ps
T934	/workspace/coverage/default/174.edn_genbits.3876232494	Feb 07 12:49:44 PM PST 24	Feb 07 12:49:47 PM PST 24	63693446 ps
T935	/workspace/coverage/default/8.edn_disable.2821015017	Feb 07 12:48:06 PM PST 24	Feb 07 12:48:08 PM PST 24	17971718 ps
T936	/workspace/coverage/default/84.edn_err.4130526313	Feb 07 12:49:39 PM PST 24	Feb 07 12:49:43 PM PST 24	127465918 ps
T937	/workspace/coverage/default/32.edn_alert.4161351435	Feb 07 12:48:48 PM PST 24	Feb 07 12:48:50 PM PST 24	39970949 ps
T938	/workspace/coverage/default/57.edn_err.1681026892	Feb 07 12:49:31 PM PST 24	Feb 07 12:49:34 PM PST 24	101598546 ps
T939	/workspace/coverage/default/40.edn_alert_test.1986961808	Feb 07 12:48:59 PM PST 24	Feb 07 12:49:02 PM PST 24	15631514 ps
T940	/workspace/coverage/default/273.edn_genbits.2601720888	Feb 07 12:50:02 PM PST 24	Feb 07 12:50:05 PM PST 24	125171467 ps
T941	/workspace/coverage/default/98.edn_genbits.3737809275	Feb 07 12:49:31 PM PST 24	Feb 07 12:49:34 PM PST 24	32558981 ps
T942	/workspace/coverage/default/25.edn_intr.2520012249	Feb 07 12:48:33 PM PST 24	Feb 07 12:48:39 PM PST 24	23324720 ps
T943	/workspace/coverage/default/80.edn_err.3682026667	Feb 07 12:49:39 PM PST 24	Feb 07 12:49:43 PM PST 24	53489464 ps
T944	/workspace/coverage/default/47.edn_stress_all_with_rand_reset.2720042150	Feb 07 12:49:15 PM PST 24	Feb 07 01:00:26 PM PST 24	105971453880 ps
T945	/workspace/coverage/default/78.edn_err.3550250642	Feb 07 12:49:39 PM PST 24	Feb 07 12:49:42 PM PST 24	21349805 ps
T946	/workspace/coverage/default/189.edn_genbits.2275393789	Feb 07 12:49:47 PM PST 24	Feb 07 12:49:51 PM PST 24	80776925 ps
T947	/workspace/coverage/default/49.edn_smoke.3339623808	Feb 07 12:49:13 PM PST 24	Feb 07 12:49:19 PM PST 24	56746275 ps
T948	/workspace/coverage/default/16.edn_stress_all.3973707457	Feb 07 12:48:18 PM PST 24	Feb 07 12:48:31 PM PST 24	972032809 ps
T949	/workspace/coverage/default/29.edn_smoke.1136402287	Feb 07 12:48:50 PM PST 24	Feb 07 12:48:52 PM PST 24	32761741 ps
T950	/workspace/coverage/default/9.edn_genbits.1818444949	Feb 07 12:48:08 PM PST 24	Feb 07 12:48:12 PM PST 24	64840481 ps
T951	/workspace/coverage/default/49.edn_stress_all_with_rand_reset.2076305265	Feb 07 12:49:30 PM PST 24	Feb 07 12:59:33 PM PST 24	26655129352 ps
T952	/workspace/coverage/default/250.edn_genbits.2481866697	Feb 07 12:50:12 PM PST 24	Feb 07 12:50:15 PM PST 24	111859334 ps
T953	/workspace/coverage/default/42.edn_genbits.1233927430	Feb 07 12:49:09 PM PST 24	Feb 07 12:49:16 PM PST 24	66550217 ps
T954	/workspace/coverage/default/28.edn_alert_test.898097416	Feb 07 12:48:38 PM PST 24	Feb 07 12:48:44 PM PST 24	19474549 ps
T955	/workspace/coverage/default/42.edn_stress_all_with_rand_reset.59047228	Feb 07 12:49:07 PM PST 24	Feb 07 12:59:16 PM PST 24	91708174796 ps
T956	/workspace/coverage/default/54.edn_err.2777402736	Feb 07 12:49:30 PM PST 24	Feb 07 12:49:32 PM PST 24	20769522 ps
T957	/workspace/coverage/default/11.edn_alert.3093735883	Feb 07 12:48:07 PM PST 24	Feb 07 12:48:09 PM PST 24	38093171 ps
T958	/workspace/coverage/default/5.edn_intr.3190474056	Feb 07 12:47:58 PM PST 24	Feb 07 12:48:00 PM PST 24	39046153 ps
T959	/workspace/coverage/default/10.edn_genbits.770768366	Feb 07 12:48:06 PM PST 24	Feb 07 12:48:09 PM PST 24	43510535 ps
T960	/workspace/coverage/default/33.edn_stress_all.1676938359	Feb 07 12:48:42 PM PST 24	Feb 07 12:48:50 PM PST 24	237463396 ps
T961	/workspace/coverage/default/40.edn_disable_auto_req_mode.3025505497	Feb 07 12:49:10 PM PST 24	Feb 07 12:49:16 PM PST 24	88486337 ps
T962	/workspace/coverage/default/6.edn_alert.2508020451	Feb 07 12:47:58 PM PST 24	Feb 07 12:48:00 PM PST 24	22468172 ps
T963	/workspace/coverage/default/40.edn_genbits.2012258216	Feb 07 12:48:56 PM PST 24	Feb 07 12:49:00 PM PST 24	77803194 ps
T964	/workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2527012968	Feb 07 01:16:01 PM PST 24	Feb 07 01:16:02 PM PST 24	17524578 ps

Test location	/workspace/coverage/cover_reg_top/1.edn_csr_rw.622246443
Short name	T17
Test name
Test status
Simulation time	14620244 ps
CPU time	0.88 seconds
Started	Feb 07 01:14:50 PM PST 24
Finished	Feb 07 01:14:51 PM PST 24
Peak memory	205860 kb
Host	smart-1f0e993f-2110-4150-b40c-9c3f524135a8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622246443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.622246443
Directory	/workspace/1.edn_csr_rw/latest

Test location	/workspace/coverage/default/260.edn_genbits.834908712
Short name	T29
Test name
Test status
Simulation time	84546708 ps
CPU time	1.48 seconds
Started	Feb 07 12:50:09 PM PST 24
Finished	Feb 07 12:50:12 PM PST 24
Peak memory	217868 kb
Host	smart-f8a9c73f-c5d8-431e-a98f-969235c47749
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834908712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.834908712
Directory	/workspace/260.edn_genbits/latest

Test location	/workspace/coverage/cover_reg_top/3.edn_tl_errors.808361439
Short name	T23
Test name
Test status
Simulation time	212523872 ps
CPU time	3.78 seconds
Started	Feb 07 01:15:04 PM PST 24
Finished	Feb 07 01:15:09 PM PST 24
Peak memory	214172 kb
Host	smart-8c0dda9f-d0fa-423f-9167-e5f08bff8053
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808361439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.808361439
Directory	/workspace/3.edn_tl_errors/latest

Test location	/workspace/coverage/default/77.edn_err.1656406500
Short name	T48
Test name
Test status
Simulation time	19292033 ps
CPU time	1.13 seconds
Started	Feb 07 12:49:38 PM PST 24
Finished	Feb 07 12:49:42 PM PST 24
Peak memory	222464 kb
Host	smart-aa5f2c06-9937-4fb9-b3e0-033fed789157
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1656406500 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1656406500
Directory	/workspace/77.edn_err/latest

Test location	/workspace/coverage/default/22.edn_stress_all_with_rand_reset.3403991265
Short name	T32
Test name
Test status
Simulation time	42179002981 ps
CPU time	445.64 seconds
Started	Feb 07 12:48:39 PM PST 24
Finished	Feb 07 12:56:10 PM PST 24
Peak memory	215752 kb
Host	smart-364c20b1-8fa0-4778-a59a-83b6dbe1c395
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403991265 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3403991265
Directory	/workspace/22.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.edn_genbits.1436143099
Short name	T42
Test name
Test status
Simulation time	115058146 ps
CPU time	1.68 seconds
Started	Feb 07 12:48:44 PM PST 24
Finished	Feb 07 12:48:48 PM PST 24
Peak memory	217244 kb
Host	smart-1d5131f6-38bd-4ba9-afc3-03e531ff7e79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1436143099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1436143099
Directory	/workspace/36.edn_genbits/latest

Test location	/workspace/coverage/cover_reg_top/5.edn_intr_test.4099828141
Short name	T204
Test name
Test status
Simulation time	35170650 ps
CPU time	0.77 seconds
Started	Feb 07 01:15:18 PM PST 24
Finished	Feb 07 01:15:23 PM PST 24
Peak memory	205744 kb
Host	smart-de0eb1c7-9000-46e5-81d8-cbcf63ce9f2b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099828141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.4099828141
Directory	/workspace/5.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.edn_tl_intg_err.839482987
Short name	T126
Test name
Test status
Simulation time	103950474 ps
CPU time	2.71 seconds
Started	Feb 07 01:15:21 PM PST 24
Finished	Feb 07 01:15:29 PM PST 24
Peak memory	205916 kb
Host	smart-8ba40935-19ca-4b2a-af27-8f440828cc27
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839482987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.839482987
Directory	/workspace/7.edn_tl_intg_err/latest

Test location	/workspace/coverage/default/15.edn_stress_all_with_rand_reset.4157059682
Short name	T208
Test name
Test status
Simulation time	43530156863 ps
CPU time	1027.77 seconds
Started	Feb 07 12:48:15 PM PST 24
Finished	Feb 07 01:05:24 PM PST 24
Peak memory	223472 kb
Host	smart-0c0c4e99-8a8a-492c-a23e-6a19f0141a0b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157059682 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.4157059682
Directory	/workspace/15.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.edn_sec_cm.3112619286
Short name	T4
Test name
Test status
Simulation time	1285742271 ps
CPU time	5.59 seconds
Started	Feb 07 12:47:49 PM PST 24
Finished	Feb 07 12:47:55 PM PST 24
Peak memory	234684 kb
Host	smart-5c072519-fcdc-48d0-8aaf-b7b678cb9ce8
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112619286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3112619286
Directory	/workspace/2.edn_sec_cm/latest

Test location	/workspace/coverage/default/20.edn_intr.1952310579
Short name	T68
Test name
Test status
Simulation time	29009976 ps
CPU time	0.89 seconds
Started	Feb 07 12:48:29 PM PST 24
Finished	Feb 07 12:48:37 PM PST 24
Peak memory	215208 kb
Host	smart-99ed7874-9c39-4443-9770-4f70a963e8ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1952310579 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1952310579
Directory	/workspace/20.edn_intr/latest

Test location	/workspace/coverage/default/24.edn_genbits.1241792563
Short name	T178
Test name
Test status
Simulation time	36154241 ps
CPU time	1.37 seconds
Started	Feb 07 12:48:37 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	218116 kb
Host	smart-67197b90-ad50-4564-bfa9-31498e697bad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1241792563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1241792563
Directory	/workspace/24.edn_genbits/latest

Test location	/workspace/coverage/default/14.edn_alert.2985278313
Short name	T236
Test name
Test status
Simulation time	22217185 ps
CPU time	1.07 seconds
Started	Feb 07 12:48:18 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	206136 kb
Host	smart-317183ea-5c95-42fd-bd0a-39a684112b2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2985278313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2985278313
Directory	/workspace/14.edn_alert/latest

Test location	/workspace/coverage/cover_reg_top/2.edn_csr_rw.1198923578
Short name	T43
Test name
Test status
Simulation time	30207472 ps
CPU time	0.81 seconds
Started	Feb 07 01:14:55 PM PST 24
Finished	Feb 07 01:14:57 PM PST 24
Peak memory	205688 kb
Host	smart-a8bb6e1a-ca08-4009-b672-9a2c5344a28f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198923578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1198923578
Directory	/workspace/2.edn_csr_rw/latest

Test location	/workspace/coverage/default/2.edn_regwen.786530417
Short name	T218
Test name
Test status
Simulation time	17733163 ps
CPU time	0.9 seconds
Started	Feb 07 12:47:49 PM PST 24
Finished	Feb 07 12:47:51 PM PST 24
Peak memory	206820 kb
Host	smart-8bb2ae7d-e07d-4169-9e4c-e51c359a4aa5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=786530417 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.786530417
Directory	/workspace/2.edn_regwen/latest

Test location	/workspace/coverage/default/26.edn_intr.4267586022
Short name	T60
Test name
Test status
Simulation time	25410613 ps
CPU time	0.98 seconds
Started	Feb 07 12:48:35 PM PST 24
Finished	Feb 07 12:48:43 PM PST 24
Peak memory	215412 kb
Host	smart-4cfca1fb-8c88-4066-a924-8e18b03769af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4267586022 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.4267586022
Directory	/workspace/26.edn_intr/latest

Test location	/workspace/coverage/default/39.edn_disable_auto_req_mode.4136771416
Short name	T33
Test name
Test status
Simulation time	65495576 ps
CPU time	1.14 seconds
Started	Feb 07 12:48:54 PM PST 24
Finished	Feb 07 12:48:56 PM PST 24
Peak memory	215176 kb
Host	smart-3809e6d2-0da3-4289-b80f-9d662f7bc1bd
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136771416 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d isable_auto_req_mode.4136771416
Directory	/workspace/39.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/cover_reg_top/16.edn_tl_errors.3065116752
Short name	T125
Test name
Test status
Simulation time	442593971 ps
CPU time	3.66 seconds
Started	Feb 07 01:16:00 PM PST 24
Finished	Feb 07 01:16:04 PM PST 24
Peak memory	214116 kb
Host	smart-eff64422-1e6e-49cd-8e80-5e7cf5abd6b8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065116752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3065116752
Directory	/workspace/16.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.edn_intr_test.1489450342
Short name	T250
Test name
Test status
Simulation time	58921585 ps
CPU time	0.79 seconds
Started	Feb 07 01:14:44 PM PST 24
Finished	Feb 07 01:14:45 PM PST 24
Peak memory	205608 kb
Host	smart-eeff518f-2580-4c79-a197-052551042c8e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489450342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1489450342
Directory	/workspace/1.edn_intr_test/latest

Test location	/workspace/coverage/default/224.edn_genbits.1056641936
Short name	T31
Test name
Test status
Simulation time	107841730 ps
CPU time	1.32 seconds
Started	Feb 07 12:50:00 PM PST 24
Finished	Feb 07 12:50:04 PM PST 24
Peak memory	216900 kb
Host	smart-9ed37994-e86a-4101-9180-92d3441210e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1056641936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1056641936
Directory	/workspace/224.edn_genbits/latest

Test location	/workspace/coverage/default/85.edn_genbits.286205993
Short name	T192
Test name
Test status
Simulation time	17925550 ps
CPU time	1.04 seconds
Started	Feb 07 12:49:35 PM PST 24
Finished	Feb 07 12:49:40 PM PST 24
Peak memory	215340 kb
Host	smart-9ce06780-ccb3-4688-b6ae-48c7eaf3b5f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=286205993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.286205993
Directory	/workspace/85.edn_genbits/latest

Test location	/workspace/coverage/default/1.edn_alert.2298821331
Short name	T715
Test name
Test status
Simulation time	36659460 ps
CPU time	0.99 seconds
Started	Feb 07 12:47:48 PM PST 24
Finished	Feb 07 12:47:50 PM PST 24
Peak memory	205924 kb
Host	smart-5c530e9a-1445-4049-9fb1-0e252fb5efdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2298821331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2298821331
Directory	/workspace/1.edn_alert/latest

Test location	/workspace/coverage/default/15.edn_alert.2046464053
Short name	T98
Test name
Test status
Simulation time	34747809 ps
CPU time	1.02 seconds
Started	Feb 07 12:48:26 PM PST 24
Finished	Feb 07 12:48:36 PM PST 24
Peak memory	206000 kb
Host	smart-07945e7d-61c8-418a-9d00-2b314f5f668e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2046464053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2046464053
Directory	/workspace/15.edn_alert/latest

Test location	/workspace/coverage/default/33.edn_alert.3382575514
Short name	T910
Test name
Test status
Simulation time	23390861 ps
CPU time	1.06 seconds
Started	Feb 07 12:48:48 PM PST 24
Finished	Feb 07 12:48:50 PM PST 24
Peak memory	205984 kb
Host	smart-80dc668f-0eb5-4bdf-92fa-c3517f79495b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3382575514 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3382575514
Directory	/workspace/33.edn_alert/latest

Test location	/workspace/coverage/default/190.edn_genbits.1328095798
Short name	T38
Test name
Test status
Simulation time	49040354 ps
CPU time	1.81 seconds
Started	Feb 07 12:49:50 PM PST 24
Finished	Feb 07 12:49:53 PM PST 24
Peak memory	216816 kb
Host	smart-83ab03a5-bdc3-4e76-b450-fc8604bc563e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1328095798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1328095798
Directory	/workspace/190.edn_genbits/latest

Test location	/workspace/coverage/default/110.edn_genbits.3321302741
Short name	T540
Test name
Test status
Simulation time	36410103 ps
CPU time	1.25 seconds
Started	Feb 07 12:49:35 PM PST 24
Finished	Feb 07 12:49:39 PM PST 24
Peak memory	217696 kb
Host	smart-09742e81-1e4c-414e-ac79-4669864247e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3321302741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3321302741
Directory	/workspace/110.edn_genbits/latest

Test location	/workspace/coverage/default/1.edn_regwen.263185198
Short name	T167
Test name
Test status
Simulation time	59127467 ps
CPU time	0.85 seconds
Started	Feb 07 12:47:49 PM PST 24
Finished	Feb 07 12:47:50 PM PST 24
Peak memory	206836 kb
Host	smart-673286ea-727a-40bb-ae6d-3605ce8711e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=263185198 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.263185198
Directory	/workspace/1.edn_regwen/latest

Test location	/workspace/coverage/default/191.edn_genbits.47215651
Short name	T387
Test name
Test status
Simulation time	48282369 ps
CPU time	1.28 seconds
Started	Feb 07 12:49:46 PM PST 24
Finished	Feb 07 12:49:49 PM PST 24
Peak memory	215384 kb
Host	smart-fc4d4094-aa9f-482e-8f84-06fab4af55fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=47215651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.47215651
Directory	/workspace/191.edn_genbits/latest

Test location	/workspace/coverage/default/43.edn_genbits.4082464920
Short name	T434
Test name
Test status
Simulation time	265545190 ps
CPU time	1.49 seconds
Started	Feb 07 12:48:57 PM PST 24
Finished	Feb 07 12:49:00 PM PST 24
Peak memory	215680 kb
Host	smart-769c6b25-921b-438f-9f5f-9ec5ce1ad465
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4082464920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.4082464920
Directory	/workspace/43.edn_genbits/latest

Test location	/workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.242719831
Short name	T251
Test name
Test status
Simulation time	68478051 ps
CPU time	1.15 seconds
Started	Feb 07 01:15:05 PM PST 24
Finished	Feb 07 01:15:07 PM PST 24
Peak memory	214088 kb
Host	smart-14604ebe-2315-4df9-aae8-756d6e3f2f09
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242719831 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.242719831
Directory	/workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/146.edn_genbits.1858473450
Short name	T917
Test name
Test status
Simulation time	25611567 ps
CPU time	1.13 seconds
Started	Feb 07 12:49:46 PM PST 24
Finished	Feb 07 12:49:49 PM PST 24
Peak memory	215428 kb
Host	smart-79d32779-4fa5-49eb-a92b-1350be2c4c5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1858473450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1858473450
Directory	/workspace/146.edn_genbits/latest

Test location	/workspace/coverage/default/3.edn_regwen.3856471553
Short name	T232
Test name
Test status
Simulation time	121077197 ps
CPU time	0.88 seconds
Started	Feb 07 12:47:47 PM PST 24
Finished	Feb 07 12:47:49 PM PST 24
Peak memory	206788 kb
Host	smart-a30c3181-602d-4699-bd93-081c54c542be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3856471553 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3856471553
Directory	/workspace/3.edn_regwen/latest

Test location	/workspace/coverage/default/38.edn_disable.46500915
Short name	T102
Test name
Test status
Simulation time	29744672 ps
CPU time	0.79 seconds
Started	Feb 07 12:48:56 PM PST 24
Finished	Feb 07 12:48:58 PM PST 24
Peak memory	215020 kb
Host	smart-fc7e10d0-2ebd-48ed-8a4e-27356f08cad7
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46500915 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.46500915
Directory	/workspace/38.edn_disable/latest

Test location	/workspace/coverage/default/10.edn_alert_test.1106401515
Short name	T100
Test name
Test status
Simulation time	22976830 ps
CPU time	0.85 seconds
Started	Feb 07 12:48:07 PM PST 24
Finished	Feb 07 12:48:09 PM PST 24
Peak memory	206352 kb
Host	smart-2b0a560a-105a-4238-9904-4811dfea01f2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106401515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1106401515
Directory	/workspace/10.edn_alert_test/latest

Test location	/workspace/coverage/default/42.edn_intr.1249311172
Short name	T70
Test name
Test status
Simulation time	20565416 ps
CPU time	1.06 seconds
Started	Feb 07 12:48:56 PM PST 24
Finished	Feb 07 12:48:58 PM PST 24
Peak memory	215264 kb
Host	smart-2ab3fc5e-5b67-40b1-ae50-ce5591e652a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249311172 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1249311172
Directory	/workspace/42.edn_intr/latest

Test location	/workspace/coverage/cover_reg_top/0.edn_intr_test.2613502439
Short name	T254
Test name
Test status
Simulation time	17387313 ps
CPU time	0.95 seconds
Started	Feb 07 01:14:51 PM PST 24
Finished	Feb 07 01:14:52 PM PST 24
Peak memory	205748 kb
Host	smart-b6c3109a-f8a3-41eb-97f1-417723d658a3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613502439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2613502439
Directory	/workspace/0.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2871567486
Short name	T169
Test name
Test status
Simulation time	41978543 ps
CPU time	1.5 seconds
Started	Feb 07 01:15:22 PM PST 24
Finished	Feb 07 01:15:33 PM PST 24
Peak memory	205772 kb
Host	smart-8c36688e-5a75-462e-9be4-8fc4a2acf95e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871567486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2871567486
Directory	/workspace/5.edn_tl_intg_err/latest

Test location	/workspace/coverage/default/1.edn_stress_all_with_rand_reset.812486978
Short name	T886
Test name
Test status
Simulation time	62091407545 ps
CPU time	1611.64 seconds
Started	Feb 07 12:47:46 PM PST 24
Finished	Feb 07 01:14:38 PM PST 24
Peak memory	223904 kb
Host	smart-457de9d7-4efc-4e88-8d7f-e804ef909e27
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812486978 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.812486978
Directory	/workspace/1.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/100.edn_genbits.1253247813
Short name	T644
Test name
Test status
Simulation time	129049630 ps
CPU time	1.16 seconds
Started	Feb 07 12:49:46 PM PST 24
Finished	Feb 07 12:49:49 PM PST 24
Peak memory	215280 kb
Host	smart-dab3b9ba-104b-4111-9d8a-3186fd9a24f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1253247813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1253247813
Directory	/workspace/100.edn_genbits/latest

Test location	/workspace/coverage/default/108.edn_genbits.2979733786
Short name	T211
Test name
Test status
Simulation time	47369591 ps
CPU time	1.35 seconds
Started	Feb 07 12:49:36 PM PST 24
Finished	Feb 07 12:49:40 PM PST 24
Peak memory	216664 kb
Host	smart-6ddd9e30-aad5-4189-bb5a-228b8d11d2d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2979733786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2979733786
Directory	/workspace/108.edn_genbits/latest

Test location	/workspace/coverage/default/12.edn_alert.1132568487
Short name	T227
Test name
Test status
Simulation time	24944890 ps
CPU time	1.08 seconds
Started	Feb 07 12:48:19 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	206076 kb
Host	smart-d900646f-589a-4e95-9c79-19eab298f8e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1132568487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1132568487
Directory	/workspace/12.edn_alert/latest

Test location	/workspace/coverage/default/124.edn_genbits.3979253294
Short name	T187
Test name
Test status
Simulation time	49618319 ps
CPU time	1.36 seconds
Started	Feb 07 12:49:46 PM PST 24
Finished	Feb 07 12:49:49 PM PST 24
Peak memory	216752 kb
Host	smart-35966db2-9e83-4853-b08f-eadafa56bcfa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3979253294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3979253294
Directory	/workspace/124.edn_genbits/latest

Test location	/workspace/coverage/default/136.edn_genbits.3024832314
Short name	T88
Test name
Test status
Simulation time	63089248 ps
CPU time	1.05 seconds
Started	Feb 07 12:50:00 PM PST 24
Finished	Feb 07 12:50:03 PM PST 24
Peak memory	215476 kb
Host	smart-fb869c68-3b8a-42c4-af2b-204c17d2c597
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3024832314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3024832314
Directory	/workspace/136.edn_genbits/latest

Test location	/workspace/coverage/default/138.edn_genbits.3954773780
Short name	T742
Test name
Test status
Simulation time	141709041 ps
CPU time	1.12 seconds
Started	Feb 07 12:49:38 PM PST 24
Finished	Feb 07 12:49:42 PM PST 24
Peak memory	215388 kb
Host	smart-d7cfb47e-fe08-42e9-8873-85fa88dea483
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3954773780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3954773780
Directory	/workspace/138.edn_genbits/latest

Test location	/workspace/coverage/default/154.edn_genbits.3491597474
Short name	T198
Test name
Test status
Simulation time	29360714 ps
CPU time	1.23 seconds
Started	Feb 07 12:49:56 PM PST 24
Finished	Feb 07 12:49:58 PM PST 24
Peak memory	217564 kb
Host	smart-a7ddd90d-fd31-4c12-b9ce-a5592dc0ecb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3491597474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3491597474
Directory	/workspace/154.edn_genbits/latest

Test location	/workspace/coverage/default/221.edn_genbits.3224019048
Short name	T181
Test name
Test status
Simulation time	57237808 ps
CPU time	1.27 seconds
Started	Feb 07 12:50:07 PM PST 24
Finished	Feb 07 12:50:10 PM PST 24
Peak memory	216588 kb
Host	smart-627772e7-3447-4342-ba1e-06eff02793e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3224019048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3224019048
Directory	/workspace/221.edn_genbits/latest

Test location	/workspace/coverage/default/25.edn_alert.3196866186
Short name	T228
Test name
Test status
Simulation time	58726913 ps
CPU time	0.92 seconds
Started	Feb 07 12:48:43 PM PST 24
Finished	Feb 07 12:48:47 PM PST 24
Peak memory	205888 kb
Host	smart-c3fcc28f-aaad-4b00-8ee5-ec30f4051bdc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3196866186 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3196866186
Directory	/workspace/25.edn_alert/latest

Test location	/workspace/coverage/default/46.edn_alert.3341067857
Short name	T221
Test name
Test status
Simulation time	106971021 ps
CPU time	0.93 seconds
Started	Feb 07 12:49:16 PM PST 24
Finished	Feb 07 12:49:21 PM PST 24
Peak memory	205980 kb
Host	smart-00118ccf-feb0-43c5-a5fe-5c2cd13e5e72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3341067857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3341067857
Directory	/workspace/46.edn_alert/latest

Test location	/workspace/coverage/default/72.edn_genbits.4027120923
Short name	T195
Test name
Test status
Simulation time	66638472 ps
CPU time	1.38 seconds
Started	Feb 07 12:49:25 PM PST 24
Finished	Feb 07 12:49:28 PM PST 24
Peak memory	216900 kb
Host	smart-a7213a48-3994-48c2-9a6f-b04115ee6319
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4027120923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.4027120923
Directory	/workspace/72.edn_genbits/latest

Test location	/workspace/coverage/default/16.edn_intr.188921307
Short name	T74
Test name
Test status
Simulation time	35201370 ps
CPU time	0.77 seconds
Started	Feb 07 12:48:19 PM PST 24
Finished	Feb 07 12:48:26 PM PST 24
Peak memory	214808 kb
Host	smart-b736596c-7fbd-4cd5-8bca-7cbaad091beb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=188921307 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.188921307
Directory	/workspace/16.edn_intr/latest

Test location	/workspace/coverage/cover_reg_top/10.edn_tl_errors.2432238679
Short name	T266
Test name
Test status
Simulation time	91843065 ps
CPU time	3.57 seconds
Started	Feb 07 01:15:33 PM PST 24
Finished	Feb 07 01:15:39 PM PST 24
Peak memory	214112 kb
Host	smart-056f8538-51e5-4c19-af3e-7d6886d4f677
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432238679 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2432238679
Directory	/workspace/10.edn_tl_errors/latest

Test location	/workspace/coverage/default/0.edn_disable.367640931
Short name	T108
Test name
Test status
Simulation time	13282342 ps
CPU time	0.91 seconds
Started	Feb 07 12:47:39 PM PST 24
Finished	Feb 07 12:47:42 PM PST 24
Peak memory	215276 kb
Host	smart-d5bc8593-488a-4f42-8f98-59755a38bd4e
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367640931 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.367640931
Directory	/workspace/0.edn_disable/latest

Test location	/workspace/coverage/default/1.edn_disable.1336732665
Short name	T119
Test name
Test status
Simulation time	72345684 ps
CPU time	0.81 seconds
Started	Feb 07 12:47:51 PM PST 24
Finished	Feb 07 12:47:52 PM PST 24
Peak memory	214980 kb
Host	smart-59d531c6-f72c-4f5f-95a3-cf569bf6f5bf
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336732665 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1336732665
Directory	/workspace/1.edn_disable/latest

Test location	/workspace/coverage/default/10.edn_disable_auto_req_mode.3565274756
Short name	T101
Test name
Test status
Simulation time	46615762 ps
CPU time	1.12 seconds
Started	Feb 07 12:48:06 PM PST 24
Finished	Feb 07 12:48:08 PM PST 24
Peak memory	215312 kb
Host	smart-9c01282e-d75c-4525-a170-e117f90ce77e
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565274756 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d isable_auto_req_mode.3565274756
Directory	/workspace/10.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/13.edn_disable.1970372765
Short name	T121
Test name
Test status
Simulation time	19901334 ps
CPU time	0.85 seconds
Started	Feb 07 12:48:18 PM PST 24
Finished	Feb 07 12:48:25 PM PST 24
Peak memory	214988 kb
Host	smart-822138bf-37b5-4387-a71a-1b6a1917801c
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970372765 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1970372765
Directory	/workspace/13.edn_disable/latest

Test location	/workspace/coverage/default/22.edn_disable.2700712559
Short name	T104
Test name
Test status
Simulation time	12656056 ps
CPU time	0.91 seconds
Started	Feb 07 12:48:37 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	215052 kb
Host	smart-0748f22b-79fe-41b9-995f-9f94c69fe622
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700712559 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2700712559
Directory	/workspace/22.edn_disable/latest

Test location	/workspace/coverage/default/23.edn_disable.3310464759
Short name	T114
Test name
Test status
Simulation time	20564771 ps
CPU time	0.87 seconds
Started	Feb 07 12:48:28 PM PST 24
Finished	Feb 07 12:48:37 PM PST 24
Peak memory	215040 kb
Host	smart-1c3bc83b-fbdd-4a16-8e05-a54b0d040b59
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310464759 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3310464759
Directory	/workspace/23.edn_disable/latest

Test location	/workspace/coverage/default/3.edn_disable.1651517659
Short name	T843
Test name
Test status
Simulation time	18448137 ps
CPU time	0.83 seconds
Started	Feb 07 12:47:49 PM PST 24
Finished	Feb 07 12:47:51 PM PST 24
Peak memory	215060 kb
Host	smart-60c84047-ac0e-44d9-af3b-ebdd3e0aa0a9
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651517659 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1651517659
Directory	/workspace/3.edn_disable/latest

Test location	/workspace/coverage/default/0.edn_err.2727594599
Short name	T444
Test name
Test status
Simulation time	20807280 ps
CPU time	1.08 seconds
Started	Feb 07 12:47:55 PM PST 24
Finished	Feb 07 12:47:57 PM PST 24
Peak memory	215608 kb
Host	smart-e4195dbd-d605-406d-b3b0-724acba1f56d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2727594599 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2727594599
Directory	/workspace/0.edn_err/latest

Test location	/workspace/coverage/default/161.edn_genbits.1319750147
Short name	T11
Test name
Test status
Simulation time	132341395 ps
CPU time	1.39 seconds
Started	Feb 07 12:49:56 PM PST 24
Finished	Feb 07 12:49:58 PM PST 24
Peak memory	217736 kb
Host	smart-2a0a90c5-9d68-4e0e-b540-067ee1e8c273
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1319750147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1319750147
Directory	/workspace/161.edn_genbits/latest

Test location	/workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1828493285
Short name	T161
Test name
Test status
Simulation time	33762926 ps
CPU time	1.39 seconds
Started	Feb 07 01:14:46 PM PST 24
Finished	Feb 07 01:14:48 PM PST 24
Peak memory	205820 kb
Host	smart-1d57bb60-6a03-4c0e-8b27-eadf18181147
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828493285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1828493285
Directory	/workspace/0.edn_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1169888634
Short name	T241
Test name
Test status
Simulation time	175226159 ps
CPU time	5.08 seconds
Started	Feb 07 01:14:47 PM PST 24
Finished	Feb 07 01:14:53 PM PST 24
Peak memory	205740 kb
Host	smart-fa9a4964-76af-4b81-9fa6-03141b51a73a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169888634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1169888634
Directory	/workspace/0.edn_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.133809745
Short name	T21
Test name
Test status
Simulation time	59560564 ps
CPU time	0.88 seconds
Started	Feb 07 01:14:43 PM PST 24
Finished	Feb 07 01:14:44 PM PST 24
Peak memory	205812 kb
Host	smart-0a356a51-53c2-4d4c-ad76-665bce88132c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133809745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.133809745
Directory	/workspace/0.edn_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2855410809
Short name	T315
Test name
Test status
Simulation time	39902250 ps
CPU time	1.54 seconds
Started	Feb 07 01:14:52 PM PST 24
Finished	Feb 07 01:14:55 PM PST 24
Peak memory	214120 kb
Host	smart-a5533294-82ac-4054-bc57-824ace32de9f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855410809 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2855410809
Directory	/workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.edn_csr_rw.2004655050
Short name	T19
Test name
Test status
Simulation time	26257477 ps
CPU time	0.91 seconds
Started	Feb 07 01:14:44 PM PST 24
Finished	Feb 07 01:14:45 PM PST 24
Peak memory	205812 kb
Host	smart-5eb00012-74b7-4c82-acdb-7f603b844638
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004655050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2004655050
Directory	/workspace/0.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1562014372
Short name	T132
Test name
Test status
Simulation time	23857413 ps
CPU time	1.1 seconds
Started	Feb 07 01:14:52 PM PST 24
Finished	Feb 07 01:14:53 PM PST 24
Peak memory	205908 kb
Host	smart-a47cf33a-9fd5-4794-a06e-968cd8689f4d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562014372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou tstanding.1562014372
Directory	/workspace/0.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.edn_tl_errors.2797562446
Short name	T286
Test name
Test status
Simulation time	673169635 ps
CPU time	3.18 seconds
Started	Feb 07 01:14:46 PM PST 24
Finished	Feb 07 01:14:49 PM PST 24
Peak memory	216868 kb
Host	smart-60edfec1-fa50-4822-8e33-f5a71b59e446
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797562446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2797562446
Directory	/workspace/0.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2548650226
Short name	T127
Test name
Test status
Simulation time	279664085 ps
CPU time	1.53 seconds
Started	Feb 07 01:14:45 PM PST 24
Finished	Feb 07 01:14:47 PM PST 24
Peak memory	205940 kb
Host	smart-044d63d6-e399-4ef9-bce5-ce1f64d72f93
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548650226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2548650226
Directory	/workspace/0.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3046208993
Short name	T242
Test name
Test status
Simulation time	15067565 ps
CPU time	0.99 seconds
Started	Feb 07 01:14:48 PM PST 24
Finished	Feb 07 01:14:49 PM PST 24
Peak memory	205824 kb
Host	smart-01ef3d46-a043-4b87-a01f-47426e3f222d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046208993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3046208993
Directory	/workspace/1.edn_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.846124891
Short name	T342
Test name
Test status
Simulation time	518215770 ps
CPU time	6.91 seconds
Started	Feb 07 01:14:49 PM PST 24
Finished	Feb 07 01:14:57 PM PST 24
Peak memory	205756 kb
Host	smart-61cb98fe-9e39-4c41-80c7-fdadbb980538
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846124891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.846124891
Directory	/workspace/1.edn_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1048332262
Short name	T157
Test name
Test status
Simulation time	43118290 ps
CPU time	0.86 seconds
Started	Feb 07 01:14:44 PM PST 24
Finished	Feb 07 01:14:45 PM PST 24
Peak memory	205724 kb
Host	smart-7b91545b-e717-470b-bb24-c32f0902f3f4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048332262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1048332262
Directory	/workspace/1.edn_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1555628775
Short name	T317
Test name
Test status
Simulation time	46917089 ps
CPU time	1.7 seconds
Started	Feb 07 01:15:02 PM PST 24
Finished	Feb 07 01:15:04 PM PST 24
Peak memory	214120 kb
Host	smart-4cc655c5-23e4-46e8-8014-cf4ac6110478
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555628775 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1555628775
Directory	/workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.483451860
Short name	T247
Test name
Test status
Simulation time	30603223 ps
CPU time	1.11 seconds
Started	Feb 07 01:14:49 PM PST 24
Finished	Feb 07 01:14:50 PM PST 24
Peak memory	205892 kb
Host	smart-81a975af-3022-4080-90d4-a253100be697
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483451860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out standing.483451860
Directory	/workspace/1.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.edn_tl_errors.110112657
Short name	T324
Test name
Test status
Simulation time	60739402 ps
CPU time	2.52 seconds
Started	Feb 07 01:14:44 PM PST 24
Finished	Feb 07 01:14:47 PM PST 24
Peak memory	214120 kb
Host	smart-ea92317b-ef99-434b-aa24-581b9f476c2e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110112657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.110112657
Directory	/workspace/1.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2492344277
Short name	T275
Test name
Test status
Simulation time	90342600 ps
CPU time	2.55 seconds
Started	Feb 07 01:14:46 PM PST 24
Finished	Feb 07 01:14:49 PM PST 24
Peak memory	205880 kb
Host	smart-041fd0b1-5d3d-41c2-b369-c8034aba07be
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492344277 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2492344277
Directory	/workspace/1.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.454016046
Short name	T269
Test name
Test status
Simulation time	40907718 ps
CPU time	1.22 seconds
Started	Feb 07 01:15:34 PM PST 24
Finished	Feb 07 01:15:37 PM PST 24
Peak memory	214084 kb
Host	smart-f869cf7f-3a46-4b78-b4d6-7bbdc62bcb10
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454016046 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.454016046
Directory	/workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.edn_csr_rw.474253131
Short name	T143
Test name
Test status
Simulation time	14700492 ps
CPU time	0.91 seconds
Started	Feb 07 01:15:32 PM PST 24
Finished	Feb 07 01:15:36 PM PST 24
Peak memory	205824 kb
Host	smart-bc8ab54c-bd20-4abe-b5a0-76e70f153ac3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474253131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.474253131
Directory	/workspace/10.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.edn_intr_test.4040611963
Short name	T147
Test name
Test status
Simulation time	21419529 ps
CPU time	0.8 seconds
Started	Feb 07 01:15:33 PM PST 24
Finished	Feb 07 01:15:36 PM PST 24
Peak memory	205748 kb
Host	smart-485c4d15-7f63-4b17-ab26-646c3055b0f6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040611963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.4040611963
Directory	/workspace/10.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3965479616
Short name	T163
Test name
Test status
Simulation time	39147541 ps
CPU time	0.93 seconds
Started	Feb 07 01:15:38 PM PST 24
Finished	Feb 07 01:15:40 PM PST 24
Peak memory	205836 kb
Host	smart-63fb9374-ae3a-416c-909a-07fc5e1b05cf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965479616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o utstanding.3965479616
Directory	/workspace/10.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2659067871
Short name	T326
Test name
Test status
Simulation time	236782526 ps
CPU time	2.08 seconds
Started	Feb 07 01:15:33 PM PST 24
Finished	Feb 07 01:15:37 PM PST 24
Peak memory	205896 kb
Host	smart-d15e119f-003b-43e1-91f0-bce4399340f4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659067871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2659067871
Directory	/workspace/10.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2455944197
Short name	T303
Test name
Test status
Simulation time	154427924 ps
CPU time	1.14 seconds
Started	Feb 07 01:15:33 PM PST 24
Finished	Feb 07 01:15:36 PM PST 24
Peak memory	222348 kb
Host	smart-425d5e5d-cc30-4966-820c-f07682e43fd5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455944197 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2455944197
Directory	/workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.edn_csr_rw.3655623575
Short name	T148
Test name
Test status
Simulation time	63588434 ps
CPU time	0.78 seconds
Started	Feb 07 01:15:33 PM PST 24
Finished	Feb 07 01:15:36 PM PST 24
Peak memory	205668 kb
Host	smart-0533bd34-2334-453e-889d-0dbcd0ba715d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655623575 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3655623575
Directory	/workspace/11.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.edn_intr_test.21264770
Short name	T276
Test name
Test status
Simulation time	16144949 ps
CPU time	0.9 seconds
Started	Feb 07 01:15:36 PM PST 24
Finished	Feb 07 01:15:38 PM PST 24
Peak memory	205704 kb
Host	smart-1af42acc-450a-409b-abec-1b141e5e3349
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21264770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.21264770
Directory	/workspace/11.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.482330885
Short name	T135
Test name
Test status
Simulation time	35513349 ps
CPU time	1.42 seconds
Started	Feb 07 01:15:36 PM PST 24
Finished	Feb 07 01:15:38 PM PST 24
Peak memory	205816 kb
Host	smart-b651967e-20a3-4757-a66c-bf6aedba0958
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482330885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_ou tstanding.482330885
Directory	/workspace/11.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.edn_tl_errors.602474322
Short name	T151
Test name
Test status
Simulation time	214047598 ps
CPU time	4.14 seconds
Started	Feb 07 01:15:32 PM PST 24
Finished	Feb 07 01:15:39 PM PST 24
Peak memory	214092 kb
Host	smart-05a5d1e8-b1e2-469e-ba01-2e4c7d33b8f1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602474322 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.602474322
Directory	/workspace/11.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1726062277
Short name	T332
Test name
Test status
Simulation time	311586129 ps
CPU time	2.36 seconds
Started	Feb 07 01:15:33 PM PST 24
Finished	Feb 07 01:15:38 PM PST 24
Peak memory	205884 kb
Host	smart-3279e082-47f8-4447-867d-8e43f96b8300
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726062277 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1726062277
Directory	/workspace/11.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.517921851
Short name	T299
Test name
Test status
Simulation time	30056300 ps
CPU time	1.26 seconds
Started	Feb 07 01:15:35 PM PST 24
Finished	Feb 07 01:15:37 PM PST 24
Peak memory	214172 kb
Host	smart-a2ef8e7a-07a4-4abb-b70f-83cb94f84352
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517921851 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.517921851
Directory	/workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.edn_csr_rw.3621394404
Short name	T144
Test name
Test status
Simulation time	19613181 ps
CPU time	0.81 seconds
Started	Feb 07 01:15:33 PM PST 24
Finished	Feb 07 01:15:36 PM PST 24
Peak memory	205612 kb
Host	smart-5d9d1ffa-3da1-453d-8b87-ce4b23d1b898
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621394404 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3621394404
Directory	/workspace/12.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.edn_intr_test.1299479958
Short name	T243
Test name
Test status
Simulation time	42139279 ps
CPU time	0.8 seconds
Started	Feb 07 01:15:36 PM PST 24
Finished	Feb 07 01:15:37 PM PST 24
Peak memory	205608 kb
Host	smart-47fdefe3-440f-4fd7-bf82-e9b5bd2c8645
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299479958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1299479958
Directory	/workspace/12.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3471285673
Short name	T44
Test name
Test status
Simulation time	21672134 ps
CPU time	0.94 seconds
Started	Feb 07 01:15:32 PM PST 24
Finished	Feb 07 01:15:36 PM PST 24
Peak memory	205924 kb
Host	smart-351df176-8598-4c28-8f8c-418d9157e138
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471285673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o utstanding.3471285673
Directory	/workspace/12.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.edn_tl_errors.2465554268
Short name	T307
Test name
Test status
Simulation time	87757484 ps
CPU time	2.27 seconds
Started	Feb 07 01:15:35 PM PST 24
Finished	Feb 07 01:15:38 PM PST 24
Peak memory	222320 kb
Host	smart-17fda23c-28c6-4804-83e1-ae17efd2bfbe
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465554268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2465554268
Directory	/workspace/12.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3223550898
Short name	T130
Test name
Test status
Simulation time	194908267 ps
CPU time	1.48 seconds
Started	Feb 07 01:15:34 PM PST 24
Finished	Feb 07 01:15:38 PM PST 24
Peak memory	205920 kb
Host	smart-16f0866a-d62c-4652-bebd-35e025d9e5a1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223550898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3223550898
Directory	/workspace/12.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2527012968
Short name	T964
Test name
Test status
Simulation time	17524578 ps
CPU time	0.93 seconds
Started	Feb 07 01:16:01 PM PST 24
Finished	Feb 07 01:16:02 PM PST 24
Peak memory	205896 kb
Host	smart-c9d3425e-65c5-4224-84aa-4661049d0745
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527012968 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2527012968
Directory	/workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.edn_csr_rw.526475610
Short name	T45
Test name
Test status
Simulation time	41940426 ps
CPU time	0.85 seconds
Started	Feb 07 01:15:54 PM PST 24
Finished	Feb 07 01:15:56 PM PST 24
Peak memory	205632 kb
Host	smart-b5da6301-44a5-461e-8e9a-def2a9d3d2d7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526475610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.526475610
Directory	/workspace/13.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.edn_intr_test.3876865428
Short name	T331
Test name
Test status
Simulation time	79284112 ps
CPU time	0.82 seconds
Started	Feb 07 01:16:00 PM PST 24
Finished	Feb 07 01:16:02 PM PST 24
Peak memory	205760 kb
Host	smart-1ccef9f8-e218-4651-98f1-db470d814dc9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876865428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3876865428
Directory	/workspace/13.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.315434676
Short name	T338
Test name
Test status
Simulation time	110951907 ps
CPU time	1.1 seconds
Started	Feb 07 01:16:02 PM PST 24
Finished	Feb 07 01:16:04 PM PST 24
Peak memory	205840 kb
Host	smart-9dc203be-8601-4561-83fe-427ca7ef7f4c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315434676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou tstanding.315434676
Directory	/workspace/13.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.edn_tl_errors.1803923713
Short name	T138
Test name
Test status
Simulation time	73177887 ps
CPU time	2.51 seconds
Started	Feb 07 01:15:34 PM PST 24
Finished	Feb 07 01:15:39 PM PST 24
Peak memory	214148 kb
Host	smart-6d429d76-43b7-4a5b-a842-13ae0f9e1397
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803923713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1803923713
Directory	/workspace/13.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2363602437
Short name	T150
Test name
Test status
Simulation time	60034512 ps
CPU time	1.74 seconds
Started	Feb 07 01:15:33 PM PST 24
Finished	Feb 07 01:15:37 PM PST 24
Peak memory	205884 kb
Host	smart-cae4776a-e234-4a34-bc95-78902c44e9da
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363602437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2363602437
Directory	/workspace/13.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1276596774
Short name	T341
Test name
Test status
Simulation time	29918922 ps
CPU time	0.95 seconds
Started	Feb 07 01:15:54 PM PST 24
Finished	Feb 07 01:15:55 PM PST 24
Peak memory	205996 kb
Host	smart-2402ddb6-b4ce-4a18-8a4b-6d3e1de79173
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276596774 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1276596774
Directory	/workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.edn_csr_rw.2143927548
Short name	T164
Test name
Test status
Simulation time	21506513 ps
CPU time	0.85 seconds
Started	Feb 07 01:15:54 PM PST 24
Finished	Feb 07 01:15:56 PM PST 24
Peak memory	205772 kb
Host	smart-48e937fc-63bc-4d64-9a9f-aa0fae01dc83
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143927548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2143927548
Directory	/workspace/14.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.edn_intr_test.2482796372
Short name	T27
Test name
Test status
Simulation time	154651137 ps
CPU time	0.95 seconds
Started	Feb 07 01:15:56 PM PST 24
Finished	Feb 07 01:15:58 PM PST 24
Peak memory	205660 kb
Host	smart-a3fbbf73-8f8c-4d06-a0ef-371e2edf94b2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482796372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2482796372
Directory	/workspace/14.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2573391517
Short name	T260
Test name
Test status
Simulation time	18586679 ps
CPU time	1.1 seconds
Started	Feb 07 01:15:54 PM PST 24
Finished	Feb 07 01:15:56 PM PST 24
Peak memory	205892 kb
Host	smart-94d63710-dfaf-47e5-bcd4-08bf4d8f6e7b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573391517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o utstanding.2573391517
Directory	/workspace/14.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.edn_tl_errors.3707825073
Short name	T279
Test name
Test status
Simulation time	122923929 ps
CPU time	2.37 seconds
Started	Feb 07 01:15:57 PM PST 24
Finished	Feb 07 01:16:01 PM PST 24
Peak memory	214188 kb
Host	smart-09c50310-9c6e-43b6-b8be-f3b5128b516d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707825073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3707825073
Directory	/workspace/14.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.edn_tl_intg_err.593620054
Short name	T336
Test name
Test status
Simulation time	160253667 ps
CPU time	3.51 seconds
Started	Feb 07 01:15:57 PM PST 24
Finished	Feb 07 01:16:01 PM PST 24
Peak memory	205792 kb
Host	smart-913b417e-b131-4816-a94b-340f52c28831
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593620054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.593620054
Directory	/workspace/14.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2906583066
Short name	T296
Test name
Test status
Simulation time	52026973 ps
CPU time	1.32 seconds
Started	Feb 07 01:15:54 PM PST 24
Finished	Feb 07 01:15:56 PM PST 24
Peak memory	214164 kb
Host	smart-a52789f1-aff4-4ff5-a787-bd202dc01ed9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906583066 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2906583066
Directory	/workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.edn_csr_rw.108238456
Short name	T244
Test name
Test status
Simulation time	14572216 ps
CPU time	0.87 seconds
Started	Feb 07 01:16:01 PM PST 24
Finished	Feb 07 01:16:04 PM PST 24
Peak memory	205740 kb
Host	smart-4400bcd8-0944-4628-8b87-3082e075ce52
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108238456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.108238456
Directory	/workspace/15.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.edn_intr_test.3194542759
Short name	T61
Test name
Test status
Simulation time	17976394 ps
CPU time	0.85 seconds
Started	Feb 07 01:16:01 PM PST 24
Finished	Feb 07 01:16:03 PM PST 24
Peak memory	205712 kb
Host	smart-f1a229d7-002f-498b-b39a-b28d421da813
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194542759 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3194542759
Directory	/workspace/15.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.336157230
Short name	T253
Test name
Test status
Simulation time	52709762 ps
CPU time	1.28 seconds
Started	Feb 07 01:16:01 PM PST 24
Finished	Feb 07 01:16:04 PM PST 24
Peak memory	205900 kb
Host	smart-8dbc958f-e5f4-4a02-aa0f-15803e893777
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336157230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou tstanding.336157230
Directory	/workspace/15.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.edn_tl_errors.762037161
Short name	T306
Test name
Test status
Simulation time	880383933 ps
CPU time	4.39 seconds
Started	Feb 07 01:15:55 PM PST 24
Finished	Feb 07 01:16:00 PM PST 24
Peak memory	214120 kb
Host	smart-3b38d031-6b4f-4add-b62f-573b0cea09cf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762037161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.762037161
Directory	/workspace/15.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.edn_tl_intg_err.539980028
Short name	T272
Test name
Test status
Simulation time	350821053 ps
CPU time	2.73 seconds
Started	Feb 07 01:15:55 PM PST 24
Finished	Feb 07 01:15:58 PM PST 24
Peak memory	205888 kb
Host	smart-8b0d8aeb-5b52-4d2d-85fb-be4a033ef79c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539980028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.539980028
Directory	/workspace/15.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1084605177
Short name	T308
Test name
Test status
Simulation time	30012061 ps
CPU time	1.4 seconds
Started	Feb 07 01:15:55 PM PST 24
Finished	Feb 07 01:15:58 PM PST 24
Peak memory	214108 kb
Host	smart-1fcff819-b3ab-4f85-81bc-cf1debfea18e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084605177 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1084605177
Directory	/workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.edn_csr_rw.496565661
Short name	T159
Test name
Test status
Simulation time	35057736 ps
CPU time	0.82 seconds
Started	Feb 07 01:16:01 PM PST 24
Finished	Feb 07 01:16:03 PM PST 24
Peak memory	205808 kb
Host	smart-e623a32a-4945-483c-b28e-4b573ab0eba6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496565661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.496565661
Directory	/workspace/16.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.edn_intr_test.3121113404
Short name	T248
Test name
Test status
Simulation time	52235303 ps
CPU time	1 seconds
Started	Feb 07 01:16:02 PM PST 24
Finished	Feb 07 01:16:04 PM PST 24
Peak memory	205580 kb
Host	smart-cd6d00db-8ff2-4ed6-bb0b-1a5d4d91938f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121113404 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3121113404
Directory	/workspace/16.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.415045418
Short name	T46
Test name
Test status
Simulation time	32763242 ps
CPU time	1.16 seconds
Started	Feb 07 01:16:01 PM PST 24
Finished	Feb 07 01:16:04 PM PST 24
Peak memory	205860 kb
Host	smart-df311b9e-60d8-44a9-aa8c-aa5022c10cb4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415045418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_ou tstanding.415045418
Directory	/workspace/16.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3132857042
Short name	T152
Test name
Test status
Simulation time	162685511 ps
CPU time	1.52 seconds
Started	Feb 07 01:16:00 PM PST 24
Finished	Feb 07 01:16:02 PM PST 24
Peak memory	205820 kb
Host	smart-15f035ef-0ec7-45d0-8f75-06b7605ec05d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132857042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3132857042
Directory	/workspace/16.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2610778121
Short name	T312
Test name
Test status
Simulation time	159543496 ps
CPU time	1.47 seconds
Started	Feb 07 01:16:08 PM PST 24
Finished	Feb 07 01:16:10 PM PST 24
Peak memory	214124 kb
Host	smart-196ea39a-f4f4-40e2-95f0-a8b7f784f596
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610778121 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2610778121
Directory	/workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.edn_csr_rw.1569261010
Short name	T156
Test name
Test status
Simulation time	22321828 ps
CPU time	0.86 seconds
Started	Feb 07 01:16:02 PM PST 24
Finished	Feb 07 01:16:03 PM PST 24
Peak memory	205800 kb
Host	smart-fab580b7-30ea-452e-9988-175d9111cc89
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569261010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1569261010
Directory	/workspace/17.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.edn_intr_test.130790228
Short name	T309
Test name
Test status
Simulation time	61713862 ps
CPU time	0.82 seconds
Started	Feb 07 01:15:56 PM PST 24
Finished	Feb 07 01:15:58 PM PST 24
Peak memory	205692 kb
Host	smart-ddb01b3b-13fd-4dc6-9615-ece215ddddb0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130790228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.130790228
Directory	/workspace/17.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1473270745
Short name	T327
Test name
Test status
Simulation time	68249122 ps
CPU time	1.18 seconds
Started	Feb 07 01:16:02 PM PST 24
Finished	Feb 07 01:16:04 PM PST 24
Peak memory	205852 kb
Host	smart-e28aa4f6-8182-4650-9c38-3e67a847b23f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473270745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o utstanding.1473270745
Directory	/workspace/17.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.edn_tl_errors.3853754730
Short name	T129
Test name
Test status
Simulation time	144629386 ps
CPU time	2.71 seconds
Started	Feb 07 01:15:56 PM PST 24
Finished	Feb 07 01:15:59 PM PST 24
Peak memory	214184 kb
Host	smart-1910d43c-4d61-4031-b2b6-356573b8754c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853754730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3853754730
Directory	/workspace/17.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.edn_tl_intg_err.749037482
Short name	T314
Test name
Test status
Simulation time	94496390 ps
CPU time	1.67 seconds
Started	Feb 07 01:15:55 PM PST 24
Finished	Feb 07 01:15:58 PM PST 24
Peak memory	205880 kb
Host	smart-379c0fb4-87a0-44f5-bbce-362d848db047
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749037482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.749037482
Directory	/workspace/17.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2030934022
Short name	T133
Test name
Test status
Simulation time	114599100 ps
CPU time	0.97 seconds
Started	Feb 07 01:16:12 PM PST 24
Finished	Feb 07 01:16:14 PM PST 24
Peak memory	205940 kb
Host	smart-52dd731f-6ad9-4c67-9cd7-2e4787a2d601
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030934022 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2030934022
Directory	/workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.edn_csr_rw.1936500321
Short name	T158
Test name
Test status
Simulation time	15159339 ps
CPU time	0.99 seconds
Started	Feb 07 01:16:06 PM PST 24
Finished	Feb 07 01:16:08 PM PST 24
Peak memory	205804 kb
Host	smart-95133d81-ca63-41c6-b732-ebb77c384fc3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936500321 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1936500321
Directory	/workspace/18.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.edn_intr_test.1743934998
Short name	T311
Test name
Test status
Simulation time	14908841 ps
CPU time	0.88 seconds
Started	Feb 07 01:16:11 PM PST 24
Finished	Feb 07 01:16:12 PM PST 24
Peak memory	205744 kb
Host	smart-7489e78c-3b0d-4bba-aeb8-32263db27674
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743934998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1743934998
Directory	/workspace/18.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.401765156
Short name	T277
Test name
Test status
Simulation time	44453866 ps
CPU time	1.06 seconds
Started	Feb 07 01:16:09 PM PST 24
Finished	Feb 07 01:16:11 PM PST 24
Peak memory	205932 kb
Host	smart-29f719bf-0ede-4cf9-aba8-0c622000fba3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401765156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou tstanding.401765156
Directory	/workspace/18.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.edn_tl_errors.1248659308
Short name	T267
Test name
Test status
Simulation time	32874429 ps
CPU time	2.16 seconds
Started	Feb 07 01:16:12 PM PST 24
Finished	Feb 07 01:16:15 PM PST 24
Peak memory	214200 kb
Host	smart-127a497b-ce12-48e9-8094-59f1d977881f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248659308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1248659308
Directory	/workspace/18.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2069079435
Short name	T270
Test name
Test status
Simulation time	150923679 ps
CPU time	1.69 seconds
Started	Feb 07 01:16:06 PM PST 24
Finished	Feb 07 01:16:09 PM PST 24
Peak memory	205896 kb
Host	smart-84b2282b-0715-4036-9137-9a994af5ae5e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069079435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2069079435
Directory	/workspace/18.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2926221337
Short name	T153
Test name
Test status
Simulation time	42115318 ps
CPU time	1.49 seconds
Started	Feb 07 01:16:10 PM PST 24
Finished	Feb 07 01:16:13 PM PST 24
Peak memory	217800 kb
Host	smart-b0c30f1a-22fa-4092-882e-bc1841df46dc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926221337 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2926221337
Directory	/workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.edn_csr_rw.3143977795
Short name	T245
Test name
Test status
Simulation time	15605528 ps
CPU time	0.9 seconds
Started	Feb 07 01:16:08 PM PST 24
Finished	Feb 07 01:16:09 PM PST 24
Peak memory	205800 kb
Host	smart-9845d259-26e6-4499-9b63-5a8d3a001e1a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143977795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3143977795
Directory	/workspace/19.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.edn_intr_test.1192829913
Short name	T18
Test name
Test status
Simulation time	15336187 ps
CPU time	0.89 seconds
Started	Feb 07 01:16:11 PM PST 24
Finished	Feb 07 01:16:13 PM PST 24
Peak memory	205752 kb
Host	smart-38943e53-1360-499e-80ae-dfed3e7a3748
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192829913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1192829913
Directory	/workspace/19.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3233959192
Short name	T264
Test name
Test status
Simulation time	17663483 ps
CPU time	1.12 seconds
Started	Feb 07 01:16:08 PM PST 24
Finished	Feb 07 01:16:10 PM PST 24
Peak memory	205924 kb
Host	smart-8c6308e5-1140-4d7b-b384-5e2832003e3c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233959192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o utstanding.3233959192
Directory	/workspace/19.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.edn_tl_errors.2560908191
Short name	T124
Test name
Test status
Simulation time	90264036 ps
CPU time	3.3 seconds
Started	Feb 07 01:16:08 PM PST 24
Finished	Feb 07 01:16:12 PM PST 24
Peak memory	214192 kb
Host	smart-6be6622f-6c36-4f40-b4da-abb6fcae59b8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560908191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2560908191
Directory	/workspace/19.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3613518742
Short name	T128
Test name
Test status
Simulation time	502402451 ps
CPU time	2.69 seconds
Started	Feb 07 01:16:10 PM PST 24
Finished	Feb 07 01:16:13 PM PST 24
Peak memory	205936 kb
Host	smart-b211ba45-0145-49dd-8d1b-9d0481c0d031
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613518742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3613518742
Directory	/workspace/19.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1921839536
Short name	T139
Test name
Test status
Simulation time	67092921 ps
CPU time	1.48 seconds
Started	Feb 07 01:15:05 PM PST 24
Finished	Feb 07 01:15:07 PM PST 24
Peak memory	205856 kb
Host	smart-1af756ad-bff9-45bd-920b-b5b0222c024d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921839536 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1921839536
Directory	/workspace/2.edn_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3591030142
Short name	T313
Test name
Test status
Simulation time	997439605 ps
CPU time	6.62 seconds
Started	Feb 07 01:15:07 PM PST 24
Finished	Feb 07 01:15:14 PM PST 24
Peak memory	205708 kb
Host	smart-35e6c729-e078-4ed8-9caf-5165ada390b8
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591030142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3591030142
Directory	/workspace/2.edn_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3517103432
Short name	T288
Test name
Test status
Simulation time	44612438 ps
CPU time	0.82 seconds
Started	Feb 07 01:14:56 PM PST 24
Finished	Feb 07 01:14:58 PM PST 24
Peak memory	205644 kb
Host	smart-37c55531-1717-4c15-8e7b-a15e0463ab2b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517103432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3517103432
Directory	/workspace/2.edn_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.edn_intr_test.2564903997
Short name	T257
Test name
Test status
Simulation time	18579163 ps
CPU time	0.83 seconds
Started	Feb 07 01:15:06 PM PST 24
Finished	Feb 07 01:15:07 PM PST 24
Peak memory	205760 kb
Host	smart-b6da0c2a-1285-4192-8e27-b498b0d8a5df
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564903997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2564903997
Directory	/workspace/2.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.329724820
Short name	T278
Test name
Test status
Simulation time	77674771 ps
CPU time	1.04 seconds
Started	Feb 07 01:14:59 PM PST 24
Finished	Feb 07 01:15:00 PM PST 24
Peak memory	205840 kb
Host	smart-34bf8e97-76a5-4626-a656-7d61e2e20c04
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329724820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_out standing.329724820
Directory	/workspace/2.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.edn_tl_errors.1851656745
Short name	T301
Test name
Test status
Simulation time	100942123 ps
CPU time	3.54 seconds
Started	Feb 07 01:15:08 PM PST 24
Finished	Feb 07 01:15:12 PM PST 24
Peak memory	214200 kb
Host	smart-c8af5cad-a413-4d47-8cdb-9f1467919d91
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851656745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1851656745
Directory	/workspace/2.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1087914375
Short name	T22
Test name
Test status
Simulation time	293896676 ps
CPU time	2.35 seconds
Started	Feb 07 01:15:06 PM PST 24
Finished	Feb 07 01:15:09 PM PST 24
Peak memory	205904 kb
Host	smart-54b4ea92-0191-4140-9825-0ac1d3d71d2f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087914375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1087914375
Directory	/workspace/2.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.edn_intr_test.1828636769
Short name	T274
Test name
Test status
Simulation time	52883752 ps
CPU time	0.91 seconds
Started	Feb 07 01:16:11 PM PST 24
Finished	Feb 07 01:16:12 PM PST 24
Peak memory	205764 kb
Host	smart-a9050d29-3de1-495c-be21-2800dc1f69ca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828636769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1828636769
Directory	/workspace/20.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.edn_intr_test.2634277698
Short name	T149
Test name
Test status
Simulation time	42119572 ps
CPU time	0.93 seconds
Started	Feb 07 01:16:13 PM PST 24
Finished	Feb 07 01:16:15 PM PST 24
Peak memory	205656 kb
Host	smart-db0d2a73-5317-4e4a-a9b0-d129e1d8e8f6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634277698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2634277698
Directory	/workspace/21.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.edn_intr_test.101757400
Short name	T256
Test name
Test status
Simulation time	43198176 ps
CPU time	0.79 seconds
Started	Feb 07 01:16:12 PM PST 24
Finished	Feb 07 01:16:13 PM PST 24
Peak memory	205588 kb
Host	smart-66594aa0-5e3b-489f-8667-f19eae5e8391
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101757400 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.101757400
Directory	/workspace/22.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.edn_intr_test.2765038299
Short name	T295
Test name
Test status
Simulation time	22242270 ps
CPU time	0.83 seconds
Started	Feb 07 01:16:12 PM PST 24
Finished	Feb 07 01:16:13 PM PST 24
Peak memory	205732 kb
Host	smart-012d401f-3407-4579-9aaf-f25e995a1943
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765038299 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2765038299
Directory	/workspace/23.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.edn_intr_test.4209040072
Short name	T24
Test name
Test status
Simulation time	32217173 ps
CPU time	0.95 seconds
Started	Feb 07 01:16:10 PM PST 24
Finished	Feb 07 01:16:12 PM PST 24
Peak memory	205744 kb
Host	smart-f717080a-bd5b-4dda-9728-c749fa3fd1dc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209040072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.4209040072
Directory	/workspace/24.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.edn_intr_test.164190079
Short name	T252
Test name
Test status
Simulation time	17365337 ps
CPU time	0.88 seconds
Started	Feb 07 01:16:11 PM PST 24
Finished	Feb 07 01:16:12 PM PST 24
Peak memory	205756 kb
Host	smart-a5c1a615-7e9f-40df-bb5d-e4d3d342c6b2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164190079 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.164190079
Directory	/workspace/25.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.edn_intr_test.1619906795
Short name	T294
Test name
Test status
Simulation time	66618533 ps
CPU time	0.84 seconds
Started	Feb 07 01:16:42 PM PST 24
Finished	Feb 07 01:16:43 PM PST 24
Peak memory	205764 kb
Host	smart-5972359a-955b-4b07-8e51-7d71aadbc323
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619906795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1619906795
Directory	/workspace/26.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.edn_intr_test.345601687
Short name	T268
Test name
Test status
Simulation time	21020187 ps
CPU time	0.83 seconds
Started	Feb 07 01:16:09 PM PST 24
Finished	Feb 07 01:16:11 PM PST 24
Peak memory	205712 kb
Host	smart-39c6a035-cd38-4633-b3de-84d3f0c5b671
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345601687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.345601687
Directory	/workspace/27.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.edn_intr_test.554189966
Short name	T298
Test name
Test status
Simulation time	36719278 ps
CPU time	0.78 seconds
Started	Feb 07 01:16:10 PM PST 24
Finished	Feb 07 01:16:11 PM PST 24
Peak memory	205652 kb
Host	smart-dfaeb355-10a2-4b82-90d6-9d96385f4d98
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554189966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.554189966
Directory	/workspace/28.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.edn_intr_test.1889415363
Short name	T337
Test name
Test status
Simulation time	13992051 ps
CPU time	0.88 seconds
Started	Feb 07 01:16:10 PM PST 24
Finished	Feb 07 01:16:11 PM PST 24
Peak memory	205748 kb
Host	smart-87ed6eb5-711e-4d49-9b1a-89c841e80a7f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889415363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1889415363
Directory	/workspace/29.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.edn_csr_aliasing.4032645053
Short name	T136
Test name
Test status
Simulation time	138195584 ps
CPU time	1.45 seconds
Started	Feb 07 01:15:18 PM PST 24
Finished	Feb 07 01:15:24 PM PST 24
Peak memory	205872 kb
Host	smart-e9501f1e-c3b4-44e6-8e96-6e956dca463a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032645053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.4032645053
Directory	/workspace/3.edn_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2179714609
Short name	T281
Test name
Test status
Simulation time	339383591 ps
CPU time	5.33 seconds
Started	Feb 07 01:15:18 PM PST 24
Finished	Feb 07 01:15:28 PM PST 24
Peak memory	205804 kb
Host	smart-c90906a1-aaac-4945-92b2-03610577ef1c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179714609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2179714609
Directory	/workspace/3.edn_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.663373200
Short name	T273
Test name
Test status
Simulation time	24569965 ps
CPU time	0.88 seconds
Started	Feb 07 01:15:12 PM PST 24
Finished	Feb 07 01:15:20 PM PST 24
Peak memory	205864 kb
Host	smart-d4599280-48c9-4d9c-a2dc-a7ea8b960942
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663373200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.663373200
Directory	/workspace/3.edn_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2841325835
Short name	T134
Test name
Test status
Simulation time	31400218 ps
CPU time	1.01 seconds
Started	Feb 07 01:15:18 PM PST 24
Finished	Feb 07 01:15:23 PM PST 24
Peak memory	214088 kb
Host	smart-6d5ffaf2-74e9-43ff-86b8-01898ada0034
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841325835 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2841325835
Directory	/workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.edn_csr_rw.3110905914
Short name	T160
Test name
Test status
Simulation time	38526451 ps
CPU time	0.84 seconds
Started	Feb 07 01:15:19 PM PST 24
Finished	Feb 07 01:15:23 PM PST 24
Peak memory	205868 kb
Host	smart-c4b734e0-2c60-4d23-9593-b45707152b27
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110905914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3110905914
Directory	/workspace/3.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.edn_intr_test.839100008
Short name	T261
Test name
Test status
Simulation time	37991925 ps
CPU time	0.78 seconds
Started	Feb 07 01:15:06 PM PST 24
Finished	Feb 07 01:15:07 PM PST 24
Peak memory	205596 kb
Host	smart-203adbc0-98c9-47c2-8f89-5a2e93dae6a7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839100008 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.839100008
Directory	/workspace/3.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3604355208
Short name	T255
Test name
Test status
Simulation time	34332934 ps
CPU time	1.45 seconds
Started	Feb 07 01:15:11 PM PST 24
Finished	Feb 07 01:15:14 PM PST 24
Peak memory	205876 kb
Host	smart-514f131e-b50e-489f-8029-9ee2841580fb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604355208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou tstanding.3604355208
Directory	/workspace/3.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3883509931
Short name	T305
Test name
Test status
Simulation time	323488999 ps
CPU time	2.51 seconds
Started	Feb 07 01:14:57 PM PST 24
Finished	Feb 07 01:15:00 PM PST 24
Peak memory	205884 kb
Host	smart-3335deaa-cc71-4cec-9c5f-bd2ff7fc04ff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883509931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3883509931
Directory	/workspace/3.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.edn_intr_test.3110872722
Short name	T290
Test name
Test status
Simulation time	18350222 ps
CPU time	0.79 seconds
Started	Feb 07 01:16:11 PM PST 24
Finished	Feb 07 01:16:13 PM PST 24
Peak memory	205764 kb
Host	smart-22426240-415b-4621-84ec-a9dacb3ba00b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110872722 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3110872722
Directory	/workspace/30.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.edn_intr_test.1813578904
Short name	T289
Test name
Test status
Simulation time	23499382 ps
CPU time	0.82 seconds
Started	Feb 07 01:16:10 PM PST 24
Finished	Feb 07 01:16:12 PM PST 24
Peak memory	205744 kb
Host	smart-c7afaace-dd7e-4636-bbc3-b48c3e76d90e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813578904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1813578904
Directory	/workspace/31.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.edn_intr_test.223510909
Short name	T334
Test name
Test status
Simulation time	22182573 ps
CPU time	0.86 seconds
Started	Feb 07 01:16:07 PM PST 24
Finished	Feb 07 01:16:08 PM PST 24
Peak memory	205788 kb
Host	smart-c5343141-9d2a-4702-bc50-501bf36740a2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223510909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.223510909
Directory	/workspace/32.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.edn_intr_test.1977839926
Short name	T131
Test name
Test status
Simulation time	21978827 ps
CPU time	0.87 seconds
Started	Feb 07 01:16:07 PM PST 24
Finished	Feb 07 01:16:09 PM PST 24
Peak memory	205740 kb
Host	smart-da53a96b-bafa-42d7-b833-d390adb035fe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977839926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1977839926
Directory	/workspace/33.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.edn_intr_test.2225172528
Short name	T284
Test name
Test status
Simulation time	30552346 ps
CPU time	0.8 seconds
Started	Feb 07 01:16:13 PM PST 24
Finished	Feb 07 01:16:15 PM PST 24
Peak memory	205468 kb
Host	smart-279bbc51-378e-4177-a807-ae9ef89e2a4c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225172528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2225172528
Directory	/workspace/34.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.edn_intr_test.1494202578
Short name	T302
Test name
Test status
Simulation time	21101467 ps
CPU time	0.84 seconds
Started	Feb 07 01:16:10 PM PST 24
Finished	Feb 07 01:16:12 PM PST 24
Peak memory	205612 kb
Host	smart-09bd8eda-463c-4ed1-a382-ce2a16a33642
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494202578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1494202578
Directory	/workspace/35.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.edn_intr_test.888352936
Short name	T259
Test name
Test status
Simulation time	15231625 ps
CPU time	0.95 seconds
Started	Feb 07 01:16:06 PM PST 24
Finished	Feb 07 01:16:08 PM PST 24
Peak memory	205640 kb
Host	smart-1b898936-4af8-4004-8d62-d676ce653b22
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888352936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.888352936
Directory	/workspace/36.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.edn_intr_test.3977975367
Short name	T283
Test name
Test status
Simulation time	30823919 ps
CPU time	0.87 seconds
Started	Feb 07 01:16:08 PM PST 24
Finished	Feb 07 01:16:10 PM PST 24
Peak memory	205716 kb
Host	smart-7728d803-a699-475a-91d5-c114989f17dd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977975367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3977975367
Directory	/workspace/37.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.edn_intr_test.1578571131
Short name	T258
Test name
Test status
Simulation time	43079336 ps
CPU time	0.89 seconds
Started	Feb 07 01:16:06 PM PST 24
Finished	Feb 07 01:16:08 PM PST 24
Peak memory	205744 kb
Host	smart-9922a484-35e3-4bbd-a28e-a3dbf83c2ca6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578571131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1578571131
Directory	/workspace/38.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.edn_intr_test.2045163383
Short name	T262
Test name
Test status
Simulation time	26652223 ps
CPU time	0.89 seconds
Started	Feb 07 01:16:13 PM PST 24
Finished	Feb 07 01:16:15 PM PST 24
Peak memory	205616 kb
Host	smart-efcff89d-dc80-48f5-85c6-c5b57630feee
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045163383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2045163383
Directory	/workspace/39.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1356995755
Short name	T155
Test name
Test status
Simulation time	26797735 ps
CPU time	0.99 seconds
Started	Feb 07 01:15:18 PM PST 24
Finished	Feb 07 01:15:23 PM PST 24
Peak memory	205924 kb
Host	smart-ebb1b386-46dd-404a-95a3-e9375862bb2e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356995755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1356995755
Directory	/workspace/4.edn_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2694359729
Short name	T246
Test name
Test status
Simulation time	354733319 ps
CPU time	2.88 seconds
Started	Feb 07 01:15:17 PM PST 24
Finished	Feb 07 01:15:25 PM PST 24
Peak memory	205872 kb
Host	smart-89d910db-7ed7-4818-bb8b-26bec66504c3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694359729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2694359729
Directory	/workspace/4.edn_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3237550885
Short name	T20
Test name
Test status
Simulation time	16755902 ps
CPU time	0.97 seconds
Started	Feb 07 01:15:06 PM PST 24
Finished	Feb 07 01:15:08 PM PST 24
Peak memory	205760 kb
Host	smart-0d29202d-f849-43f8-be0c-8c397467eacc
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237550885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3237550885
Directory	/workspace/4.edn_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.817968059
Short name	T335
Test name
Test status
Simulation time	32234446 ps
CPU time	1.49 seconds
Started	Feb 07 01:15:06 PM PST 24
Finished	Feb 07 01:15:09 PM PST 24
Peak memory	214192 kb
Host	smart-27d9e212-2e59-4f96-a2cb-d9c8f578ea11
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817968059 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.817968059
Directory	/workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.edn_csr_rw.2976429626
Short name	T287
Test name
Test status
Simulation time	40583654 ps
CPU time	0.81 seconds
Started	Feb 07 01:15:17 PM PST 24
Finished	Feb 07 01:15:23 PM PST 24
Peak memory	205660 kb
Host	smart-0bcaffad-0d76-4762-907c-d682b2afed38
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976429626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2976429626
Directory	/workspace/4.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.edn_intr_test.2431967960
Short name	T263
Test name
Test status
Simulation time	15852362 ps
CPU time	0.91 seconds
Started	Feb 07 01:15:18 PM PST 24
Finished	Feb 07 01:15:23 PM PST 24
Peak memory	205676 kb
Host	smart-95738372-0773-4841-9bd7-2a547b952b09
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431967960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2431967960
Directory	/workspace/4.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2609852858
Short name	T328
Test name
Test status
Simulation time	100326124 ps
CPU time	1.46 seconds
Started	Feb 07 01:15:20 PM PST 24
Finished	Feb 07 01:15:24 PM PST 24
Peak memory	205880 kb
Host	smart-6434c8ae-19d4-4e22-ba0a-da036ccd6c16
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609852858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou tstanding.2609852858
Directory	/workspace/4.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.edn_tl_errors.8480646
Short name	T141
Test name
Test status
Simulation time	172579103 ps
CPU time	2.2 seconds
Started	Feb 07 01:15:11 PM PST 24
Finished	Feb 07 01:15:15 PM PST 24
Peak memory	214084 kb
Host	smart-81da3d02-6355-483e-9f63-69c1640e22de
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8480646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.8480646
Directory	/workspace/4.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3393235952
Short name	T293
Test name
Test status
Simulation time	93402782 ps
CPU time	2.5 seconds
Started	Feb 07 01:15:17 PM PST 24
Finished	Feb 07 01:15:25 PM PST 24
Peak memory	205864 kb
Host	smart-9f9e93b4-746c-41c3-86e5-78c3952a7dfc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393235952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3393235952
Directory	/workspace/4.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.edn_intr_test.3195678604
Short name	T320
Test name
Test status
Simulation time	25034350 ps
CPU time	0.88 seconds
Started	Feb 07 01:16:10 PM PST 24
Finished	Feb 07 01:16:12 PM PST 24
Peak memory	205792 kb
Host	smart-c7f7b494-3401-4b89-9ec4-45451f84e2e9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195678604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3195678604
Directory	/workspace/40.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.edn_intr_test.2452707382
Short name	T316
Test name
Test status
Simulation time	15004318 ps
CPU time	0.87 seconds
Started	Feb 07 01:16:35 PM PST 24
Finished	Feb 07 01:16:36 PM PST 24
Peak memory	205728 kb
Host	smart-519f5518-f978-45de-bd23-c8c3454d1e6e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452707382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2452707382
Directory	/workspace/41.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.edn_intr_test.1848463892
Short name	T333
Test name
Test status
Simulation time	37066187 ps
CPU time	0.8 seconds
Started	Feb 07 01:16:28 PM PST 24
Finished	Feb 07 01:16:30 PM PST 24
Peak memory	205440 kb
Host	smart-393adce2-d81b-4fec-b002-12056b2348a9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848463892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1848463892
Directory	/workspace/42.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.edn_intr_test.532281842
Short name	T62
Test name
Test status
Simulation time	11065367 ps
CPU time	0.83 seconds
Started	Feb 07 01:16:28 PM PST 24
Finished	Feb 07 01:16:29 PM PST 24
Peak memory	205660 kb
Host	smart-40ecf6df-b753-4386-9968-dabc7012af99
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532281842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.532281842
Directory	/workspace/43.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.edn_intr_test.2669228049
Short name	T300
Test name
Test status
Simulation time	20627576 ps
CPU time	0.79 seconds
Started	Feb 07 01:16:27 PM PST 24
Finished	Feb 07 01:16:28 PM PST 24
Peak memory	205608 kb
Host	smart-e4693279-b5ad-4c9f-81c1-259bd17f1936
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669228049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2669228049
Directory	/workspace/44.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.edn_intr_test.4282445408
Short name	T318
Test name
Test status
Simulation time	13851298 ps
CPU time	0.89 seconds
Started	Feb 07 01:16:27 PM PST 24
Finished	Feb 07 01:16:28 PM PST 24
Peak memory	205768 kb
Host	smart-40e74f77-c352-49f0-a30b-acd16e70939b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282445408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.4282445408
Directory	/workspace/45.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.edn_intr_test.3533855660
Short name	T145
Test name
Test status
Simulation time	60372150 ps
CPU time	0.83 seconds
Started	Feb 07 01:16:37 PM PST 24
Finished	Feb 07 01:16:38 PM PST 24
Peak memory	205760 kb
Host	smart-1835af66-ca88-417a-802f-d449b05fcc8e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533855660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3533855660
Directory	/workspace/46.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.edn_intr_test.3172915964
Short name	T291
Test name
Test status
Simulation time	14789795 ps
CPU time	0.91 seconds
Started	Feb 07 01:16:29 PM PST 24
Finished	Feb 07 01:16:30 PM PST 24
Peak memory	205692 kb
Host	smart-41dcc053-ff48-44a3-890e-fc95264e387f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172915964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3172915964
Directory	/workspace/47.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.edn_intr_test.1271205143
Short name	T205
Test name
Test status
Simulation time	13647003 ps
CPU time	0.88 seconds
Started	Feb 07 01:16:30 PM PST 24
Finished	Feb 07 01:16:31 PM PST 24
Peak memory	205724 kb
Host	smart-fe56a7fe-712c-41dc-b8a5-7de200ea0a70
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271205143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1271205143
Directory	/workspace/48.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.edn_intr_test.3354919692
Short name	T146
Test name
Test status
Simulation time	40279512 ps
CPU time	0.77 seconds
Started	Feb 07 01:16:28 PM PST 24
Finished	Feb 07 01:16:29 PM PST 24
Peak memory	205596 kb
Host	smart-56087cd1-f22b-4c33-a8de-59a14e7cf3f8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354919692 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3354919692
Directory	/workspace/49.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2146385601
Short name	T292
Test name
Test status
Simulation time	25470430 ps
CPU time	1.29 seconds
Started	Feb 07 01:15:20 PM PST 24
Finished	Feb 07 01:15:24 PM PST 24
Peak memory	214112 kb
Host	smart-9973e091-4199-4632-8d04-c52396220447
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146385601 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2146385601
Directory	/workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.edn_csr_rw.2142678289
Short name	T154
Test name
Test status
Simulation time	26141330 ps
CPU time	0.8 seconds
Started	Feb 07 01:15:18 PM PST 24
Finished	Feb 07 01:15:23 PM PST 24
Peak memory	205656 kb
Host	smart-5b7b07e3-7f4d-445c-992b-fe53463b6292
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142678289 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2142678289
Directory	/workspace/5.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1149475474
Short name	T321
Test name
Test status
Simulation time	23889618 ps
CPU time	1.11 seconds
Started	Feb 07 01:15:23 PM PST 24
Finished	Feb 07 01:15:33 PM PST 24
Peak memory	205864 kb
Host	smart-59fef8af-a575-4b52-962e-57d5ed9f8bdc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149475474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou tstanding.1149475474
Directory	/workspace/5.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.edn_tl_errors.2584003328
Short name	T271
Test name
Test status
Simulation time	462696222 ps
CPU time	2.88 seconds
Started	Feb 07 01:15:06 PM PST 24
Finished	Feb 07 01:15:10 PM PST 24
Peak memory	214224 kb
Host	smart-eac82217-d1f5-4f48-969a-3fec07e384d0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584003328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2584003328
Directory	/workspace/5.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1793488085
Short name	T325
Test name
Test status
Simulation time	24240993 ps
CPU time	1.23 seconds
Started	Feb 07 01:15:21 PM PST 24
Finished	Feb 07 01:15:31 PM PST 24
Peak memory	214184 kb
Host	smart-2a229347-e11b-4827-809b-1069dc57ad9f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793488085 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1793488085
Directory	/workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.edn_csr_rw.2928284920
Short name	T265
Test name
Test status
Simulation time	43153984 ps
CPU time	0.92 seconds
Started	Feb 07 01:15:21 PM PST 24
Finished	Feb 07 01:15:31 PM PST 24
Peak memory	205712 kb
Host	smart-f3b558fd-fcc3-45b9-9424-5e0ec816ee7b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928284920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2928284920
Directory	/workspace/6.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.edn_intr_test.2008155863
Short name	T323
Test name
Test status
Simulation time	24928765 ps
CPU time	0.86 seconds
Started	Feb 07 01:15:22 PM PST 24
Finished	Feb 07 01:15:32 PM PST 24
Peak memory	205764 kb
Host	smart-232d6968-9e4f-4510-b3b3-6f63e49ae8bd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008155863 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2008155863
Directory	/workspace/6.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.604120965
Short name	T282
Test name
Test status
Simulation time	29522324 ps
CPU time	0.96 seconds
Started	Feb 07 01:15:22 PM PST 24
Finished	Feb 07 01:15:32 PM PST 24
Peak memory	205744 kb
Host	smart-98914973-10b3-40e0-988c-ba6f83e9c495
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604120965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out standing.604120965
Directory	/workspace/6.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.edn_tl_errors.3080249171
Short name	T280
Test name
Test status
Simulation time	207263314 ps
CPU time	3.85 seconds
Started	Feb 07 01:15:21 PM PST 24
Finished	Feb 07 01:15:30 PM PST 24
Peak memory	214112 kb
Host	smart-5b391923-f0f9-4f57-a273-be88422e2874
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080249171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3080249171
Directory	/workspace/6.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2496017879
Short name	T142
Test name
Test status
Simulation time	323647638 ps
CPU time	2.31 seconds
Started	Feb 07 01:15:19 PM PST 24
Finished	Feb 07 01:15:25 PM PST 24
Peak memory	205928 kb
Host	smart-e116ac24-ca50-4323-85dc-0c909e92f15e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496017879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2496017879
Directory	/workspace/6.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3701773795
Short name	T322
Test name
Test status
Simulation time	26154415 ps
CPU time	1.67 seconds
Started	Feb 07 01:15:23 PM PST 24
Finished	Feb 07 01:15:33 PM PST 24
Peak memory	214164 kb
Host	smart-9664b918-be58-471d-9996-c632106ed830
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701773795 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3701773795
Directory	/workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.edn_csr_rw.2704430709
Short name	T25
Test name
Test status
Simulation time	18378521 ps
CPU time	0.81 seconds
Started	Feb 07 01:15:17 PM PST 24
Finished	Feb 07 01:15:23 PM PST 24
Peak memory	205652 kb
Host	smart-7b59362b-48a8-430d-8893-46071de27b9e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704430709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2704430709
Directory	/workspace/7.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.edn_intr_test.4140264651
Short name	T310
Test name
Test status
Simulation time	28147369 ps
CPU time	0.87 seconds
Started	Feb 07 01:15:22 PM PST 24
Finished	Feb 07 01:15:32 PM PST 24
Peak memory	205740 kb
Host	smart-20383142-300d-4531-aeba-3f999c502b35
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140264651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.4140264651
Directory	/workspace/7.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2612482908
Short name	T340
Test name
Test status
Simulation time	35709154 ps
CPU time	0.89 seconds
Started	Feb 07 01:15:21 PM PST 24
Finished	Feb 07 01:15:28 PM PST 24
Peak memory	205784 kb
Host	smart-b62e98a1-2555-4c71-b6d6-74c2f854763d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612482908 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou tstanding.2612482908
Directory	/workspace/7.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.edn_tl_errors.3828157106
Short name	T319
Test name
Test status
Simulation time	366037474 ps
CPU time	3.49 seconds
Started	Feb 07 01:15:22 PM PST 24
Finished	Feb 07 01:15:35 PM PST 24
Peak memory	214080 kb
Host	smart-69367aa1-c4a5-4f12-9a18-8ebdfedde059
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828157106 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3828157106
Directory	/workspace/7.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2006170300
Short name	T285
Test name
Test status
Simulation time	19190302 ps
CPU time	1.34 seconds
Started	Feb 07 01:15:38 PM PST 24
Finished	Feb 07 01:15:40 PM PST 24
Peak memory	216216 kb
Host	smart-6524528a-e48c-4cb9-88c0-7f0428ddde7e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006170300 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2006170300
Directory	/workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.edn_csr_rw.1584390918
Short name	T162
Test name
Test status
Simulation time	16846150 ps
CPU time	0.88 seconds
Started	Feb 07 01:15:37 PM PST 24
Finished	Feb 07 01:15:39 PM PST 24
Peak memory	205812 kb
Host	smart-860831c0-592b-4ecf-8dd7-cd754a1f85be
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584390918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1584390918
Directory	/workspace/8.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.edn_intr_test.1798784892
Short name	T249
Test name
Test status
Simulation time	41872501 ps
CPU time	0.79 seconds
Started	Feb 07 01:15:36 PM PST 24
Finished	Feb 07 01:15:38 PM PST 24
Peak memory	205464 kb
Host	smart-01243dcf-71c7-4330-88c7-4589d52adabb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798784892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1798784892
Directory	/workspace/8.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.801323695
Short name	T140
Test name
Test status
Simulation time	74644583 ps
CPU time	1.05 seconds
Started	Feb 07 01:15:34 PM PST 24
Finished	Feb 07 01:15:37 PM PST 24
Peak memory	205840 kb
Host	smart-f8d01c1b-ae33-411e-931c-95ae040d68e7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801323695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_out standing.801323695
Directory	/workspace/8.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.edn_tl_errors.2197961847
Short name	T137
Test name
Test status
Simulation time	876471220 ps
CPU time	4.98 seconds
Started	Feb 07 01:15:22 PM PST 24
Finished	Feb 07 01:15:36 PM PST 24
Peak memory	217412 kb
Host	smart-b9e6ced9-4283-474a-9f30-6ad27aeec70f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197961847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2197961847
Directory	/workspace/8.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1762478921
Short name	T26
Test name
Test status
Simulation time	356591527 ps
CPU time	2.24 seconds
Started	Feb 07 01:15:34 PM PST 24
Finished	Feb 07 01:15:38 PM PST 24
Peak memory	205916 kb
Host	smart-e1cab01f-e3e0-4afc-b55a-b35410672fa8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762478921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1762478921
Directory	/workspace/8.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3721067518
Short name	T240
Test name
Test status
Simulation time	169919679 ps
CPU time	1.36 seconds
Started	Feb 07 01:15:34 PM PST 24
Finished	Feb 07 01:15:37 PM PST 24
Peak memory	214208 kb
Host	smart-83aa8af2-99ad-4b5e-9e25-5a1e20fd00a6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721067518 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3721067518
Directory	/workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.edn_csr_rw.3256909928
Short name	T339
Test name
Test status
Simulation time	23873574 ps
CPU time	0.88 seconds
Started	Feb 07 01:15:38 PM PST 24
Finished	Feb 07 01:15:39 PM PST 24
Peak memory	205756 kb
Host	smart-1c2a9baa-37f5-4cd1-8024-abe41e7d526b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256909928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3256909928
Directory	/workspace/9.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.edn_intr_test.1370879016
Short name	T330
Test name
Test status
Simulation time	55979253 ps
CPU time	0.76 seconds
Started	Feb 07 01:15:33 PM PST 24
Finished	Feb 07 01:15:36 PM PST 24
Peak memory	205648 kb
Host	smart-572882ab-b3e8-4681-ab2f-eaaec11a8c7e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370879016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1370879016
Directory	/workspace/9.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.4069877737
Short name	T297
Test name
Test status
Simulation time	30703133 ps
CPU time	1.07 seconds
Started	Feb 07 01:15:36 PM PST 24
Finished	Feb 07 01:15:38 PM PST 24
Peak memory	205920 kb
Host	smart-ad09be2c-f104-45f5-96dc-8b6fdbeb07ca
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069877737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou tstanding.4069877737
Directory	/workspace/9.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.edn_tl_errors.1422212131
Short name	T304
Test name
Test status
Simulation time	36024184 ps
CPU time	1.99 seconds
Started	Feb 07 01:15:34 PM PST 24
Finished	Feb 07 01:15:38 PM PST 24
Peak memory	214072 kb
Host	smart-11ec851f-1488-4a57-a28e-b9d9ffc94905
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422212131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1422212131
Directory	/workspace/9.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1906884751
Short name	T329
Test name
Test status
Simulation time	49973412 ps
CPU time	1.47 seconds
Started	Feb 07 01:15:35 PM PST 24
Finished	Feb 07 01:15:38 PM PST 24
Peak memory	205932 kb
Host	smart-6bfdb935-0606-48eb-b2d7-851db4de6aab
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906884751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1906884751
Directory	/workspace/9.edn_tl_intg_err/latest

Test location	/workspace/coverage/default/0.edn_alert.2605080091
Short name	T91
Test name
Test status
Simulation time	70688556 ps
CPU time	1.04 seconds
Started	Feb 07 12:47:55 PM PST 24
Finished	Feb 07 12:47:57 PM PST 24
Peak memory	205892 kb
Host	smart-c9483311-eed7-4d14-95a8-ed4ecc36026e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2605080091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2605080091
Directory	/workspace/0.edn_alert/latest

Test location	/workspace/coverage/default/0.edn_alert_test.3972033520
Short name	T562
Test name
Test status
Simulation time	28664420 ps
CPU time	0.9 seconds
Started	Feb 07 12:47:47 PM PST 24
Finished	Feb 07 12:47:49 PM PST 24
Peak memory	205412 kb
Host	smart-07a52810-652d-4c71-a848-eba9fccd0b2e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972033520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3972033520
Directory	/workspace/0.edn_alert_test/latest

Test location	/workspace/coverage/default/0.edn_genbits.235157000
Short name	T908
Test name
Test status
Simulation time	71300370 ps
CPU time	1.23 seconds
Started	Feb 07 12:47:54 PM PST 24
Finished	Feb 07 12:47:56 PM PST 24
Peak memory	216824 kb
Host	smart-0404208b-ee3a-42f1-b736-c149ac5aa328
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=235157000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.235157000
Directory	/workspace/0.edn_genbits/latest

Test location	/workspace/coverage/default/0.edn_intr.983700111
Short name	T67
Test name
Test status
Simulation time	22243285 ps
CPU time	1.08 seconds
Started	Feb 07 12:47:53 PM PST 24
Finished	Feb 07 12:47:55 PM PST 24
Peak memory	215328 kb
Host	smart-84643bd4-74be-4c46-9283-883c21b52e37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=983700111 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.983700111
Directory	/workspace/0.edn_intr/latest

Test location	/workspace/coverage/default/0.edn_regwen.4680722
Short name	T932
Test name
Test status
Simulation time	24081327 ps
CPU time	0.89 seconds
Started	Feb 07 12:47:40 PM PST 24
Finished	Feb 07 12:47:42 PM PST 24
Peak memory	206716 kb
Host	smart-aa0e8505-3061-418f-a757-b106277b607e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4680722 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.4680722
Directory	/workspace/0.edn_regwen/latest

Test location	/workspace/coverage/default/0.edn_sec_cm.84466939
Short name	T55
Test name
Test status
Simulation time	369644745 ps
CPU time	6.21 seconds
Started	Feb 07 12:47:47 PM PST 24
Finished	Feb 07 12:47:54 PM PST 24
Peak memory	234652 kb
Host	smart-747cee44-1a99-4a9b-ae34-114c9a75febf
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84466939 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.84466939
Directory	/workspace/0.edn_sec_cm/latest

Test location	/workspace/coverage/default/0.edn_smoke.1849290524
Short name	T823
Test name
Test status
Simulation time	41594465 ps
CPU time	0.93 seconds
Started	Feb 07 12:47:42 PM PST 24
Finished	Feb 07 12:47:44 PM PST 24
Peak memory	214960 kb
Host	smart-22f0375d-d863-4d0e-8ba2-e1629e1d3fb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1849290524 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1849290524
Directory	/workspace/0.edn_smoke/latest

Test location	/workspace/coverage/default/0.edn_stress_all.2982296153
Short name	T570
Test name
Test status
Simulation time	278238693 ps
CPU time	5.07 seconds
Started	Feb 07 12:47:43 PM PST 24
Finished	Feb 07 12:47:49 PM PST 24
Peak memory	216632 kb
Host	smart-3d46e5d0-d650-4f65-aa71-5530e1a96e10
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982296153 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2982296153
Directory	/workspace/0.edn_stress_all/latest

Test location	/workspace/coverage/default/0.edn_stress_all_with_rand_reset.3014102449
Short name	T618
Test name
Test status
Simulation time	124557904510 ps
CPU time	2945.41 seconds
Started	Feb 07 12:47:40 PM PST 24
Finished	Feb 07 01:36:47 PM PST 24
Peak memory	228660 kb
Host	smart-13841720-a180-4201-8a57-48ce897e7959
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014102449 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3014102449
Directory	/workspace/0.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.edn_alert_test.256020984
Short name	T453
Test name
Test status
Simulation time	16699690 ps
CPU time	0.95 seconds
Started	Feb 07 12:47:47 PM PST 24
Finished	Feb 07 12:47:49 PM PST 24
Peak memory	205448 kb
Host	smart-5459abdd-7bd8-412e-8cd2-186f69972b79
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256020984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.256020984
Directory	/workspace/1.edn_alert_test/latest

Test location	/workspace/coverage/default/1.edn_disable_auto_req_mode.1521332421
Short name	T683
Test name
Test status
Simulation time	46140754 ps
CPU time	1 seconds
Started	Feb 07 12:47:49 PM PST 24
Finished	Feb 07 12:47:51 PM PST 24
Peak memory	215276 kb
Host	smart-28eb3ec9-e372-4c04-b515-eba7f032a739
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521332421 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di sable_auto_req_mode.1521332421
Directory	/workspace/1.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/1.edn_err.752520219
Short name	T520
Test name
Test status
Simulation time	55522082 ps
CPU time	0.94 seconds
Started	Feb 07 12:47:48 PM PST 24
Finished	Feb 07 12:47:50 PM PST 24
Peak memory	216596 kb
Host	smart-2b0a8f01-b48c-4a55-83fe-21d2a8e61a25
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=752520219 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.752520219
Directory	/workspace/1.edn_err/latest

Test location	/workspace/coverage/default/1.edn_genbits.2406212673
Short name	T815
Test name
Test status
Simulation time	47026253 ps
CPU time	1.18 seconds
Started	Feb 07 12:47:45 PM PST 24
Finished	Feb 07 12:47:47 PM PST 24
Peak memory	216760 kb
Host	smart-ece8019b-4fff-411c-add8-b446bf2b347e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2406212673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2406212673
Directory	/workspace/1.edn_genbits/latest

Test location	/workspace/coverage/default/1.edn_intr.2877278527
Short name	T72
Test name
Test status
Simulation time	101051257 ps
CPU time	0.79 seconds
Started	Feb 07 12:47:47 PM PST 24
Finished	Feb 07 12:47:49 PM PST 24
Peak memory	215116 kb
Host	smart-29bf4d8d-b247-43b0-9c98-75ea074ecda2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2877278527 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2877278527
Directory	/workspace/1.edn_intr/latest

Test location	/workspace/coverage/default/1.edn_sec_cm.644370525
Short name	T16
Test name
Test status
Simulation time	540004398 ps
CPU time	8.02 seconds
Started	Feb 07 12:47:48 PM PST 24
Finished	Feb 07 12:47:57 PM PST 24
Peak memory	234724 kb
Host	smart-2e001ffd-b511-46f6-9450-626a533d724d
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644370525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.644370525
Directory	/workspace/1.edn_sec_cm/latest

Test location	/workspace/coverage/default/1.edn_smoke.3528778295
Short name	T839
Test name
Test status
Simulation time	18534462 ps
CPU time	0.98 seconds
Started	Feb 07 12:47:45 PM PST 24
Finished	Feb 07 12:47:47 PM PST 24
Peak memory	214996 kb
Host	smart-a034bc88-5fa7-4a7e-a36f-045c03804d8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3528778295 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3528778295
Directory	/workspace/1.edn_smoke/latest

Test location	/workspace/coverage/default/1.edn_stress_all.2909199004
Short name	T397
Test name
Test status
Simulation time	453976241 ps
CPU time	4.69 seconds
Started	Feb 07 12:47:56 PM PST 24
Finished	Feb 07 12:48:01 PM PST 24
Peak memory	216472 kb
Host	smart-c649907d-b40c-48d3-b00a-fec1a4d28e13
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909199004 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2909199004
Directory	/workspace/1.edn_stress_all/latest

Test location	/workspace/coverage/default/10.edn_alert.2333156821
Short name	T756
Test name
Test status
Simulation time	34351214 ps
CPU time	0.98 seconds
Started	Feb 07 12:48:06 PM PST 24
Finished	Feb 07 12:48:08 PM PST 24
Peak memory	206008 kb
Host	smart-4de777af-ffad-4657-88a6-4355618a0202
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2333156821 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2333156821
Directory	/workspace/10.edn_alert/latest

Test location	/workspace/coverage/default/10.edn_disable.2000844552
Short name	T479
Test name
Test status
Simulation time	10760355 ps
CPU time	0.86 seconds
Started	Feb 07 12:48:03 PM PST 24
Finished	Feb 07 12:48:04 PM PST 24
Peak memory	214732 kb
Host	smart-16ace31c-c3ef-401d-95b5-ea0bca2f3eb4
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000844552 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2000844552
Directory	/workspace/10.edn_disable/latest

Test location	/workspace/coverage/default/10.edn_err.2081925467
Short name	T619
Test name
Test status
Simulation time	24124272 ps
CPU time	1.11 seconds
Started	Feb 07 12:48:07 PM PST 24
Finished	Feb 07 12:48:10 PM PST 24
Peak memory	216732 kb
Host	smart-c3f3cb7c-b5eb-468b-b5bc-b29cda7a0359
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2081925467 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2081925467
Directory	/workspace/10.edn_err/latest

Test location	/workspace/coverage/default/10.edn_genbits.770768366
Short name	T959
Test name
Test status
Simulation time	43510535 ps
CPU time	1.62 seconds
Started	Feb 07 12:48:06 PM PST 24
Finished	Feb 07 12:48:09 PM PST 24
Peak memory	216716 kb
Host	smart-3d83b3a8-6a9a-4943-9bab-8499c9687d82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=770768366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.770768366
Directory	/workspace/10.edn_genbits/latest

Test location	/workspace/coverage/default/10.edn_intr.1434829936
Short name	T75
Test name
Test status
Simulation time	21709475 ps
CPU time	1.07 seconds
Started	Feb 07 12:48:05 PM PST 24
Finished	Feb 07 12:48:07 PM PST 24
Peak memory	215432 kb
Host	smart-28751628-f632-4c5d-9116-47039b476a03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1434829936 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1434829936
Directory	/workspace/10.edn_intr/latest

Test location	/workspace/coverage/default/10.edn_smoke.640726488
Short name	T776
Test name
Test status
Simulation time	39625191 ps
CPU time	0.92 seconds
Started	Feb 07 12:48:05 PM PST 24
Finished	Feb 07 12:48:07 PM PST 24
Peak memory	215104 kb
Host	smart-596a8d81-56aa-47d6-a0b8-3fdb2dd3c84e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=640726488 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.640726488
Directory	/workspace/10.edn_smoke/latest

Test location	/workspace/coverage/default/10.edn_stress_all.3132063690
Short name	T376
Test name
Test status
Simulation time	64913971 ps
CPU time	1.95 seconds
Started	Feb 07 12:48:08 PM PST 24
Finished	Feb 07 12:48:11 PM PST 24
Peak memory	214868 kb
Host	smart-94705ca2-3f22-4d91-a585-05d536a64b0c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132063690 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3132063690
Directory	/workspace/10.edn_stress_all/latest

Test location	/workspace/coverage/default/10.edn_stress_all_with_rand_reset.1085477436
Short name	T858
Test name
Test status
Simulation time	220078956996 ps
CPU time	1142.21 seconds
Started	Feb 07 12:48:05 PM PST 24
Finished	Feb 07 01:07:08 PM PST 24
Peak memory	221164 kb
Host	smart-5e724ef5-ec61-4a00-a1d5-01b812bbda51
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085477436 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1085477436
Directory	/workspace/10.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/101.edn_genbits.3710619570
Short name	T457
Test name
Test status
Simulation time	63109764 ps
CPU time	1.17 seconds
Started	Feb 07 12:49:29 PM PST 24
Finished	Feb 07 12:49:31 PM PST 24
Peak memory	216868 kb
Host	smart-b5f015f4-0424-4f6c-8a60-50916def4a6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3710619570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3710619570
Directory	/workspace/101.edn_genbits/latest

Test location	/workspace/coverage/default/102.edn_genbits.2975707020
Short name	T797
Test name
Test status
Simulation time	31333055 ps
CPU time	1.37 seconds
Started	Feb 07 12:49:28 PM PST 24
Finished	Feb 07 12:49:31 PM PST 24
Peak memory	216644 kb
Host	smart-26e31b98-aae0-4d54-84f2-634fe24efa6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2975707020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2975707020
Directory	/workspace/102.edn_genbits/latest

Test location	/workspace/coverage/default/103.edn_genbits.3416255200
Short name	T480
Test name
Test status
Simulation time	47245188 ps
CPU time	1.13 seconds
Started	Feb 07 12:49:34 PM PST 24
Finished	Feb 07 12:49:37 PM PST 24
Peak memory	217676 kb
Host	smart-76d84be9-213c-477f-b207-3a02f5077874
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3416255200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3416255200
Directory	/workspace/103.edn_genbits/latest

Test location	/workspace/coverage/default/104.edn_genbits.4149724494
Short name	T383
Test name
Test status
Simulation time	65373246 ps
CPU time	1.53 seconds
Started	Feb 07 12:49:31 PM PST 24
Finished	Feb 07 12:49:34 PM PST 24
Peak memory	216620 kb
Host	smart-082d2787-4313-4b85-be00-c6464a0fb1da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4149724494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.4149724494
Directory	/workspace/104.edn_genbits/latest

Test location	/workspace/coverage/default/105.edn_genbits.3465344758
Short name	T532
Test name
Test status
Simulation time	87061192 ps
CPU time	1.43 seconds
Started	Feb 07 12:49:34 PM PST 24
Finished	Feb 07 12:49:37 PM PST 24
Peak memory	217024 kb
Host	smart-0b99786a-cd25-431f-9bca-2b001a67a855
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3465344758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3465344758
Directory	/workspace/105.edn_genbits/latest

Test location	/workspace/coverage/default/106.edn_genbits.2194063586
Short name	T213
Test name
Test status
Simulation time	84242118 ps
CPU time	1.06 seconds
Started	Feb 07 12:49:38 PM PST 24
Finished	Feb 07 12:49:42 PM PST 24
Peak memory	215512 kb
Host	smart-9c4d06e1-fc6f-484e-afca-048dd363d17d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2194063586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2194063586
Directory	/workspace/106.edn_genbits/latest

Test location	/workspace/coverage/default/107.edn_genbits.898881014
Short name	T647
Test name
Test status
Simulation time	111632603 ps
CPU time	1.25 seconds
Started	Feb 07 12:49:35 PM PST 24
Finished	Feb 07 12:49:39 PM PST 24
Peak memory	218044 kb
Host	smart-88b625d6-fb17-43e6-ac8f-939153e25895
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=898881014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.898881014
Directory	/workspace/107.edn_genbits/latest

Test location	/workspace/coverage/default/109.edn_genbits.979860816
Short name	T779
Test name
Test status
Simulation time	48798589 ps
CPU time	1.39 seconds
Started	Feb 07 12:49:43 PM PST 24
Finished	Feb 07 12:49:46 PM PST 24
Peak memory	217024 kb
Host	smart-9efaf714-2c83-4e7e-a91f-f143de46af13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=979860816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.979860816
Directory	/workspace/109.edn_genbits/latest

Test location	/workspace/coverage/default/11.edn_alert.3093735883
Short name	T957
Test name
Test status
Simulation time	38093171 ps
CPU time	1.04 seconds
Started	Feb 07 12:48:07 PM PST 24
Finished	Feb 07 12:48:09 PM PST 24
Peak memory	206280 kb
Host	smart-af041774-1369-4e5d-8c96-fb8d3da9925b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3093735883 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3093735883
Directory	/workspace/11.edn_alert/latest

Test location	/workspace/coverage/default/11.edn_alert_test.1418678857
Short name	T926
Test name
Test status
Simulation time	32147636 ps
CPU time	0.9 seconds
Started	Feb 07 12:48:15 PM PST 24
Finished	Feb 07 12:48:17 PM PST 24
Peak memory	206344 kb
Host	smart-89d7e627-021e-478f-9d95-30913211d1c2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418678857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1418678857
Directory	/workspace/11.edn_alert_test/latest

Test location	/workspace/coverage/default/11.edn_disable.2008468519
Short name	T118
Test name
Test status
Simulation time	29753454 ps
CPU time	0.84 seconds
Started	Feb 07 12:48:33 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	214984 kb
Host	smart-3519ab56-f630-49c8-a6b7-19fac386d6f0
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008468519 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2008468519
Directory	/workspace/11.edn_disable/latest

Test location	/workspace/coverage/default/11.edn_disable_auto_req_mode.3018100408
Short name	T875
Test name
Test status
Simulation time	32647466 ps
CPU time	1.03 seconds
Started	Feb 07 12:48:18 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	215192 kb
Host	smart-c8ef0c23-c120-4dc6-8a37-8247e2907808
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018100408 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d isable_auto_req_mode.3018100408
Directory	/workspace/11.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/11.edn_err.359677621
Short name	T730
Test name
Test status
Simulation time	92593117 ps
CPU time	1.17 seconds
Started	Feb 07 12:48:07 PM PST 24
Finished	Feb 07 12:48:09 PM PST 24
Peak memory	229280 kb
Host	smart-3080efc6-46f5-4dbe-ae55-6198048875e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=359677621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.359677621
Directory	/workspace/11.edn_err/latest

Test location	/workspace/coverage/default/11.edn_genbits.3317818004
Short name	T482
Test name
Test status
Simulation time	84505689 ps
CPU time	2.04 seconds
Started	Feb 07 12:48:21 PM PST 24
Finished	Feb 07 12:48:28 PM PST 24
Peak memory	216520 kb
Host	smart-0ccebffc-6b0d-4218-977f-2f53e3ead93e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3317818004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3317818004
Directory	/workspace/11.edn_genbits/latest

Test location	/workspace/coverage/default/11.edn_intr.3468962153
Short name	T560
Test name
Test status
Simulation time	23957232 ps
CPU time	1.01 seconds
Started	Feb 07 12:48:17 PM PST 24
Finished	Feb 07 12:48:19 PM PST 24
Peak memory	222308 kb
Host	smart-48fbec18-333a-4e75-ad75-21004d25a17f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3468962153 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3468962153
Directory	/workspace/11.edn_intr/latest

Test location	/workspace/coverage/default/11.edn_smoke.4039523066
Short name	T478
Test name
Test status
Simulation time	48479503 ps
CPU time	0.91 seconds
Started	Feb 07 12:48:08 PM PST 24
Finished	Feb 07 12:48:10 PM PST 24
Peak memory	214944 kb
Host	smart-4e2d7227-463f-4a22-836b-78c5b2db555d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4039523066 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.4039523066
Directory	/workspace/11.edn_smoke/latest

Test location	/workspace/coverage/default/11.edn_stress_all.1853084630
Short name	T852
Test name
Test status
Simulation time	39233715 ps
CPU time	1.25 seconds
Started	Feb 07 12:48:05 PM PST 24
Finished	Feb 07 12:48:07 PM PST 24
Peak memory	214992 kb
Host	smart-c0dd575d-c52d-4771-869f-ffd1dd2c8da1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853084630 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1853084630
Directory	/workspace/11.edn_stress_all/latest

Test location	/workspace/coverage/default/11.edn_stress_all_with_rand_reset.237846280
Short name	T84
Test name
Test status
Simulation time	378475837895 ps
CPU time	2472.04 seconds
Started	Feb 07 12:48:06 PM PST 24
Finished	Feb 07 01:29:19 PM PST 24
Peak memory	229364 kb
Host	smart-89461ae4-4e69-428d-bf3e-80d1def401d0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237846280 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.237846280
Directory	/workspace/11.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/111.edn_genbits.3363937506
Short name	T905
Test name
Test status
Simulation time	72142309 ps
CPU time	1.08 seconds
Started	Feb 07 12:49:38 PM PST 24
Finished	Feb 07 12:49:42 PM PST 24
Peak memory	215380 kb
Host	smart-247c7300-03db-4f5c-aa4d-89d498bb0127
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363937506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3363937506
Directory	/workspace/111.edn_genbits/latest

Test location	/workspace/coverage/default/112.edn_genbits.2071517500
Short name	T469
Test name
Test status
Simulation time	194414300 ps
CPU time	1.32 seconds
Started	Feb 07 12:49:39 PM PST 24
Finished	Feb 07 12:49:44 PM PST 24
Peak memory	215504 kb
Host	smart-95d29084-f930-4cf9-81ad-7fd94c5cc74e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2071517500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2071517500
Directory	/workspace/112.edn_genbits/latest

Test location	/workspace/coverage/default/113.edn_genbits.2771157256
Short name	T761
Test name
Test status
Simulation time	66526764 ps
CPU time	1.58 seconds
Started	Feb 07 12:49:42 PM PST 24
Finished	Feb 07 12:49:46 PM PST 24
Peak memory	216776 kb
Host	smart-f4f2d99b-9b4d-49ca-908f-adc096f231f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2771157256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2771157256
Directory	/workspace/113.edn_genbits/latest

Test location	/workspace/coverage/default/114.edn_genbits.1578882910
Short name	T512
Test name
Test status
Simulation time	183492711 ps
CPU time	1.21 seconds
Started	Feb 07 12:49:36 PM PST 24
Finished	Feb 07 12:49:40 PM PST 24
Peak memory	217428 kb
Host	smart-80ecde39-f59d-4c10-b2b0-4b3415534704
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1578882910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1578882910
Directory	/workspace/114.edn_genbits/latest

Test location	/workspace/coverage/default/115.edn_genbits.145328270
Short name	T534
Test name
Test status
Simulation time	94294720 ps
CPU time	1.45 seconds
Started	Feb 07 12:49:36 PM PST 24
Finished	Feb 07 12:49:41 PM PST 24
Peak memory	217024 kb
Host	smart-61299d1d-c847-4fb5-9d25-b38a37f333e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=145328270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.145328270
Directory	/workspace/115.edn_genbits/latest

Test location	/workspace/coverage/default/116.edn_genbits.3053580785
Short name	T835
Test name
Test status
Simulation time	58081726 ps
CPU time	1.64 seconds
Started	Feb 07 12:49:36 PM PST 24
Finished	Feb 07 12:49:40 PM PST 24
Peak memory	216328 kb
Host	smart-ec8b1660-98a7-4a45-9d7b-3f492ff9b141
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3053580785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3053580785
Directory	/workspace/116.edn_genbits/latest

Test location	/workspace/coverage/default/117.edn_genbits.3564716904
Short name	T345
Test name
Test status
Simulation time	82972355 ps
CPU time	1.69 seconds
Started	Feb 07 12:49:44 PM PST 24
Finished	Feb 07 12:49:48 PM PST 24
Peak memory	216432 kb
Host	smart-3c26863a-714c-401c-8bf2-430ebf51ef78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3564716904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3564716904
Directory	/workspace/117.edn_genbits/latest

Test location	/workspace/coverage/default/118.edn_genbits.1057663108
Short name	T585
Test name
Test status
Simulation time	35636997 ps
CPU time	1.32 seconds
Started	Feb 07 12:49:34 PM PST 24
Finished	Feb 07 12:49:37 PM PST 24
Peak memory	216652 kb
Host	smart-c3d6cbea-22d0-4be2-9811-a78d4a9e4b9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1057663108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1057663108
Directory	/workspace/118.edn_genbits/latest

Test location	/workspace/coverage/default/119.edn_genbits.321696704
Short name	T528
Test name
Test status
Simulation time	37713913 ps
CPU time	1.36 seconds
Started	Feb 07 12:49:42 PM PST 24
Finished	Feb 07 12:49:46 PM PST 24
Peak memory	216420 kb
Host	smart-30e4a98d-08a8-4049-a17a-9fbc40dd5aa2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=321696704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.321696704
Directory	/workspace/119.edn_genbits/latest

Test location	/workspace/coverage/default/12.edn_alert_test.407713354
Short name	T556
Test name
Test status
Simulation time	67570446 ps
CPU time	0.87 seconds
Started	Feb 07 12:48:16 PM PST 24
Finished	Feb 07 12:48:18 PM PST 24
Peak memory	205888 kb
Host	smart-dfc391f5-8710-4aab-b12b-0f3a034eccc1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407713354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.407713354
Directory	/workspace/12.edn_alert_test/latest

Test location	/workspace/coverage/default/12.edn_disable.3512449029
Short name	T674
Test name
Test status
Simulation time	21743448 ps
CPU time	0.83 seconds
Started	Feb 07 12:48:18 PM PST 24
Finished	Feb 07 12:48:26 PM PST 24
Peak memory	215036 kb
Host	smart-59f26c2a-774d-48bd-bfb2-aa7de860ce6c
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512449029 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3512449029
Directory	/workspace/12.edn_disable/latest

Test location	/workspace/coverage/default/12.edn_disable_auto_req_mode.2240051746
Short name	T898
Test name
Test status
Simulation time	157105204 ps
CPU time	1.16 seconds
Started	Feb 07 12:48:15 PM PST 24
Finished	Feb 07 12:48:17 PM PST 24
Peak memory	215256 kb
Host	smart-cf5c1a03-f83e-44f7-b76f-090821b89a75
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240051746 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d isable_auto_req_mode.2240051746
Directory	/workspace/12.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/12.edn_err.737604457
Short name	T361
Test name
Test status
Simulation time	24043855 ps
CPU time	0.99 seconds
Started	Feb 07 12:48:18 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	217052 kb
Host	smart-e0abfbb7-62a9-4887-aad3-ca9a78c5884b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=737604457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.737604457
Directory	/workspace/12.edn_err/latest

Test location	/workspace/coverage/default/12.edn_genbits.77770761
Short name	T826
Test name
Test status
Simulation time	54342699 ps
CPU time	1.23 seconds
Started	Feb 07 12:48:18 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	216408 kb
Host	smart-4a43c6eb-577f-4748-b92f-26e4a83d0ab2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=77770761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.77770761
Directory	/workspace/12.edn_genbits/latest

Test location	/workspace/coverage/default/12.edn_intr.3926965164
Short name	T557
Test name
Test status
Simulation time	23492900 ps
CPU time	1.16 seconds
Started	Feb 07 12:48:26 PM PST 24
Finished	Feb 07 12:48:36 PM PST 24
Peak memory	215016 kb
Host	smart-382c9785-4e19-4ee6-9bbc-5a1808d5463a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3926965164 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3926965164
Directory	/workspace/12.edn_intr/latest

Test location	/workspace/coverage/default/12.edn_smoke.1955997440
Short name	T768
Test name
Test status
Simulation time	23826611 ps
CPU time	0.94 seconds
Started	Feb 07 12:48:23 PM PST 24
Finished	Feb 07 12:48:35 PM PST 24
Peak memory	214940 kb
Host	smart-c720509a-53f8-45c7-aba3-109803a65c92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1955997440 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1955997440
Directory	/workspace/12.edn_smoke/latest

Test location	/workspace/coverage/default/12.edn_stress_all.3773997490
Short name	T646
Test name
Test status
Simulation time	125971571 ps
CPU time	1.73 seconds
Started	Feb 07 12:48:19 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	215040 kb
Host	smart-ed684b84-fc8a-42a7-83bc-bcb032de985e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773997490 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3773997490
Directory	/workspace/12.edn_stress_all/latest

Test location	/workspace/coverage/default/12.edn_stress_all_with_rand_reset.749165144
Short name	T680
Test name
Test status
Simulation time	75918418196 ps
CPU time	1025.38 seconds
Started	Feb 07 12:48:21 PM PST 24
Finished	Feb 07 01:05:31 PM PST 24
Peak memory	223372 kb
Host	smart-54f40503-39af-4630-9069-e197bd63ad74
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749165144 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.749165144
Directory	/workspace/12.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/120.edn_genbits.3263052686
Short name	T80
Test name
Test status
Simulation time	60123083 ps
CPU time	1.34 seconds
Started	Feb 07 12:49:42 PM PST 24
Finished	Feb 07 12:49:46 PM PST 24
Peak memory	217996 kb
Host	smart-54dd5251-693d-4ee8-84ea-fdbb32cb06ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263052686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3263052686
Directory	/workspace/120.edn_genbits/latest

Test location	/workspace/coverage/default/121.edn_genbits.184615738
Short name	T565
Test name
Test status
Simulation time	40700365 ps
CPU time	1.26 seconds
Started	Feb 07 12:49:33 PM PST 24
Finished	Feb 07 12:49:36 PM PST 24
Peak memory	215248 kb
Host	smart-2bc46a16-198d-4d91-9ead-64f9f84eb3a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=184615738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.184615738
Directory	/workspace/121.edn_genbits/latest

Test location	/workspace/coverage/default/122.edn_genbits.3695383770
Short name	T808
Test name
Test status
Simulation time	68950840 ps
CPU time	2.49 seconds
Started	Feb 07 12:49:42 PM PST 24
Finished	Feb 07 12:49:47 PM PST 24
Peak memory	216784 kb
Host	smart-7ba21991-f13d-46e6-994c-7767e3895cbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3695383770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3695383770
Directory	/workspace/122.edn_genbits/latest

Test location	/workspace/coverage/default/123.edn_genbits.445780918
Short name	T442
Test name
Test status
Simulation time	41830487 ps
CPU time	1.7 seconds
Started	Feb 07 12:49:47 PM PST 24
Finished	Feb 07 12:49:50 PM PST 24
Peak memory	216508 kb
Host	smart-a1c025e1-2881-46ff-8e4e-262f9a84e8c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=445780918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.445780918
Directory	/workspace/123.edn_genbits/latest

Test location	/workspace/coverage/default/125.edn_genbits.980273688
Short name	T702
Test name
Test status
Simulation time	39263941 ps
CPU time	1.07 seconds
Started	Feb 07 12:49:43 PM PST 24
Finished	Feb 07 12:49:46 PM PST 24
Peak memory	215312 kb
Host	smart-3a74aa8d-cbfe-4594-bf5b-49d61f288c49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=980273688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.980273688
Directory	/workspace/125.edn_genbits/latest

Test location	/workspace/coverage/default/126.edn_genbits.869766187
Short name	T661
Test name
Test status
Simulation time	52826768 ps
CPU time	1.26 seconds
Started	Feb 07 12:49:40 PM PST 24
Finished	Feb 07 12:49:45 PM PST 24
Peak memory	216568 kb
Host	smart-9008eab6-0323-493d-811a-c69b02358cfa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=869766187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.869766187
Directory	/workspace/126.edn_genbits/latest

Test location	/workspace/coverage/default/127.edn_genbits.1164602347
Short name	T352
Test name
Test status
Simulation time	25076563 ps
CPU time	1.17 seconds
Started	Feb 07 12:49:51 PM PST 24
Finished	Feb 07 12:49:53 PM PST 24
Peak memory	215336 kb
Host	smart-6a96971e-a203-4bd7-840b-6aebc9c95b2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1164602347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1164602347
Directory	/workspace/127.edn_genbits/latest

Test location	/workspace/coverage/default/128.edn_genbits.302097703
Short name	T709
Test name
Test status
Simulation time	69715025 ps
CPU time	1.22 seconds
Started	Feb 07 12:49:44 PM PST 24
Finished	Feb 07 12:49:47 PM PST 24
Peak memory	216968 kb
Host	smart-ffae8dd5-9c1a-4e6f-ba25-fad87cbc15f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=302097703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.302097703
Directory	/workspace/128.edn_genbits/latest

Test location	/workspace/coverage/default/129.edn_genbits.226606306
Short name	T594
Test name
Test status
Simulation time	91117146 ps
CPU time	1.42 seconds
Started	Feb 07 12:49:34 PM PST 24
Finished	Feb 07 12:49:38 PM PST 24
Peak memory	215552 kb
Host	smart-f658ad07-63c4-46e5-85d2-5ce5cd9f97fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=226606306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.226606306
Directory	/workspace/129.edn_genbits/latest

Test location	/workspace/coverage/default/13.edn_alert.2282866046
Short name	T868
Test name
Test status
Simulation time	30198021 ps
CPU time	0.93 seconds
Started	Feb 07 12:48:19 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	205820 kb
Host	smart-080b5b71-7132-4140-8d25-8b27defa661a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2282866046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2282866046
Directory	/workspace/13.edn_alert/latest

Test location	/workspace/coverage/default/13.edn_alert_test.2957450301
Short name	T782
Test name
Test status
Simulation time	67302788 ps
CPU time	0.9 seconds
Started	Feb 07 12:48:14 PM PST 24
Finished	Feb 07 12:48:16 PM PST 24
Peak memory	205460 kb
Host	smart-22398ace-16bf-444c-9f61-d03719df20ff
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957450301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2957450301
Directory	/workspace/13.edn_alert_test/latest

Test location	/workspace/coverage/default/13.edn_disable_auto_req_mode.3981372588
Short name	T529
Test name
Test status
Simulation time	56290596 ps
CPU time	1.14 seconds
Started	Feb 07 12:48:26 PM PST 24
Finished	Feb 07 12:48:36 PM PST 24
Peak memory	215432 kb
Host	smart-e0f856d0-fd4b-4703-b2db-eee8a2562a3c
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981372588 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d isable_auto_req_mode.3981372588
Directory	/workspace/13.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/13.edn_err.3180885082
Short name	T473
Test name
Test status
Simulation time	24312056 ps
CPU time	0.93 seconds
Started	Feb 07 12:48:26 PM PST 24
Finished	Feb 07 12:48:36 PM PST 24
Peak memory	216840 kb
Host	smart-618a2187-c469-45f7-b9bc-be4f27609705
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3180885082 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3180885082
Directory	/workspace/13.edn_err/latest

Test location	/workspace/coverage/default/13.edn_genbits.2058854185
Short name	T615
Test name
Test status
Simulation time	203964556 ps
CPU time	1.55 seconds
Started	Feb 07 12:48:28 PM PST 24
Finished	Feb 07 12:48:38 PM PST 24
Peak memory	216628 kb
Host	smart-d1b78f89-dc91-41ee-8ff2-2a872c7f6bb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2058854185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2058854185
Directory	/workspace/13.edn_genbits/latest

Test location	/workspace/coverage/default/13.edn_intr.2500959815
Short name	T66
Test name
Test status
Simulation time	31248693 ps
CPU time	0.85 seconds
Started	Feb 07 12:48:15 PM PST 24
Finished	Feb 07 12:48:17 PM PST 24
Peak memory	215180 kb
Host	smart-576b3f7c-b728-46c7-8894-74db3e3c6a49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2500959815 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2500959815
Directory	/workspace/13.edn_intr/latest

Test location	/workspace/coverage/default/13.edn_smoke.502890029
Short name	T831
Test name
Test status
Simulation time	32782403 ps
CPU time	0.92 seconds
Started	Feb 07 12:48:29 PM PST 24
Finished	Feb 07 12:48:37 PM PST 24
Peak memory	215012 kb
Host	smart-7dded401-f3ed-452c-9fb9-0a0254e0cf1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=502890029 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.502890029
Directory	/workspace/13.edn_smoke/latest

Test location	/workspace/coverage/default/13.edn_stress_all.2651159354
Short name	T492
Test name
Test status
Simulation time	628635087 ps
CPU time	3.63 seconds
Started	Feb 07 12:48:16 PM PST 24
Finished	Feb 07 12:48:21 PM PST 24
Peak memory	216660 kb
Host	smart-aafa008c-d4e3-4949-a846-04b0f66c2b4c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651159354 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2651159354
Directory	/workspace/13.edn_stress_all/latest

Test location	/workspace/coverage/default/13.edn_stress_all_with_rand_reset.3845206436
Short name	T202
Test name
Test status
Simulation time	39778873487 ps
CPU time	465.67 seconds
Started	Feb 07 12:48:22 PM PST 24
Finished	Feb 07 12:56:12 PM PST 24
Peak memory	218716 kb
Host	smart-15715923-5c06-493f-a1fe-0469547fbc4c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845206436 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3845206436
Directory	/workspace/13.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/130.edn_genbits.3512606411
Short name	T656
Test name
Test status
Simulation time	100735815 ps
CPU time	3.07 seconds
Started	Feb 07 12:49:45 PM PST 24
Finished	Feb 07 12:49:51 PM PST 24
Peak memory	216796 kb
Host	smart-161f00fa-530d-45f5-af4c-82b390c48294
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3512606411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3512606411
Directory	/workspace/130.edn_genbits/latest

Test location	/workspace/coverage/default/131.edn_genbits.1760036232
Short name	T173
Test name
Test status
Simulation time	123158188 ps
CPU time	2.67 seconds
Started	Feb 07 12:49:46 PM PST 24
Finished	Feb 07 12:49:56 PM PST 24
Peak memory	218428 kb
Host	smart-6adfee5b-5c64-4384-871c-400aa9469786
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1760036232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1760036232
Directory	/workspace/131.edn_genbits/latest

Test location	/workspace/coverage/default/132.edn_genbits.3361548214
Short name	T185
Test name
Test status
Simulation time	28953321 ps
CPU time	1.14 seconds
Started	Feb 07 12:49:42 PM PST 24
Finished	Feb 07 12:49:46 PM PST 24
Peak memory	215608 kb
Host	smart-4ccba424-916a-4dfe-9c3a-dbf4220f938a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3361548214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3361548214
Directory	/workspace/132.edn_genbits/latest

Test location	/workspace/coverage/default/133.edn_genbits.1372737479
Short name	T783
Test name
Test status
Simulation time	65829078 ps
CPU time	1.37 seconds
Started	Feb 07 12:49:38 PM PST 24
Finished	Feb 07 12:49:43 PM PST 24
Peak memory	216848 kb
Host	smart-e270f1bd-abbd-4b94-ad08-f1a1d9dda649
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1372737479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1372737479
Directory	/workspace/133.edn_genbits/latest

Test location	/workspace/coverage/default/134.edn_genbits.2001926331
Short name	T717
Test name
Test status
Simulation time	102852370 ps
CPU time	1.11 seconds
Started	Feb 07 12:49:38 PM PST 24
Finished	Feb 07 12:49:42 PM PST 24
Peak memory	215260 kb
Host	smart-ad19bfb5-0637-4757-a717-3b57297356c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2001926331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2001926331
Directory	/workspace/134.edn_genbits/latest

Test location	/workspace/coverage/default/135.edn_genbits.2641175453
Short name	T814
Test name
Test status
Simulation time	136220140 ps
CPU time	1.1 seconds
Started	Feb 07 12:49:42 PM PST 24
Finished	Feb 07 12:49:45 PM PST 24
Peak memory	215492 kb
Host	smart-e4274615-7dcf-4f71-ad49-a6c28efb7150
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2641175453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2641175453
Directory	/workspace/135.edn_genbits/latest

Test location	/workspace/coverage/default/137.edn_genbits.473374820
Short name	T855
Test name
Test status
Simulation time	194374616 ps
CPU time	1.61 seconds
Started	Feb 07 12:49:50 PM PST 24
Finished	Feb 07 12:49:53 PM PST 24
Peak memory	216860 kb
Host	smart-ae38014d-cd50-438d-b3c0-0525df580275
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=473374820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.473374820
Directory	/workspace/137.edn_genbits/latest

Test location	/workspace/coverage/default/139.edn_genbits.2214040289
Short name	T693
Test name
Test status
Simulation time	77437592 ps
CPU time	1.5 seconds
Started	Feb 07 12:49:43 PM PST 24
Finished	Feb 07 12:49:46 PM PST 24
Peak memory	215636 kb
Host	smart-8426e702-4a5c-4e50-8359-b1a4e065fb90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2214040289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2214040289
Directory	/workspace/139.edn_genbits/latest

Test location	/workspace/coverage/default/14.edn_alert_test.3315161326
Short name	T650
Test name
Test status
Simulation time	67839334 ps
CPU time	0.84 seconds
Started	Feb 07 12:48:19 PM PST 24
Finished	Feb 07 12:48:26 PM PST 24
Peak memory	205316 kb
Host	smart-be83738c-382a-4a1c-959a-77d80457576f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315161326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3315161326
Directory	/workspace/14.edn_alert_test/latest

Test location	/workspace/coverage/default/14.edn_disable.2568886746
Short name	T623
Test name
Test status
Simulation time	31576778 ps
CPU time	0.83 seconds
Started	Feb 07 12:48:32 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	214864 kb
Host	smart-ff9ba7db-459d-4cb4-b0d8-885b44924f26
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568886746 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2568886746
Directory	/workspace/14.edn_disable/latest

Test location	/workspace/coverage/default/14.edn_disable_auto_req_mode.822245408
Short name	T8
Test name
Test status
Simulation time	36823908 ps
CPU time	1.27 seconds
Started	Feb 07 12:48:16 PM PST 24
Finished	Feb 07 12:48:18 PM PST 24
Peak memory	216300 kb
Host	smart-3e819622-cb4b-4710-a010-5fc2717f2370
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822245408 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di sable_auto_req_mode.822245408
Directory	/workspace/14.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/14.edn_err.3992050737
Short name	T420
Test name
Test status
Simulation time	18905709 ps
CPU time	0.97 seconds
Started	Feb 07 12:48:28 PM PST 24
Finished	Feb 07 12:48:37 PM PST 24
Peak memory	216672 kb
Host	smart-4db9c48d-ab01-4819-a2bb-4a0da9176a74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3992050737 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3992050737
Directory	/workspace/14.edn_err/latest

Test location	/workspace/coverage/default/14.edn_genbits.4060912127
Short name	T659
Test name
Test status
Simulation time	40172501 ps
CPU time	1.38 seconds
Started	Feb 07 12:48:20 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	216528 kb
Host	smart-d09ed99d-ba30-46dc-83c1-227dd45f7706
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4060912127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.4060912127
Directory	/workspace/14.edn_genbits/latest

Test location	/workspace/coverage/default/14.edn_intr.3250177003
Short name	T64
Test name
Test status
Simulation time	21965242 ps
CPU time	1.06 seconds
Started	Feb 07 12:48:28 PM PST 24
Finished	Feb 07 12:48:37 PM PST 24
Peak memory	215208 kb
Host	smart-b154b4ef-0b7a-48fe-83fa-2fdafe711cdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3250177003 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3250177003
Directory	/workspace/14.edn_intr/latest

Test location	/workspace/coverage/default/14.edn_smoke.2789837456
Short name	T860
Test name
Test status
Simulation time	18618096 ps
CPU time	0.97 seconds
Started	Feb 07 12:48:17 PM PST 24
Finished	Feb 07 12:48:22 PM PST 24
Peak memory	215000 kb
Host	smart-0225d28e-c474-47f9-bfb6-156b44e07d04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789837456 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2789837456
Directory	/workspace/14.edn_smoke/latest

Test location	/workspace/coverage/default/14.edn_stress_all.3072009492
Short name	T925
Test name
Test status
Simulation time	788011264 ps
CPU time	4.32 seconds
Started	Feb 07 12:48:18 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	215144 kb
Host	smart-5c4a734d-26c9-42b3-87f6-6aba31bb55f2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072009492 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3072009492
Directory	/workspace/14.edn_stress_all/latest

Test location	/workspace/coverage/default/14.edn_stress_all_with_rand_reset.1288955134
Short name	T407
Test name
Test status
Simulation time	305366736830 ps
CPU time	1589.82 seconds
Started	Feb 07 12:48:28 PM PST 24
Finished	Feb 07 01:15:06 PM PST 24
Peak memory	225380 kb
Host	smart-9ebaf16c-dd54-4919-aff8-b131a75897e5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288955134 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1288955134
Directory	/workspace/14.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/140.edn_genbits.3885433022
Short name	T663
Test name
Test status
Simulation time	47328528 ps
CPU time	1.06 seconds
Started	Feb 07 12:49:43 PM PST 24
Finished	Feb 07 12:49:46 PM PST 24
Peak memory	215348 kb
Host	smart-64831ec0-4e79-47b9-962f-784fbc97d3eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3885433022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3885433022
Directory	/workspace/140.edn_genbits/latest

Test location	/workspace/coverage/default/141.edn_genbits.3027777804
Short name	T193
Test name
Test status
Simulation time	89881749 ps
CPU time	1.43 seconds
Started	Feb 07 12:49:37 PM PST 24
Finished	Feb 07 12:49:42 PM PST 24
Peak memory	215556 kb
Host	smart-e164fea0-494b-44cb-a5f6-c798ed747e84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3027777804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3027777804
Directory	/workspace/141.edn_genbits/latest

Test location	/workspace/coverage/default/142.edn_genbits.4256173580
Short name	T608
Test name
Test status
Simulation time	298531715 ps
CPU time	3.49 seconds
Started	Feb 07 12:49:51 PM PST 24
Finished	Feb 07 12:49:55 PM PST 24
Peak memory	215768 kb
Host	smart-d7c8605a-cd42-4fb5-94a0-0028ce4f79d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4256173580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.4256173580
Directory	/workspace/142.edn_genbits/latest

Test location	/workspace/coverage/default/143.edn_genbits.1861455764
Short name	T679
Test name
Test status
Simulation time	33213452 ps
CPU time	1.4 seconds
Started	Feb 07 12:49:40 PM PST 24
Finished	Feb 07 12:49:45 PM PST 24
Peak memory	216416 kb
Host	smart-72171f60-8089-4f71-b4ba-fe48c6e7b2e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1861455764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1861455764
Directory	/workspace/143.edn_genbits/latest

Test location	/workspace/coverage/default/144.edn_genbits.839076557
Short name	T931
Test name
Test status
Simulation time	87715382 ps
CPU time	0.98 seconds
Started	Feb 07 12:49:46 PM PST 24
Finished	Feb 07 12:49:49 PM PST 24
Peak memory	215332 kb
Host	smart-8cc98aff-037a-4402-a596-a194e230774c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=839076557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.839076557
Directory	/workspace/144.edn_genbits/latest

Test location	/workspace/coverage/default/145.edn_genbits.2574567667
Short name	T710
Test name
Test status
Simulation time	162399610 ps
CPU time	1.03 seconds
Started	Feb 07 12:49:45 PM PST 24
Finished	Feb 07 12:49:49 PM PST 24
Peak memory	215452 kb
Host	smart-40b048b9-0897-4b30-8a9e-da454b797ff3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2574567667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2574567667
Directory	/workspace/145.edn_genbits/latest

Test location	/workspace/coverage/default/147.edn_genbits.2623463833
Short name	T549
Test name
Test status
Simulation time	32842964 ps
CPU time	1.36 seconds
Started	Feb 07 12:49:40 PM PST 24
Finished	Feb 07 12:49:45 PM PST 24
Peak memory	218096 kb
Host	smart-1206f12a-2732-4b07-b1cf-988d72e8379d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2623463833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2623463833
Directory	/workspace/147.edn_genbits/latest

Test location	/workspace/coverage/default/148.edn_genbits.1057928673
Short name	T530
Test name
Test status
Simulation time	69051673 ps
CPU time	1.26 seconds
Started	Feb 07 12:49:43 PM PST 24
Finished	Feb 07 12:49:47 PM PST 24
Peak memory	216692 kb
Host	smart-d5306400-2d46-4791-b9e3-40b17a97f2bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1057928673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1057928673
Directory	/workspace/148.edn_genbits/latest

Test location	/workspace/coverage/default/149.edn_genbits.3283304028
Short name	T566
Test name
Test status
Simulation time	269359845 ps
CPU time	1.12 seconds
Started	Feb 07 12:49:46 PM PST 24
Finished	Feb 07 12:49:49 PM PST 24
Peak memory	215080 kb
Host	smart-829dd0ef-e3f3-400c-a880-709291da125a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3283304028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3283304028
Directory	/workspace/149.edn_genbits/latest

Test location	/workspace/coverage/default/15.edn_alert_test.3718018138
Short name	T468
Test name
Test status
Simulation time	63654019 ps
CPU time	0.84 seconds
Started	Feb 07 12:48:18 PM PST 24
Finished	Feb 07 12:48:24 PM PST 24
Peak memory	205748 kb
Host	smart-609dd683-0389-4c16-b77d-2c4c890ac110
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718018138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3718018138
Directory	/workspace/15.edn_alert_test/latest

Test location	/workspace/coverage/default/15.edn_disable.1774792078
Short name	T37
Test name
Test status
Simulation time	19974022 ps
CPU time	0.82 seconds
Started	Feb 07 12:48:17 PM PST 24
Finished	Feb 07 12:48:19 PM PST 24
Peak memory	214740 kb
Host	smart-8f5a3293-888e-4e12-82bd-7b2472486ee3
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774792078 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1774792078
Directory	/workspace/15.edn_disable/latest

Test location	/workspace/coverage/default/15.edn_disable_auto_req_mode.1719781842
Short name	T798
Test name
Test status
Simulation time	63628219 ps
CPU time	1.26 seconds
Started	Feb 07 12:48:18 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	215248 kb
Host	smart-711ec1ff-f9b4-42fe-970b-c3e2c745dff5
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719781842 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d isable_auto_req_mode.1719781842
Directory	/workspace/15.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/15.edn_err.1462581392
Short name	T856
Test name
Test status
Simulation time	36823825 ps
CPU time	1.06 seconds
Started	Feb 07 12:48:22 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	221928 kb
Host	smart-2220cd62-7222-45d2-9806-f3c10dacb247
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1462581392 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1462581392
Directory	/workspace/15.edn_err/latest

Test location	/workspace/coverage/default/15.edn_genbits.3999177123
Short name	T595
Test name
Test status
Simulation time	105315557 ps
CPU time	1.18 seconds
Started	Feb 07 12:48:19 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	216628 kb
Host	smart-eee0bd36-9a55-4614-9713-9cc4056a4381
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3999177123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3999177123
Directory	/workspace/15.edn_genbits/latest

Test location	/workspace/coverage/default/15.edn_intr.1276882349
Short name	T475
Test name
Test status
Simulation time	22843678 ps
CPU time	1.11 seconds
Started	Feb 07 12:48:19 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	215288 kb
Host	smart-e246cf51-5544-44dd-b146-35277107b23e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1276882349 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1276882349
Directory	/workspace/15.edn_intr/latest

Test location	/workspace/coverage/default/15.edn_smoke.2398008129
Short name	T452
Test name
Test status
Simulation time	29623575 ps
CPU time	1 seconds
Started	Feb 07 12:48:18 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	214944 kb
Host	smart-1e630419-f4b2-4819-bfc5-5beaa7192b4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2398008129 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2398008129
Directory	/workspace/15.edn_smoke/latest

Test location	/workspace/coverage/default/15.edn_stress_all.353668799
Short name	T603
Test name
Test status
Simulation time	1356252895 ps
CPU time	4.2 seconds
Started	Feb 07 12:48:17 PM PST 24
Finished	Feb 07 12:48:22 PM PST 24
Peak memory	218156 kb
Host	smart-0d70ea8a-36bb-4460-87e4-ba0c9fd2723c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353668799 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.353668799
Directory	/workspace/15.edn_stress_all/latest

Test location	/workspace/coverage/default/150.edn_genbits.1620196005
Short name	T410
Test name
Test status
Simulation time	25298337 ps
CPU time	1.19 seconds
Started	Feb 07 12:49:59 PM PST 24
Finished	Feb 07 12:50:03 PM PST 24
Peak memory	218124 kb
Host	smart-4dfd09c6-3d78-4b08-820e-9d6d62220bb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1620196005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1620196005
Directory	/workspace/150.edn_genbits/latest

Test location	/workspace/coverage/default/151.edn_genbits.2669409868
Short name	T638
Test name
Test status
Simulation time	49170719 ps
CPU time	1.65 seconds
Started	Feb 07 12:49:52 PM PST 24
Finished	Feb 07 12:49:54 PM PST 24
Peak memory	216696 kb
Host	smart-a67300f1-02fd-4063-95be-473a09e661bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2669409868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2669409868
Directory	/workspace/151.edn_genbits/latest

Test location	/workspace/coverage/default/152.edn_genbits.800789829
Short name	T606
Test name
Test status
Simulation time	86545726 ps
CPU time	1.19 seconds
Started	Feb 07 12:49:40 PM PST 24
Finished	Feb 07 12:49:45 PM PST 24
Peak memory	216624 kb
Host	smart-45dbc52e-c393-424b-b176-d0db3a87a349
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=800789829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.800789829
Directory	/workspace/152.edn_genbits/latest

Test location	/workspace/coverage/default/153.edn_genbits.2882692107
Short name	T466
Test name
Test status
Simulation time	63860537 ps
CPU time	1.21 seconds
Started	Feb 07 12:50:05 PM PST 24
Finished	Feb 07 12:50:07 PM PST 24
Peak memory	215444 kb
Host	smart-b165c1bf-bfc3-4a5b-9f95-a1a93a2eccf7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2882692107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2882692107
Directory	/workspace/153.edn_genbits/latest

Test location	/workspace/coverage/default/155.edn_genbits.3765677715
Short name	T524
Test name
Test status
Simulation time	49367298 ps
CPU time	1.18 seconds
Started	Feb 07 12:49:44 PM PST 24
Finished	Feb 07 12:49:48 PM PST 24
Peak memory	216748 kb
Host	smart-f2a77734-73fc-4bc0-855d-0c89c95e9d92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3765677715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3765677715
Directory	/workspace/155.edn_genbits/latest

Test location	/workspace/coverage/default/156.edn_genbits.3329600457
Short name	T909
Test name
Test status
Simulation time	73836644 ps
CPU time	2.48 seconds
Started	Feb 07 12:49:52 PM PST 24
Finished	Feb 07 12:49:55 PM PST 24
Peak memory	216588 kb
Host	smart-e76e7fbb-193e-4f4d-aa83-7b05bbed4996
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3329600457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3329600457
Directory	/workspace/156.edn_genbits/latest

Test location	/workspace/coverage/default/157.edn_genbits.3835381906
Short name	T718
Test name
Test status
Simulation time	42111162 ps
CPU time	1.55 seconds
Started	Feb 07 12:49:49 PM PST 24
Finished	Feb 07 12:49:52 PM PST 24
Peak memory	216816 kb
Host	smart-9400edce-449f-48f4-a09e-5ba1a69a46be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3835381906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3835381906
Directory	/workspace/157.edn_genbits/latest

Test location	/workspace/coverage/default/158.edn_genbits.1492606396
Short name	T405
Test name
Test status
Simulation time	40201310 ps
CPU time	1.11 seconds
Started	Feb 07 12:49:47 PM PST 24
Finished	Feb 07 12:49:49 PM PST 24
Peak memory	215292 kb
Host	smart-0ae7d30f-c435-497a-a2cf-e51c213408d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1492606396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1492606396
Directory	/workspace/158.edn_genbits/latest

Test location	/workspace/coverage/default/159.edn_genbits.246238769
Short name	T625
Test name
Test status
Simulation time	27076259 ps
CPU time	1 seconds
Started	Feb 07 12:49:57 PM PST 24
Finished	Feb 07 12:49:59 PM PST 24
Peak memory	215328 kb
Host	smart-4ab270af-b669-49af-a919-1dc9a168ee15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=246238769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.246238769
Directory	/workspace/159.edn_genbits/latest

Test location	/workspace/coverage/default/16.edn_alert.605129700
Short name	T834
Test name
Test status
Simulation time	23700563 ps
CPU time	1.07 seconds
Started	Feb 07 12:48:21 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	205952 kb
Host	smart-13e989d7-b08c-4522-a4cb-0d862c4ac16d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=605129700 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.605129700
Directory	/workspace/16.edn_alert/latest

Test location	/workspace/coverage/default/16.edn_alert_test.3384709634
Short name	T780
Test name
Test status
Simulation time	25751867 ps
CPU time	1.07 seconds
Started	Feb 07 12:48:19 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	205868 kb
Host	smart-b97086ef-bb13-4616-bbd5-bdddce51eee4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384709634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3384709634
Directory	/workspace/16.edn_alert_test/latest

Test location	/workspace/coverage/default/16.edn_disable.4125356490
Short name	T123
Test name
Test status
Simulation time	39954980 ps
CPU time	0.87 seconds
Started	Feb 07 12:48:28 PM PST 24
Finished	Feb 07 12:48:37 PM PST 24
Peak memory	215168 kb
Host	smart-4beb798f-ed05-4ea2-9cb2-95c3cac6ed0b
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125356490 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.4125356490
Directory	/workspace/16.edn_disable/latest

Test location	/workspace/coverage/default/16.edn_disable_auto_req_mode.3714809851
Short name	T762
Test name
Test status
Simulation time	50579121 ps
CPU time	1.2 seconds
Started	Feb 07 12:48:28 PM PST 24
Finished	Feb 07 12:48:38 PM PST 24
Peak memory	215408 kb
Host	smart-2f3da588-d6e3-4384-80e5-4f73868cc381
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714809851 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d isable_auto_req_mode.3714809851
Directory	/workspace/16.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/16.edn_genbits.373134160
Short name	T35
Test name
Test status
Simulation time	44563442 ps
CPU time	1.41 seconds
Started	Feb 07 12:48:17 PM PST 24
Finished	Feb 07 12:48:24 PM PST 24
Peak memory	215392 kb
Host	smart-1d3a502a-15b4-44b3-a4a2-5690a5a3f61a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=373134160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.373134160
Directory	/workspace/16.edn_genbits/latest

Test location	/workspace/coverage/default/16.edn_smoke.3930667480
Short name	T389
Test name
Test status
Simulation time	39297486 ps
CPU time	0.86 seconds
Started	Feb 07 12:48:19 PM PST 24
Finished	Feb 07 12:48:26 PM PST 24
Peak memory	214676 kb
Host	smart-9e0f558c-b839-4291-bc56-a611e6785f99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3930667480 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3930667480
Directory	/workspace/16.edn_smoke/latest

Test location	/workspace/coverage/default/16.edn_stress_all.3973707457
Short name	T948
Test name
Test status
Simulation time	972032809 ps
CPU time	5.29 seconds
Started	Feb 07 12:48:18 PM PST 24
Finished	Feb 07 12:48:31 PM PST 24
Peak memory	215108 kb
Host	smart-986844e6-381f-4303-9db4-1e4f1d88a88f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973707457 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3973707457
Directory	/workspace/16.edn_stress_all/latest

Test location	/workspace/coverage/default/16.edn_stress_all_with_rand_reset.418822149
Short name	T501
Test name
Test status
Simulation time	260114252356 ps
CPU time	644.24 seconds
Started	Feb 07 12:48:18 PM PST 24
Finished	Feb 07 12:59:10 PM PST 24
Peak memory	219836 kb
Host	smart-40b51113-450b-4d75-a4d0-50fda5bbb2eb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418822149 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.418822149
Directory	/workspace/16.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/160.edn_genbits.171641765
Short name	T77
Test name
Test status
Simulation time	69542582 ps
CPU time	1 seconds
Started	Feb 07 12:49:51 PM PST 24
Finished	Feb 07 12:49:53 PM PST 24
Peak memory	215512 kb
Host	smart-de1067c2-828e-407d-802f-aebf2518694c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=171641765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.171641765
Directory	/workspace/160.edn_genbits/latest

Test location	/workspace/coverage/default/162.edn_genbits.3744700288
Short name	T171
Test name
Test status
Simulation time	56166439 ps
CPU time	1.36 seconds
Started	Feb 07 12:49:47 PM PST 24
Finished	Feb 07 12:49:50 PM PST 24
Peak memory	216664 kb
Host	smart-4eee525f-a62e-44cb-9900-ebe50bacbc7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3744700288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3744700288
Directory	/workspace/162.edn_genbits/latest

Test location	/workspace/coverage/default/163.edn_genbits.1637207803
Short name	T57
Test name
Test status
Simulation time	72590601 ps
CPU time	1.03 seconds
Started	Feb 07 12:50:05 PM PST 24
Finished	Feb 07 12:50:07 PM PST 24
Peak memory	215552 kb
Host	smart-5d91fb27-e07c-4409-92eb-95c0379e98d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1637207803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1637207803
Directory	/workspace/163.edn_genbits/latest

Test location	/workspace/coverage/default/164.edn_genbits.1164357970
Short name	T635
Test name
Test status
Simulation time	22269642 ps
CPU time	1.08 seconds
Started	Feb 07 12:49:56 PM PST 24
Finished	Feb 07 12:49:58 PM PST 24
Peak memory	214992 kb
Host	smart-e9cc4a24-d764-4c31-8bba-767f2d10ac66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1164357970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1164357970
Directory	/workspace/164.edn_genbits/latest

Test location	/workspace/coverage/default/165.edn_genbits.675499080
Short name	T539
Test name
Test status
Simulation time	96043405 ps
CPU time	1.33 seconds
Started	Feb 07 12:50:06 PM PST 24
Finished	Feb 07 12:50:08 PM PST 24
Peak memory	216688 kb
Host	smart-5dedd15f-53b4-40a1-ab6a-62d040d9cc53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=675499080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.675499080
Directory	/workspace/165.edn_genbits/latest

Test location	/workspace/coverage/default/166.edn_genbits.2264095903
Short name	T721
Test name
Test status
Simulation time	43150167 ps
CPU time	1.68 seconds
Started	Feb 07 12:49:36 PM PST 24
Finished	Feb 07 12:49:41 PM PST 24
Peak memory	216592 kb
Host	smart-00635736-77bc-41fa-9add-1172df12f599
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2264095903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2264095903
Directory	/workspace/166.edn_genbits/latest

Test location	/workspace/coverage/default/167.edn_genbits.1525916180
Short name	T504
Test name
Test status
Simulation time	48201669 ps
CPU time	1.35 seconds
Started	Feb 07 12:49:43 PM PST 24
Finished	Feb 07 12:49:46 PM PST 24
Peak memory	216440 kb
Host	smart-8298f0bb-8b1f-4541-9cef-2382227acf4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1525916180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1525916180
Directory	/workspace/167.edn_genbits/latest

Test location	/workspace/coverage/default/168.edn_genbits.648636631
Short name	T744
Test name
Test status
Simulation time	113406483 ps
CPU time	1.25 seconds
Started	Feb 07 12:49:34 PM PST 24
Finished	Feb 07 12:49:37 PM PST 24
Peak memory	215488 kb
Host	smart-31de8fb2-1ec2-45db-9307-89186b13cf45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=648636631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.648636631
Directory	/workspace/168.edn_genbits/latest

Test location	/workspace/coverage/default/169.edn_genbits.4088577434
Short name	T447
Test name
Test status
Simulation time	118489515 ps
CPU time	1.14 seconds
Started	Feb 07 12:49:36 PM PST 24
Finished	Feb 07 12:49:40 PM PST 24
Peak memory	215392 kb
Host	smart-17006d4d-7188-4817-bdee-a2d0b981f4f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4088577434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.4088577434
Directory	/workspace/169.edn_genbits/latest

Test location	/workspace/coverage/default/17.edn_alert.2035514794
Short name	T828
Test name
Test status
Simulation time	123720506 ps
CPU time	1.03 seconds
Started	Feb 07 12:48:20 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	205960 kb
Host	smart-8920f4a8-b592-4de9-8827-d3280e03d543
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2035514794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2035514794
Directory	/workspace/17.edn_alert/latest

Test location	/workspace/coverage/default/17.edn_alert_test.2113403913
Short name	T672
Test name
Test status
Simulation time	14429346 ps
CPU time	0.86 seconds
Started	Feb 07 12:48:21 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	205012 kb
Host	smart-edeb63a5-aa1a-4776-9700-eded0afccbf2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113403913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2113403913
Directory	/workspace/17.edn_alert_test/latest

Test location	/workspace/coverage/default/17.edn_disable.4143078641
Short name	T106
Test name
Test status
Simulation time	18255483 ps
CPU time	0.82 seconds
Started	Feb 07 12:48:21 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	214828 kb
Host	smart-d1e6ffd0-ef83-4379-be77-aeb93fbae6b7
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143078641 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.4143078641
Directory	/workspace/17.edn_disable/latest

Test location	/workspace/coverage/default/17.edn_disable_auto_req_mode.1733817308
Short name	T544
Test name
Test status
Simulation time	105596304 ps
CPU time	1.06 seconds
Started	Feb 07 12:48:31 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	215140 kb
Host	smart-d7b1c0be-28bf-4618-8444-b14971e7c5c6
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733817308 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d isable_auto_req_mode.1733817308
Directory	/workspace/17.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/17.edn_err.3386074062
Short name	T818
Test name
Test status
Simulation time	87582720 ps
CPU time	0.93 seconds
Started	Feb 07 12:48:18 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	215188 kb
Host	smart-6d456667-b7cf-4ff1-b432-d3a5eade9a55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3386074062 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3386074062
Directory	/workspace/17.edn_err/latest

Test location	/workspace/coverage/default/17.edn_genbits.2674808495
Short name	T199
Test name
Test status
Simulation time	78519994 ps
CPU time	1.49 seconds
Started	Feb 07 12:48:21 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	216996 kb
Host	smart-fdd473ef-f43c-4749-8abb-c17ce45fe120
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2674808495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2674808495
Directory	/workspace/17.edn_genbits/latest

Test location	/workspace/coverage/default/17.edn_intr.723756146
Short name	T65
Test name
Test status
Simulation time	22007582 ps
CPU time	1.11 seconds
Started	Feb 07 12:48:18 PM PST 24
Finished	Feb 07 12:48:25 PM PST 24
Peak memory	215304 kb
Host	smart-793ad13d-106d-4198-88c7-c908069ad994
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=723756146 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.723756146
Directory	/workspace/17.edn_intr/latest

Test location	/workspace/coverage/default/17.edn_smoke.272469557
Short name	T922
Test name
Test status
Simulation time	15723684 ps
CPU time	0.93 seconds
Started	Feb 07 12:48:21 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	215044 kb
Host	smart-e7e5d851-27f5-42c3-9562-351d6c0579df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=272469557 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.272469557
Directory	/workspace/17.edn_smoke/latest

Test location	/workspace/coverage/default/17.edn_stress_all.4266042412
Short name	T165
Test name
Test status
Simulation time	283312231 ps
CPU time	5.27 seconds
Started	Feb 07 12:48:18 PM PST 24
Finished	Feb 07 12:48:29 PM PST 24
Peak memory	215004 kb
Host	smart-6960b114-5f03-42e3-b684-9778536dde01
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266042412 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.4266042412
Directory	/workspace/17.edn_stress_all/latest

Test location	/workspace/coverage/default/17.edn_stress_all_with_rand_reset.2327887537
Short name	T817
Test name
Test status
Simulation time	71539907747 ps
CPU time	1611.22 seconds
Started	Feb 07 12:48:20 PM PST 24
Finished	Feb 07 01:15:17 PM PST 24
Peak memory	222556 kb
Host	smart-1623fa48-eb61-42ab-8a01-a0e0c25d6d16
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327887537 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2327887537
Directory	/workspace/17.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/170.edn_genbits.2914909753
Short name	T462
Test name
Test status
Simulation time	69333398 ps
CPU time	1.54 seconds
Started	Feb 07 12:49:44 PM PST 24
Finished	Feb 07 12:49:48 PM PST 24
Peak memory	216860 kb
Host	smart-ff31c823-376b-446a-8a3c-e7b48967e39d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2914909753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2914909753
Directory	/workspace/170.edn_genbits/latest

Test location	/workspace/coverage/default/171.edn_genbits.3370233850
Short name	T216
Test name
Test status
Simulation time	47403952 ps
CPU time	1.84 seconds
Started	Feb 07 12:49:44 PM PST 24
Finished	Feb 07 12:49:49 PM PST 24
Peak memory	216528 kb
Host	smart-b7d7d5e5-ce27-41f5-898d-422ce173786e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3370233850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3370233850
Directory	/workspace/171.edn_genbits/latest

Test location	/workspace/coverage/default/172.edn_genbits.3424849052
Short name	T203
Test name
Test status
Simulation time	120059156 ps
CPU time	2.36 seconds
Started	Feb 07 12:49:37 PM PST 24
Finished	Feb 07 12:49:43 PM PST 24
Peak memory	215856 kb
Host	smart-80eeb0a5-16e0-40d7-aa49-57bd32281158
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3424849052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3424849052
Directory	/workspace/172.edn_genbits/latest

Test location	/workspace/coverage/default/173.edn_genbits.2431128923
Short name	T851
Test name
Test status
Simulation time	63944212 ps
CPU time	1.24 seconds
Started	Feb 07 12:49:44 PM PST 24
Finished	Feb 07 12:49:47 PM PST 24
Peak memory	215556 kb
Host	smart-f274260d-96ed-43d7-ac9c-c101abe338c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2431128923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2431128923
Directory	/workspace/173.edn_genbits/latest

Test location	/workspace/coverage/default/174.edn_genbits.3876232494
Short name	T934
Test name
Test status
Simulation time	63693446 ps
CPU time	1.14 seconds
Started	Feb 07 12:49:44 PM PST 24
Finished	Feb 07 12:49:47 PM PST 24
Peak memory	216648 kb
Host	smart-648254be-69f1-47a7-975b-e290c8f1b09a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3876232494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3876232494
Directory	/workspace/174.edn_genbits/latest

Test location	/workspace/coverage/default/175.edn_genbits.3964196557
Short name	T804
Test name
Test status
Simulation time	23810841 ps
CPU time	1.12 seconds
Started	Feb 07 12:49:41 PM PST 24
Finished	Feb 07 12:49:45 PM PST 24
Peak memory	218056 kb
Host	smart-a830e6e1-8248-46a8-ab51-2816c9c8c9b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3964196557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3964196557
Directory	/workspace/175.edn_genbits/latest

Test location	/workspace/coverage/default/176.edn_genbits.1781216550
Short name	T642
Test name
Test status
Simulation time	110051143 ps
CPU time	1.3 seconds
Started	Feb 07 12:49:42 PM PST 24
Finished	Feb 07 12:49:46 PM PST 24
Peak memory	215408 kb
Host	smart-5e873306-bfee-4081-9a5e-ce00281ccca5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1781216550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1781216550
Directory	/workspace/176.edn_genbits/latest

Test location	/workspace/coverage/default/177.edn_genbits.4014337552
Short name	T450
Test name
Test status
Simulation time	35530768 ps
CPU time	1.35 seconds
Started	Feb 07 12:49:45 PM PST 24
Finished	Feb 07 12:49:49 PM PST 24
Peak memory	216684 kb
Host	smart-34aa6601-7887-4bec-be5f-2573e9d45bad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4014337552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.4014337552
Directory	/workspace/177.edn_genbits/latest

Test location	/workspace/coverage/default/178.edn_genbits.2045911501
Short name	T794
Test name
Test status
Simulation time	27816990 ps
CPU time	1.23 seconds
Started	Feb 07 12:49:37 PM PST 24
Finished	Feb 07 12:49:42 PM PST 24
Peak memory	215516 kb
Host	smart-2c849642-daae-4795-b613-810e13d97779
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2045911501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2045911501
Directory	/workspace/178.edn_genbits/latest

Test location	/workspace/coverage/default/179.edn_genbits.167827227
Short name	T120
Test name
Test status
Simulation time	100920998 ps
CPU time	1.64 seconds
Started	Feb 07 12:49:40 PM PST 24
Finished	Feb 07 12:49:45 PM PST 24
Peak memory	217092 kb
Host	smart-fab74477-fc00-4636-98f0-ebc9848b9f0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=167827227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.167827227
Directory	/workspace/179.edn_genbits/latest

Test location	/workspace/coverage/default/18.edn_alert.2182515119
Short name	T613
Test name
Test status
Simulation time	257180391 ps
CPU time	0.91 seconds
Started	Feb 07 12:48:20 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	205840 kb
Host	smart-e7a9fb81-d9f3-4525-b47c-3db9efbd622a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2182515119 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2182515119
Directory	/workspace/18.edn_alert/latest

Test location	/workspace/coverage/default/18.edn_alert_test.271651213
Short name	T515
Test name
Test status
Simulation time	46881029 ps
CPU time	0.85 seconds
Started	Feb 07 12:48:24 PM PST 24
Finished	Feb 07 12:48:34 PM PST 24
Peak memory	205416 kb
Host	smart-9d25c6e8-7af0-4993-812c-ff43f9d902d5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271651213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.271651213
Directory	/workspace/18.edn_alert_test/latest

Test location	/workspace/coverage/default/18.edn_disable.4208307052
Short name	T830
Test name
Test status
Simulation time	20675572 ps
CPU time	0.86 seconds
Started	Feb 07 12:48:22 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	215016 kb
Host	smart-bb083f35-489e-445c-8e77-daf1e652dcc9
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208307052 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.4208307052
Directory	/workspace/18.edn_disable/latest

Test location	/workspace/coverage/default/18.edn_disable_auto_req_mode.2338622701
Short name	T365
Test name
Test status
Simulation time	200226249 ps
CPU time	0.99 seconds
Started	Feb 07 12:48:29 PM PST 24
Finished	Feb 07 12:48:37 PM PST 24
Peak memory	215104 kb
Host	smart-ce7e2331-7000-4eb4-be03-8acd15381cfd
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338622701 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d isable_auto_req_mode.2338622701
Directory	/workspace/18.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/18.edn_err.3713914153
Short name	T736
Test name
Test status
Simulation time	89594035 ps
CPU time	1.23 seconds
Started	Feb 07 12:48:31 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	222484 kb
Host	smart-955ad325-7211-420f-8b1b-6430fed9e366
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3713914153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3713914153
Directory	/workspace/18.edn_err/latest

Test location	/workspace/coverage/default/18.edn_genbits.1650957094
Short name	T900
Test name
Test status
Simulation time	58579289 ps
CPU time	1.26 seconds
Started	Feb 07 12:48:26 PM PST 24
Finished	Feb 07 12:48:37 PM PST 24
Peak memory	217492 kb
Host	smart-40d5590b-cf98-45a8-af49-f24d3ff8b35c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1650957094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1650957094
Directory	/workspace/18.edn_genbits/latest

Test location	/workspace/coverage/default/18.edn_intr.2557922946
Short name	T653
Test name
Test status
Simulation time	40893971 ps
CPU time	0.9 seconds
Started	Feb 07 12:48:20 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	214968 kb
Host	smart-b5fb7525-aba0-4dcb-9d6c-5526b76dc8f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2557922946 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2557922946
Directory	/workspace/18.edn_intr/latest

Test location	/workspace/coverage/default/18.edn_smoke.2968195272
Short name	T476
Test name
Test status
Simulation time	51135876 ps
CPU time	0.9 seconds
Started	Feb 07 12:48:19 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	214964 kb
Host	smart-435fd52e-4c40-46c2-8707-58d184569cb5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2968195272 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2968195272
Directory	/workspace/18.edn_smoke/latest

Test location	/workspace/coverage/default/18.edn_stress_all.710908473
Short name	T521
Test name
Test status
Simulation time	59923344 ps
CPU time	1.68 seconds
Started	Feb 07 12:48:29 PM PST 24
Finished	Feb 07 12:48:38 PM PST 24
Peak memory	206700 kb
Host	smart-970a2c78-8ba3-4e6b-969a-c771ad6b07bd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710908473 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.710908473
Directory	/workspace/18.edn_stress_all/latest

Test location	/workspace/coverage/default/18.edn_stress_all_with_rand_reset.245588363
Short name	T550
Test name
Test status
Simulation time	21459551026 ps
CPU time	483.74 seconds
Started	Feb 07 12:48:20 PM PST 24
Finished	Feb 07 12:56:29 PM PST 24
Peak memory	217588 kb
Host	smart-5f8ab3ba-79a0-4a34-ac01-5d515c6796e7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245588363 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.245588363
Directory	/workspace/18.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/180.edn_genbits.144569117
Short name	T474
Test name
Test status
Simulation time	46121401 ps
CPU time	1.77 seconds
Started	Feb 07 12:49:37 PM PST 24
Finished	Feb 07 12:49:42 PM PST 24
Peak memory	216944 kb
Host	smart-4fcbcb25-fe98-4524-a8b3-51988080a510
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=144569117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.144569117
Directory	/workspace/180.edn_genbits/latest

Test location	/workspace/coverage/default/181.edn_genbits.1291955018
Short name	T414
Test name
Test status
Simulation time	41273741 ps
CPU time	1.46 seconds
Started	Feb 07 12:49:45 PM PST 24
Finished	Feb 07 12:49:49 PM PST 24
Peak memory	216860 kb
Host	smart-3a2c4adc-3363-4e5d-a558-68afc24a17b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291955018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1291955018
Directory	/workspace/181.edn_genbits/latest

Test location	/workspace/coverage/default/182.edn_genbits.376443163
Short name	T439
Test name
Test status
Simulation time	50312370 ps
CPU time	1.25 seconds
Started	Feb 07 12:49:45 PM PST 24
Finished	Feb 07 12:49:49 PM PST 24
Peak memory	215460 kb
Host	smart-b2d6e731-8ee1-45d7-913c-38055b0a09f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=376443163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.376443163
Directory	/workspace/182.edn_genbits/latest

Test location	/workspace/coverage/default/183.edn_genbits.2073898018
Short name	T582
Test name
Test status
Simulation time	61275763 ps
CPU time	1.65 seconds
Started	Feb 07 12:49:55 PM PST 24
Finished	Feb 07 12:49:58 PM PST 24
Peak memory	216540 kb
Host	smart-c1c60c2b-1c86-4d18-8b7d-0e0361bebd06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2073898018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2073898018
Directory	/workspace/183.edn_genbits/latest

Test location	/workspace/coverage/default/184.edn_genbits.1350324471
Short name	T486
Test name
Test status
Simulation time	72227351 ps
CPU time	1.11 seconds
Started	Feb 07 12:49:37 PM PST 24
Finished	Feb 07 12:49:42 PM PST 24
Peak memory	215268 kb
Host	smart-a3db9a99-77c4-42f1-b1f7-3bd511d9bb2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1350324471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1350324471
Directory	/workspace/184.edn_genbits/latest

Test location	/workspace/coverage/default/185.edn_genbits.2909687027
Short name	T713
Test name
Test status
Simulation time	169549800 ps
CPU time	2.38 seconds
Started	Feb 07 12:49:44 PM PST 24
Finished	Feb 07 12:49:49 PM PST 24
Peak memory	216648 kb
Host	smart-73dcfaf7-46da-49b6-8367-13d653a6e7de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2909687027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2909687027
Directory	/workspace/185.edn_genbits/latest

Test location	/workspace/coverage/default/186.edn_genbits.1818149329
Short name	T30
Test name
Test status
Simulation time	49859447 ps
CPU time	1.61 seconds
Started	Feb 07 12:49:56 PM PST 24
Finished	Feb 07 12:49:58 PM PST 24
Peak memory	216660 kb
Host	smart-d3f9224c-5444-4550-8134-8783cf8438c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1818149329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1818149329
Directory	/workspace/186.edn_genbits/latest

Test location	/workspace/coverage/default/187.edn_genbits.701244764
Short name	T878
Test name
Test status
Simulation time	85722659 ps
CPU time	1.1 seconds
Started	Feb 07 12:49:51 PM PST 24
Finished	Feb 07 12:49:53 PM PST 24
Peak memory	215360 kb
Host	smart-c9ac081e-b693-48d7-bf8e-7e72b75823f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=701244764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.701244764
Directory	/workspace/187.edn_genbits/latest

Test location	/workspace/coverage/default/188.edn_genbits.1266675736
Short name	T904
Test name
Test status
Simulation time	218191895 ps
CPU time	0.97 seconds
Started	Feb 07 12:49:36 PM PST 24
Finished	Feb 07 12:49:40 PM PST 24
Peak memory	215484 kb
Host	smart-9d96cf79-c284-48b0-b9ea-78f455b0c71a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1266675736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1266675736
Directory	/workspace/188.edn_genbits/latest

Test location	/workspace/coverage/default/189.edn_genbits.2275393789
Short name	T946
Test name
Test status
Simulation time	80776925 ps
CPU time	2.73 seconds
Started	Feb 07 12:49:47 PM PST 24
Finished	Feb 07 12:49:51 PM PST 24
Peak memory	216656 kb
Host	smart-ea205b63-aa64-4594-bcf0-c187ef8e56a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2275393789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2275393789
Directory	/workspace/189.edn_genbits/latest

Test location	/workspace/coverage/default/19.edn_alert.2676578563
Short name	T735
Test name
Test status
Simulation time	19780268 ps
CPU time	0.99 seconds
Started	Feb 07 12:48:33 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	206052 kb
Host	smart-f79bbd34-0d88-46bc-9d25-ee337637e5c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2676578563 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2676578563
Directory	/workspace/19.edn_alert/latest

Test location	/workspace/coverage/default/19.edn_alert_test.3921040233
Short name	T516
Test name
Test status
Simulation time	92547645 ps
CPU time	0.88 seconds
Started	Feb 07 12:48:36 PM PST 24
Finished	Feb 07 12:48:43 PM PST 24
Peak memory	206348 kb
Host	smart-f680f0e4-bc50-403b-aeb8-e1db5c8e0fa2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921040233 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3921040233
Directory	/workspace/19.edn_alert_test/latest

Test location	/workspace/coverage/default/19.edn_disable.1481563768
Short name	T448
Test name
Test status
Simulation time	38184049 ps
CPU time	0.87 seconds
Started	Feb 07 12:48:31 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	215020 kb
Host	smart-f0869bd6-62fa-481f-a1b5-f6e028bc189d
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481563768 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1481563768
Directory	/workspace/19.edn_disable/latest

Test location	/workspace/coverage/default/19.edn_disable_auto_req_mode.1009472692
Short name	T723
Test name
Test status
Simulation time	139362952 ps
CPU time	1.02 seconds
Started	Feb 07 12:48:26 PM PST 24
Finished	Feb 07 12:48:36 PM PST 24
Peak memory	215276 kb
Host	smart-4406bae8-8078-4dee-9273-8e198357cdc8
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009472692 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d isable_auto_req_mode.1009472692
Directory	/workspace/19.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/19.edn_err.3441771248
Short name	T896
Test name
Test status
Simulation time	21453878 ps
CPU time	0.88 seconds
Started	Feb 07 12:48:30 PM PST 24
Finished	Feb 07 12:48:38 PM PST 24
Peak memory	216820 kb
Host	smart-1abcf166-ce94-4637-a635-54b7fc5e7cb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3441771248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3441771248
Directory	/workspace/19.edn_err/latest

Test location	/workspace/coverage/default/19.edn_genbits.3799944125
Short name	T928
Test name
Test status
Simulation time	69891245 ps
CPU time	1.3 seconds
Started	Feb 07 12:48:37 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	216444 kb
Host	smart-3a3ba4f3-09bb-4bf5-a83e-e2aae4cb37e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3799944125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3799944125
Directory	/workspace/19.edn_genbits/latest

Test location	/workspace/coverage/default/19.edn_intr.768550936
Short name	T73
Test name
Test status
Simulation time	21432146 ps
CPU time	1.04 seconds
Started	Feb 07 12:48:30 PM PST 24
Finished	Feb 07 12:48:38 PM PST 24
Peak memory	215304 kb
Host	smart-67d96101-4763-45bf-8b85-13da154627c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=768550936 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.768550936
Directory	/workspace/19.edn_intr/latest

Test location	/workspace/coverage/default/19.edn_smoke.3555715613
Short name	T866
Test name
Test status
Simulation time	47884270 ps
CPU time	0.92 seconds
Started	Feb 07 12:48:24 PM PST 24
Finished	Feb 07 12:48:35 PM PST 24
Peak memory	215024 kb
Host	smart-c25659cd-6d78-4d1d-a7d3-99ab35209d25
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3555715613 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3555715613
Directory	/workspace/19.edn_smoke/latest

Test location	/workspace/coverage/default/19.edn_stress_all.903473090
Short name	T757
Test name
Test status
Simulation time	345168457 ps
CPU time	6.52 seconds
Started	Feb 07 12:48:28 PM PST 24
Finished	Feb 07 12:48:43 PM PST 24
Peak memory	215616 kb
Host	smart-b674dc3a-4342-4dc9-b80b-64af2b5e9f55
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903473090 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.903473090
Directory	/workspace/19.edn_stress_all/latest

Test location	/workspace/coverage/default/19.edn_stress_all_with_rand_reset.999182393
Short name	T552
Test name
Test status
Simulation time	22901628779 ps
CPU time	580.13 seconds
Started	Feb 07 12:48:39 PM PST 24
Finished	Feb 07 12:58:24 PM PST 24
Peak memory	218948 kb
Host	smart-30ed42f8-4adc-485b-8009-a5117f27f4ac
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999182393 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.999182393
Directory	/workspace/19.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/192.edn_genbits.1546280734
Short name	T505
Test name
Test status
Simulation time	61171774 ps
CPU time	1.14 seconds
Started	Feb 07 12:49:41 PM PST 24
Finished	Feb 07 12:49:45 PM PST 24
Peak memory	217020 kb
Host	smart-fbe94206-54ad-4b99-8785-35c1f4028bfb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1546280734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1546280734
Directory	/workspace/192.edn_genbits/latest

Test location	/workspace/coverage/default/193.edn_genbits.2763414859
Short name	T36
Test name
Test status
Simulation time	85561934 ps
CPU time	1.3 seconds
Started	Feb 07 12:49:48 PM PST 24
Finished	Feb 07 12:49:50 PM PST 24
Peak memory	215376 kb
Host	smart-850475db-41a4-4b3a-927d-73ec109db592
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2763414859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2763414859
Directory	/workspace/193.edn_genbits/latest

Test location	/workspace/coverage/default/194.edn_genbits.407941519
Short name	T708
Test name
Test status
Simulation time	57698270 ps
CPU time	1.29 seconds
Started	Feb 07 12:50:00 PM PST 24
Finished	Feb 07 12:50:04 PM PST 24
Peak memory	218124 kb
Host	smart-85b5067d-0966-46f3-9981-abd311cab3bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=407941519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.407941519
Directory	/workspace/194.edn_genbits/latest

Test location	/workspace/coverage/default/195.edn_genbits.2223044635
Short name	T902
Test name
Test status
Simulation time	64956831 ps
CPU time	1.54 seconds
Started	Feb 07 12:50:13 PM PST 24
Finished	Feb 07 12:50:16 PM PST 24
Peak memory	216876 kb
Host	smart-ab5fb5c7-79e0-458b-89a8-e0d0bada6e7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2223044635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2223044635
Directory	/workspace/195.edn_genbits/latest

Test location	/workspace/coverage/default/196.edn_genbits.1934077932
Short name	T356
Test name
Test status
Simulation time	48782402 ps
CPU time	1.27 seconds
Started	Feb 07 12:49:47 PM PST 24
Finished	Feb 07 12:49:50 PM PST 24
Peak memory	215476 kb
Host	smart-af531a8c-6e3d-4a71-bcc5-0d2c4f5098b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1934077932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1934077932
Directory	/workspace/196.edn_genbits/latest

Test location	/workspace/coverage/default/197.edn_genbits.3292356258
Short name	T568
Test name
Test status
Simulation time	41419887 ps
CPU time	1.11 seconds
Started	Feb 07 12:50:06 PM PST 24
Finished	Feb 07 12:50:09 PM PST 24
Peak memory	215364 kb
Host	smart-b2e680b9-a8e1-4609-82ac-2105428ad21a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3292356258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3292356258
Directory	/workspace/197.edn_genbits/latest

Test location	/workspace/coverage/default/198.edn_genbits.700938089
Short name	T545
Test name
Test status
Simulation time	39169466 ps
CPU time	1.1 seconds
Started	Feb 07 12:49:55 PM PST 24
Finished	Feb 07 12:49:57 PM PST 24
Peak memory	215448 kb
Host	smart-7b450447-d338-48a7-8113-7807e43bead2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=700938089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.700938089
Directory	/workspace/198.edn_genbits/latest

Test location	/workspace/coverage/default/199.edn_genbits.2240031004
Short name	T705
Test name
Test status
Simulation time	131826026 ps
CPU time	1.1 seconds
Started	Feb 07 12:50:00 PM PST 24
Finished	Feb 07 12:50:03 PM PST 24
Peak memory	215388 kb
Host	smart-09fd7a65-6ab1-438f-998b-dd9861ec9b5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2240031004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2240031004
Directory	/workspace/199.edn_genbits/latest

Test location	/workspace/coverage/default/2.edn_alert.2985492836
Short name	T749
Test name
Test status
Simulation time	70906529 ps
CPU time	0.97 seconds
Started	Feb 07 12:47:46 PM PST 24
Finished	Feb 07 12:47:48 PM PST 24
Peak memory	206160 kb
Host	smart-3408c943-04f6-4e6a-8f23-5bbbd08e2c92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2985492836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2985492836
Directory	/workspace/2.edn_alert/latest

Test location	/workspace/coverage/default/2.edn_alert_test.3385013742
Short name	T349
Test name
Test status
Simulation time	11353494 ps
CPU time	0.83 seconds
Started	Feb 07 12:47:48 PM PST 24
Finished	Feb 07 12:47:50 PM PST 24
Peak memory	205184 kb
Host	smart-4eb43fca-3fd4-4f65-877d-541894c1c159
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385013742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3385013742
Directory	/workspace/2.edn_alert_test/latest

Test location	/workspace/coverage/default/2.edn_disable.952382210
Short name	T353
Test name
Test status
Simulation time	59637134 ps
CPU time	0.78 seconds
Started	Feb 07 12:47:45 PM PST 24
Finished	Feb 07 12:47:46 PM PST 24
Peak memory	214844 kb
Host	smart-3e96be1c-e255-4575-8e9d-c642c33ac30f
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952382210 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.952382210
Directory	/workspace/2.edn_disable/latest

Test location	/workspace/coverage/default/2.edn_disable_auto_req_mode.735606377
Short name	T575
Test name
Test status
Simulation time	44579173 ps
CPU time	1.34 seconds
Started	Feb 07 12:47:45 PM PST 24
Finished	Feb 07 12:47:47 PM PST 24
Peak memory	215320 kb
Host	smart-02cd5078-c9ee-4971-9b04-7420bd15f93a
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735606377 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis able_auto_req_mode.735606377
Directory	/workspace/2.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/2.edn_err.4253523021
Short name	T413
Test name
Test status
Simulation time	19762854 ps
CPU time	1.04 seconds
Started	Feb 07 12:47:48 PM PST 24
Finished	Feb 07 12:47:50 PM PST 24
Peak memory	216680 kb
Host	smart-c5f31644-0435-4d6c-9322-3c228e347379
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4253523021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.4253523021
Directory	/workspace/2.edn_err/latest

Test location	/workspace/coverage/default/2.edn_genbits.320753285
Short name	T194
Test name
Test status
Simulation time	104424383 ps
CPU time	3.11 seconds
Started	Feb 07 12:47:47 PM PST 24
Finished	Feb 07 12:47:51 PM PST 24
Peak memory	215636 kb
Host	smart-eaf24717-1db9-497e-99da-70f5f9dcd38a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=320753285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.320753285
Directory	/workspace/2.edn_genbits/latest

Test location	/workspace/coverage/default/2.edn_intr.3562986202
Short name	T366
Test name
Test status
Simulation time	30930126 ps
CPU time	0.9 seconds
Started	Feb 07 12:47:48 PM PST 24
Finished	Feb 07 12:47:49 PM PST 24
Peak memory	215060 kb
Host	smart-8af5585a-ebf1-4e69-bd9c-cfdf906a23fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3562986202 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3562986202
Directory	/workspace/2.edn_intr/latest

Test location	/workspace/coverage/default/2.edn_smoke.3917266879
Short name	T360
Test name
Test status
Simulation time	29239275 ps
CPU time	0.95 seconds
Started	Feb 07 12:47:50 PM PST 24
Finished	Feb 07 12:47:52 PM PST 24
Peak memory	215040 kb
Host	smart-16b5f429-253f-44e8-89f3-7d04009032a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3917266879 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3917266879
Directory	/workspace/2.edn_smoke/latest

Test location	/workspace/coverage/default/2.edn_stress_all.3804486128
Short name	T777
Test name
Test status
Simulation time	777167099 ps
CPU time	4.29 seconds
Started	Feb 07 12:47:47 PM PST 24
Finished	Feb 07 12:47:52 PM PST 24
Peak memory	215100 kb
Host	smart-cdff8b19-f3c8-4fbb-99d2-7bafcea8b48a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804486128 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3804486128
Directory	/workspace/2.edn_stress_all/latest

Test location	/workspace/coverage/default/2.edn_stress_all_with_rand_reset.1500966359
Short name	T704
Test name
Test status
Simulation time	78363549734 ps
CPU time	1091.97 seconds
Started	Feb 07 12:47:49 PM PST 24
Finished	Feb 07 01:06:02 PM PST 24
Peak memory	219164 kb
Host	smart-a8aa5412-7bd1-4afc-820d-76cedde4d338
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500966359 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1500966359
Directory	/workspace/2.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.edn_alert.2488628271
Short name	T96
Test name
Test status
Simulation time	119535869 ps
CPU time	0.98 seconds
Started	Feb 07 12:48:29 PM PST 24
Finished	Feb 07 12:48:38 PM PST 24
Peak memory	205924 kb
Host	smart-3d803993-f74f-4eb6-a8f5-59482261821a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2488628271 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2488628271
Directory	/workspace/20.edn_alert/latest

Test location	/workspace/coverage/default/20.edn_alert_test.2320089796
Short name	T461
Test name
Test status
Simulation time	31726345 ps
CPU time	0.92 seconds
Started	Feb 07 12:48:37 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	205912 kb
Host	smart-96cff932-54d3-447c-ae0a-afafc99b4351
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320089796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2320089796
Directory	/workspace/20.edn_alert_test/latest

Test location	/workspace/coverage/default/20.edn_disable.1643514228
Short name	T722
Test name
Test status
Simulation time	134149881 ps
CPU time	0.8 seconds
Started	Feb 07 12:48:38 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	215092 kb
Host	smart-6d7053f7-c27a-4c57-af4a-577d7ac88ccc
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643514228 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1643514228
Directory	/workspace/20.edn_disable/latest

Test location	/workspace/coverage/default/20.edn_disable_auto_req_mode.2527435833
Short name	T822
Test name
Test status
Simulation time	88503651 ps
CPU time	1.34 seconds
Started	Feb 07 12:48:29 PM PST 24
Finished	Feb 07 12:48:38 PM PST 24
Peak memory	215292 kb
Host	smart-86c0c859-d2d7-493d-b8aa-1d89a0883041
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527435833 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d isable_auto_req_mode.2527435833
Directory	/workspace/20.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/20.edn_err.547868988
Short name	T543
Test name
Test status
Simulation time	64529923 ps
CPU time	1.17 seconds
Started	Feb 07 12:48:37 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	229368 kb
Host	smart-237e4673-a1cf-4645-8eda-4f0e968b2df0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=547868988 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.547868988
Directory	/workspace/20.edn_err/latest

Test location	/workspace/coverage/default/20.edn_genbits.873845943
Short name	T915
Test name
Test status
Simulation time	30785507 ps
CPU time	1.11 seconds
Started	Feb 07 12:48:35 PM PST 24
Finished	Feb 07 12:48:40 PM PST 24
Peak memory	216612 kb
Host	smart-5b7fe5a0-861d-4989-bde0-7fc21f9996fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=873845943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.873845943
Directory	/workspace/20.edn_genbits/latest

Test location	/workspace/coverage/default/20.edn_smoke.3453388198
Short name	T888
Test name
Test status
Simulation time	45505959 ps
CPU time	0.91 seconds
Started	Feb 07 12:48:23 PM PST 24
Finished	Feb 07 12:48:28 PM PST 24
Peak memory	215024 kb
Host	smart-aef4c5bb-5232-4d89-a153-ef1280fa1262
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3453388198 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3453388198
Directory	/workspace/20.edn_smoke/latest

Test location	/workspace/coverage/default/20.edn_stress_all.310499773
Short name	T695
Test name
Test status
Simulation time	103892587 ps
CPU time	1.63 seconds
Started	Feb 07 12:48:34 PM PST 24
Finished	Feb 07 12:48:40 PM PST 24
Peak memory	215492 kb
Host	smart-762fad32-3c94-4c9c-9e45-f737c6d28340
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310499773 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.310499773
Directory	/workspace/20.edn_stress_all/latest

Test location	/workspace/coverage/default/20.edn_stress_all_with_rand_reset.1350271431
Short name	T786
Test name
Test status
Simulation time	19794105201 ps
CPU time	446.77 seconds
Started	Feb 07 12:48:41 PM PST 24
Finished	Feb 07 12:56:11 PM PST 24
Peak memory	216948 kb
Host	smart-07667751-10b3-4437-82a4-f5e2477a6a8e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350271431 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1350271431
Directory	/workspace/20.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/200.edn_genbits.1502260674
Short name	T186
Test name
Test status
Simulation time	42459091 ps
CPU time	1.24 seconds
Started	Feb 07 12:50:06 PM PST 24
Finished	Feb 07 12:50:09 PM PST 24
Peak memory	216632 kb
Host	smart-63510c38-4925-4599-8fe1-f5cb63decfba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1502260674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1502260674
Directory	/workspace/200.edn_genbits/latest

Test location	/workspace/coverage/default/201.edn_genbits.569457769
Short name	T793
Test name
Test status
Simulation time	71630634 ps
CPU time	1.36 seconds
Started	Feb 07 12:50:06 PM PST 24
Finished	Feb 07 12:50:09 PM PST 24
Peak memory	216604 kb
Host	smart-42f26d07-914a-46d5-a2e6-716bb4f43fe0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=569457769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.569457769
Directory	/workspace/201.edn_genbits/latest

Test location	/workspace/coverage/default/202.edn_genbits.750856864
Short name	T772
Test name
Test status
Simulation time	288330148 ps
CPU time	1.03 seconds
Started	Feb 07 12:50:05 PM PST 24
Finished	Feb 07 12:50:07 PM PST 24
Peak memory	215296 kb
Host	smart-46d80041-40ff-458b-8f61-49e9cda25f42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=750856864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.750856864
Directory	/workspace/202.edn_genbits/latest

Test location	/workspace/coverage/default/203.edn_genbits.3504680992
Short name	T188
Test name
Test status
Simulation time	48041137 ps
CPU time	1.73 seconds
Started	Feb 07 12:49:45 PM PST 24
Finished	Feb 07 12:49:49 PM PST 24
Peak memory	216676 kb
Host	smart-5b7af1ac-71f5-44b9-a098-236a0c92cba5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3504680992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3504680992
Directory	/workspace/203.edn_genbits/latest

Test location	/workspace/coverage/default/204.edn_genbits.3579537194
Short name	T665
Test name
Test status
Simulation time	88948918 ps
CPU time	1.44 seconds
Started	Feb 07 12:49:52 PM PST 24
Finished	Feb 07 12:49:54 PM PST 24
Peak memory	216720 kb
Host	smart-dc670511-f127-45b9-a529-d09b6e0a5379
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3579537194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3579537194
Directory	/workspace/204.edn_genbits/latest

Test location	/workspace/coverage/default/205.edn_genbits.557177178
Short name	T631
Test name
Test status
Simulation time	108962520 ps
CPU time	1.69 seconds
Started	Feb 07 12:49:57 PM PST 24
Finished	Feb 07 12:50:00 PM PST 24
Peak memory	216552 kb
Host	smart-7d50ffe0-2f37-4b31-8a0a-0567833fde20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=557177178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.557177178
Directory	/workspace/205.edn_genbits/latest

Test location	/workspace/coverage/default/206.edn_genbits.3710253274
Short name	T591
Test name
Test status
Simulation time	85787261 ps
CPU time	1.33 seconds
Started	Feb 07 12:49:53 PM PST 24
Finished	Feb 07 12:49:55 PM PST 24
Peak memory	216948 kb
Host	smart-c2a195af-e76e-4135-af1f-c70c3ab420aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3710253274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3710253274
Directory	/workspace/206.edn_genbits/latest

Test location	/workspace/coverage/default/207.edn_genbits.742317608
Short name	T463
Test name
Test status
Simulation time	39003512 ps
CPU time	1.4 seconds
Started	Feb 07 12:50:06 PM PST 24
Finished	Feb 07 12:50:09 PM PST 24
Peak memory	215360 kb
Host	smart-d4581bbc-e886-4a61-8db5-5749d6c77e2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=742317608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.742317608
Directory	/workspace/207.edn_genbits/latest

Test location	/workspace/coverage/default/208.edn_genbits.4149251967
Short name	T113
Test name
Test status
Simulation time	81248676 ps
CPU time	1.26 seconds
Started	Feb 07 12:49:51 PM PST 24
Finished	Feb 07 12:49:53 PM PST 24
Peak memory	215344 kb
Host	smart-9a3f28dc-571e-4c11-870e-d2890cf84f37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4149251967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.4149251967
Directory	/workspace/208.edn_genbits/latest

Test location	/workspace/coverage/default/209.edn_genbits.2282905388
Short name	T354
Test name
Test status
Simulation time	62592738 ps
CPU time	1.14 seconds
Started	Feb 07 12:49:54 PM PST 24
Finished	Feb 07 12:49:56 PM PST 24
Peak memory	217240 kb
Host	smart-7efcf0d0-e6dc-4be2-ab88-40ea44995277
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2282905388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2282905388
Directory	/workspace/209.edn_genbits/latest

Test location	/workspace/coverage/default/21.edn_alert.213865603
Short name	T97
Test name
Test status
Simulation time	23087124 ps
CPU time	1.11 seconds
Started	Feb 07 12:48:32 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	205768 kb
Host	smart-1b0f947b-856f-4850-a8ac-403bd3a10676
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=213865603 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.213865603
Directory	/workspace/21.edn_alert/latest

Test location	/workspace/coverage/default/21.edn_alert_test.2591268073
Short name	T47
Test name
Test status
Simulation time	25161828 ps
CPU time	0.82 seconds
Started	Feb 07 12:48:35 PM PST 24
Finished	Feb 07 12:48:42 PM PST 24
Peak memory	205204 kb
Host	smart-60cc204a-e6d9-43c9-97f0-fac7fe324a2e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591268073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2591268073
Directory	/workspace/21.edn_alert_test/latest

Test location	/workspace/coverage/default/21.edn_disable.2670263056
Short name	T574
Test name
Test status
Simulation time	22577017 ps
CPU time	0.87 seconds
Started	Feb 07 12:48:35 PM PST 24
Finished	Feb 07 12:48:43 PM PST 24
Peak memory	215148 kb
Host	smart-28f3aae6-3149-4eb2-a261-57d82a401c6b
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670263056 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2670263056
Directory	/workspace/21.edn_disable/latest

Test location	/workspace/coverage/default/21.edn_disable_auto_req_mode.3381071543
Short name	T7
Test name
Test status
Simulation time	54980019 ps
CPU time	1.11 seconds
Started	Feb 07 12:48:42 PM PST 24
Finished	Feb 07 12:48:47 PM PST 24
Peak memory	215252 kb
Host	smart-382b8103-40e0-48e0-9a10-f25e583001a3
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381071543 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d isable_auto_req_mode.3381071543
Directory	/workspace/21.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/21.edn_err.4184886145
Short name	T537
Test name
Test status
Simulation time	58322245 ps
CPU time	1.13 seconds
Started	Feb 07 12:48:25 PM PST 24
Finished	Feb 07 12:48:36 PM PST 24
Peak memory	217072 kb
Host	smart-f5ced43f-3935-49c0-9524-f46d0322157e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4184886145 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.4184886145
Directory	/workspace/21.edn_err/latest

Test location	/workspace/coverage/default/21.edn_genbits.4096923180
Short name	T636
Test name
Test status
Simulation time	34497621 ps
CPU time	1.38 seconds
Started	Feb 07 12:48:29 PM PST 24
Finished	Feb 07 12:48:38 PM PST 24
Peak memory	215532 kb
Host	smart-97721480-311d-468d-b9a8-011c9d734f50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4096923180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.4096923180
Directory	/workspace/21.edn_genbits/latest

Test location	/workspace/coverage/default/21.edn_intr.159927032
Short name	T920
Test name
Test status
Simulation time	33183509 ps
CPU time	1.01 seconds
Started	Feb 07 12:48:33 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	214928 kb
Host	smart-7b8e8cee-5dcc-49ac-b79d-fdd167011062
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=159927032 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.159927032
Directory	/workspace/21.edn_intr/latest

Test location	/workspace/coverage/default/21.edn_smoke.2510490082
Short name	T344
Test name
Test status
Simulation time	19010517 ps
CPU time	0.98 seconds
Started	Feb 07 12:48:38 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	214664 kb
Host	smart-11b13b07-cda4-4cbc-96a0-4d9fc392cb75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2510490082 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2510490082
Directory	/workspace/21.edn_smoke/latest

Test location	/workspace/coverage/default/21.edn_stress_all.608284012
Short name	T454
Test name
Test status
Simulation time	242923695 ps
CPU time	4.3 seconds
Started	Feb 07 12:48:32 PM PST 24
Finished	Feb 07 12:48:43 PM PST 24
Peak memory	217688 kb
Host	smart-1b704243-02d6-4c80-b81b-08f9cfae2117
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608284012 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.608284012
Directory	/workspace/21.edn_stress_all/latest

Test location	/workspace/coverage/default/21.edn_stress_all_with_rand_reset.1494732421
Short name	T83
Test name
Test status
Simulation time	66859339036 ps
CPU time	830 seconds
Started	Feb 07 12:48:43 PM PST 24
Finished	Feb 07 01:02:36 PM PST 24
Peak memory	219552 kb
Host	smart-57e6bc72-ec0b-441a-9d15-926b5d92e8e9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494732421 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1494732421
Directory	/workspace/21.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/210.edn_genbits.3636866500
Short name	T572
Test name
Test status
Simulation time	38583537 ps
CPU time	1.35 seconds
Started	Feb 07 12:49:55 PM PST 24
Finished	Feb 07 12:49:57 PM PST 24
Peak memory	214972 kb
Host	smart-9046d0ea-c535-4d88-a119-3e44a0039942
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3636866500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3636866500
Directory	/workspace/210.edn_genbits/latest

Test location	/workspace/coverage/default/211.edn_genbits.2416800690
Short name	T821
Test name
Test status
Simulation time	96445333 ps
CPU time	1.15 seconds
Started	Feb 07 12:49:51 PM PST 24
Finished	Feb 07 12:49:53 PM PST 24
Peak memory	215288 kb
Host	smart-9b9037ce-042e-44e3-9224-ae9aaa49fd84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2416800690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2416800690
Directory	/workspace/211.edn_genbits/latest

Test location	/workspace/coverage/default/212.edn_genbits.1918681531
Short name	T848
Test name
Test status
Simulation time	48422304 ps
CPU time	1.8 seconds
Started	Feb 07 12:49:57 PM PST 24
Finished	Feb 07 12:50:00 PM PST 24
Peak memory	216504 kb
Host	smart-0af8dc20-6d58-480c-bcde-25452f874dea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1918681531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1918681531
Directory	/workspace/212.edn_genbits/latest

Test location	/workspace/coverage/default/213.edn_genbits.1470812155
Short name	T39
Test name
Test status
Simulation time	93667535 ps
CPU time	1.2 seconds
Started	Feb 07 12:49:57 PM PST 24
Finished	Feb 07 12:49:59 PM PST 24
Peak memory	216492 kb
Host	smart-4f74b16f-c4eb-47fa-9c78-229962efa165
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1470812155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1470812155
Directory	/workspace/213.edn_genbits/latest

Test location	/workspace/coverage/default/214.edn_genbits.3560950870
Short name	T767
Test name
Test status
Simulation time	86647402 ps
CPU time	1.4 seconds
Started	Feb 07 12:50:00 PM PST 24
Finished	Feb 07 12:50:03 PM PST 24
Peak memory	215568 kb
Host	smart-8357a145-5805-4d88-add1-8748903e3df6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3560950870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3560950870
Directory	/workspace/214.edn_genbits/latest

Test location	/workspace/coverage/default/215.edn_genbits.126370049
Short name	T546
Test name
Test status
Simulation time	52038803 ps
CPU time	2.06 seconds
Started	Feb 07 12:50:06 PM PST 24
Finished	Feb 07 12:50:09 PM PST 24
Peak memory	217344 kb
Host	smart-f8bd803d-021f-4735-9dcf-77a9c415a31d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=126370049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.126370049
Directory	/workspace/215.edn_genbits/latest

Test location	/workspace/coverage/default/216.edn_genbits.3054489378
Short name	T696
Test name
Test status
Simulation time	123472680 ps
CPU time	2.09 seconds
Started	Feb 07 12:50:00 PM PST 24
Finished	Feb 07 12:50:04 PM PST 24
Peak memory	217864 kb
Host	smart-61ecb9b0-f67a-4cfb-bcdf-1933609cfbeb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3054489378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.3054489378
Directory	/workspace/216.edn_genbits/latest

Test location	/workspace/coverage/default/217.edn_genbits.2918457893
Short name	T189
Test name
Test status
Simulation time	113273867 ps
CPU time	2.91 seconds
Started	Feb 07 12:49:55 PM PST 24
Finished	Feb 07 12:49:59 PM PST 24
Peak memory	216744 kb
Host	smart-5f28421d-1694-4ad6-b5bc-bcafa28870c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2918457893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2918457893
Directory	/workspace/217.edn_genbits/latest

Test location	/workspace/coverage/default/218.edn_genbits.82015314
Short name	T431
Test name
Test status
Simulation time	29033628 ps
CPU time	1.21 seconds
Started	Feb 07 12:49:54 PM PST 24
Finished	Feb 07 12:49:56 PM PST 24
Peak memory	215440 kb
Host	smart-f5ec8c81-39ec-4dec-bb09-b8b3c5b01dcf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=82015314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.82015314
Directory	/workspace/218.edn_genbits/latest

Test location	/workspace/coverage/default/219.edn_genbits.1508051687
Short name	T641
Test name
Test status
Simulation time	72397308 ps
CPU time	1.63 seconds
Started	Feb 07 12:49:52 PM PST 24
Finished	Feb 07 12:49:55 PM PST 24
Peak memory	217008 kb
Host	smart-d308b648-0170-420b-9af6-fb547a068245
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1508051687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1508051687
Directory	/workspace/219.edn_genbits/latest

Test location	/workspace/coverage/default/22.edn_alert.2986512636
Short name	T488
Test name
Test status
Simulation time	60043087 ps
CPU time	0.97 seconds
Started	Feb 07 12:48:37 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	205964 kb
Host	smart-367a3bab-edd5-45f3-8828-aa817227a1e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2986512636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2986512636
Directory	/workspace/22.edn_alert/latest

Test location	/workspace/coverage/default/22.edn_alert_test.527452570
Short name	T820
Test name
Test status
Simulation time	16217006 ps
CPU time	0.9 seconds
Started	Feb 07 12:48:37 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	206312 kb
Host	smart-49ffd3b1-fb9f-45a2-9c85-e0e98e247c57
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527452570 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.527452570
Directory	/workspace/22.edn_alert_test/latest

Test location	/workspace/coverage/default/22.edn_disable_auto_req_mode.1944406366
Short name	T522
Test name
Test status
Simulation time	46236292 ps
CPU time	1.13 seconds
Started	Feb 07 12:48:32 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	215152 kb
Host	smart-2b22c7b4-d950-45f7-b8b6-a8654c481fcb
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944406366 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d isable_auto_req_mode.1944406366
Directory	/workspace/22.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/22.edn_err.468975464
Short name	T409
Test name
Test status
Simulation time	26988407 ps
CPU time	0.92 seconds
Started	Feb 07 12:48:42 PM PST 24
Finished	Feb 07 12:48:47 PM PST 24
Peak memory	221896 kb
Host	smart-c2f06368-1a71-4779-89d8-af8823f925be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=468975464 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.468975464
Directory	/workspace/22.edn_err/latest

Test location	/workspace/coverage/default/22.edn_genbits.657570958
Short name	T668
Test name
Test status
Simulation time	65657793 ps
CPU time	1.44 seconds
Started	Feb 07 12:48:34 PM PST 24
Finished	Feb 07 12:48:40 PM PST 24
Peak memory	217132 kb
Host	smart-229abb11-dda7-4519-a4ef-3671593f16de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=657570958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.657570958
Directory	/workspace/22.edn_genbits/latest

Test location	/workspace/coverage/default/22.edn_intr.4180054305
Short name	T53
Test name
Test status
Simulation time	24200026 ps
CPU time	1.08 seconds
Started	Feb 07 12:48:38 PM PST 24
Finished	Feb 07 12:48:45 PM PST 24
Peak memory	222536 kb
Host	smart-ec676b77-800f-40fa-a3ae-e0dc467e6332
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4180054305 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.4180054305
Directory	/workspace/22.edn_intr/latest

Test location	/workspace/coverage/default/22.edn_smoke.1426796246
Short name	T838
Test name
Test status
Simulation time	60531753 ps
CPU time	0.84 seconds
Started	Feb 07 12:48:35 PM PST 24
Finished	Feb 07 12:48:42 PM PST 24
Peak memory	214872 kb
Host	smart-53fbcf11-6b0a-42b2-9f85-3b13275a20c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1426796246 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1426796246
Directory	/workspace/22.edn_smoke/latest

Test location	/workspace/coverage/default/22.edn_stress_all.2433839974
Short name	T429
Test name
Test status
Simulation time	593793826 ps
CPU time	3.91 seconds
Started	Feb 07 12:48:37 PM PST 24
Finished	Feb 07 12:48:47 PM PST 24
Peak memory	214876 kb
Host	smart-f2c104b7-a78b-441d-ba1c-0e0adc0f0daf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433839974 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2433839974
Directory	/workspace/22.edn_stress_all/latest

Test location	/workspace/coverage/default/220.edn_genbits.723302747
Short name	T686
Test name
Test status
Simulation time	71312464 ps
CPU time	1.03 seconds
Started	Feb 07 12:50:06 PM PST 24
Finished	Feb 07 12:50:08 PM PST 24
Peak memory	214996 kb
Host	smart-8a192372-f407-4483-89c2-121b7e65ccdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=723302747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.723302747
Directory	/workspace/220.edn_genbits/latest

Test location	/workspace/coverage/default/222.edn_genbits.3782284136
Short name	T880
Test name
Test status
Simulation time	47702944 ps
CPU time	1.49 seconds
Started	Feb 07 12:49:45 PM PST 24
Finished	Feb 07 12:49:49 PM PST 24
Peak memory	216536 kb
Host	smart-5933fc60-c4ed-4293-b186-eea4bc9b9600
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3782284136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3782284136
Directory	/workspace/222.edn_genbits/latest

Test location	/workspace/coverage/default/223.edn_genbits.2910089169
Short name	T525
Test name
Test status
Simulation time	91035355 ps
CPU time	1.32 seconds
Started	Feb 07 12:49:57 PM PST 24
Finished	Feb 07 12:49:59 PM PST 24
Peak memory	215332 kb
Host	smart-9bfbbce1-6107-4161-9a28-2675c345c6df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2910089169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2910089169
Directory	/workspace/223.edn_genbits/latest

Test location	/workspace/coverage/default/225.edn_genbits.1403877341
Short name	T1
Test name
Test status
Simulation time	84134975 ps
CPU time	1.25 seconds
Started	Feb 07 12:49:58 PM PST 24
Finished	Feb 07 12:50:00 PM PST 24
Peak memory	215508 kb
Host	smart-5becbb7d-1ef8-42aa-8439-268d0c14138b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1403877341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1403877341
Directory	/workspace/225.edn_genbits/latest

Test location	/workspace/coverage/default/226.edn_genbits.2304516293
Short name	T876
Test name
Test status
Simulation time	57987734 ps
CPU time	1.67 seconds
Started	Feb 07 12:49:54 PM PST 24
Finished	Feb 07 12:49:56 PM PST 24
Peak memory	216764 kb
Host	smart-fc84ffad-131d-40ec-95b6-d849ddf31d44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2304516293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2304516293
Directory	/workspace/226.edn_genbits/latest

Test location	/workspace/coverage/default/227.edn_genbits.1997341664
Short name	T487
Test name
Test status
Simulation time	44893947 ps
CPU time	0.96 seconds
Started	Feb 07 12:49:51 PM PST 24
Finished	Feb 07 12:49:53 PM PST 24
Peak memory	216564 kb
Host	smart-7f9f945f-0b64-4bfd-9ace-0c08ea8c0763
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1997341664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1997341664
Directory	/workspace/227.edn_genbits/latest

Test location	/workspace/coverage/default/228.edn_genbits.339212068
Short name	T662
Test name
Test status
Simulation time	44515864 ps
CPU time	1.41 seconds
Started	Feb 07 12:50:00 PM PST 24
Finished	Feb 07 12:50:04 PM PST 24
Peak memory	215216 kb
Host	smart-9490d03a-b7ab-458d-a500-6e865af21bde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=339212068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.339212068
Directory	/workspace/228.edn_genbits/latest

Test location	/workspace/coverage/default/229.edn_genbits.3358827683
Short name	T460
Test name
Test status
Simulation time	123213243 ps
CPU time	1.01 seconds
Started	Feb 07 12:49:55 PM PST 24
Finished	Feb 07 12:49:56 PM PST 24
Peak memory	215200 kb
Host	smart-3ac6457c-901c-40d7-bbfb-b41084391b14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3358827683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3358827683
Directory	/workspace/229.edn_genbits/latest

Test location	/workspace/coverage/default/23.edn_alert.3205130872
Short name	T233
Test name
Test status
Simulation time	46904322 ps
CPU time	1 seconds
Started	Feb 07 12:48:29 PM PST 24
Finished	Feb 07 12:48:38 PM PST 24
Peak memory	205968 kb
Host	smart-caa5fa08-49d3-4e72-8f9c-3504751ee57e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3205130872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3205130872
Directory	/workspace/23.edn_alert/latest

Test location	/workspace/coverage/default/23.edn_alert_test.3300130131
Short name	T824
Test name
Test status
Simulation time	35110359 ps
CPU time	0.81 seconds
Started	Feb 07 12:48:39 PM PST 24
Finished	Feb 07 12:48:45 PM PST 24
Peak memory	205188 kb
Host	smart-196af586-695b-443d-9b51-f65a68958343
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300130131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3300130131
Directory	/workspace/23.edn_alert_test/latest

Test location	/workspace/coverage/default/23.edn_disable_auto_req_mode.1862830952
Short name	T403
Test name
Test status
Simulation time	75712341 ps
CPU time	1.25 seconds
Started	Feb 07 12:48:37 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	215272 kb
Host	smart-4c8b46c7-e490-4c57-b7c5-2518077868bc
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862830952 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d isable_auto_req_mode.1862830952
Directory	/workspace/23.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/23.edn_err.3353480294
Short name	T527
Test name
Test status
Simulation time	27026932 ps
CPU time	1.36 seconds
Started	Feb 07 12:48:29 PM PST 24
Finished	Feb 07 12:48:38 PM PST 24
Peak memory	229080 kb
Host	smart-90f2f5b7-6bec-4948-a5d7-2fd66908772c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3353480294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3353480294
Directory	/workspace/23.edn_err/latest

Test location	/workspace/coverage/default/23.edn_genbits.264137215
Short name	T553
Test name
Test status
Simulation time	35152825 ps
CPU time	1.27 seconds
Started	Feb 07 12:48:32 PM PST 24
Finished	Feb 07 12:48:40 PM PST 24
Peak memory	215384 kb
Host	smart-4a5288de-dcdd-43f8-bdec-8ed0b9bbccf3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=264137215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.264137215
Directory	/workspace/23.edn_genbits/latest

Test location	/workspace/coverage/default/23.edn_intr.2985327754
Short name	T850
Test name
Test status
Simulation time	22335349 ps
CPU time	1.2 seconds
Started	Feb 07 12:48:35 PM PST 24
Finished	Feb 07 12:48:42 PM PST 24
Peak memory	222576 kb
Host	smart-cff1c952-f7e8-4509-bb3b-c1decf8e03ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2985327754 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2985327754
Directory	/workspace/23.edn_intr/latest

Test location	/workspace/coverage/default/23.edn_smoke.1580969893
Short name	T727
Test name
Test status
Simulation time	30596666 ps
CPU time	0.91 seconds
Started	Feb 07 12:48:34 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	215028 kb
Host	smart-de049219-6b6e-47aa-bdc3-9923d3e04b0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1580969893 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1580969893
Directory	/workspace/23.edn_smoke/latest

Test location	/workspace/coverage/default/23.edn_stress_all.3558064580
Short name	T433
Test name
Test status
Simulation time	308717205 ps
CPU time	5.72 seconds
Started	Feb 07 12:48:32 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	214964 kb
Host	smart-cddea159-cb75-4e63-8e55-f923cac197b8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558064580 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3558064580
Directory	/workspace/23.edn_stress_all/latest

Test location	/workspace/coverage/default/23.edn_stress_all_with_rand_reset.2344622413
Short name	T499
Test name
Test status
Simulation time	13149325049 ps
CPU time	225.63 seconds
Started	Feb 07 12:48:31 PM PST 24
Finished	Feb 07 12:52:24 PM PST 24
Peak memory	216736 kb
Host	smart-f011abca-f467-48bb-a21c-8407eacc2f00
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344622413 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2344622413
Directory	/workspace/23.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/230.edn_genbits.2229539330
Short name	T355
Test name
Test status
Simulation time	34285761 ps
CPU time	1.24 seconds
Started	Feb 07 12:50:03 PM PST 24
Finished	Feb 07 12:50:06 PM PST 24
Peak memory	215388 kb
Host	smart-ab911749-2c9a-48ca-a6dc-9acbdce05e31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2229539330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2229539330
Directory	/workspace/230.edn_genbits/latest

Test location	/workspace/coverage/default/231.edn_genbits.3355170807
Short name	T845
Test name
Test status
Simulation time	226744405 ps
CPU time	2.6 seconds
Started	Feb 07 12:49:53 PM PST 24
Finished	Feb 07 12:49:57 PM PST 24
Peak memory	215552 kb
Host	smart-31736bd1-282d-46a6-9953-f2eb3335d4c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3355170807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3355170807
Directory	/workspace/231.edn_genbits/latest

Test location	/workspace/coverage/default/232.edn_genbits.1672914336
Short name	T611
Test name
Test status
Simulation time	57857117 ps
CPU time	1.19 seconds
Started	Feb 07 12:50:15 PM PST 24
Finished	Feb 07 12:50:18 PM PST 24
Peak memory	216588 kb
Host	smart-6cb58cde-52f8-4e58-ab9f-22f4f2e493a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1672914336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1672914336
Directory	/workspace/232.edn_genbits/latest

Test location	/workspace/coverage/default/233.edn_genbits.3566932440
Short name	T215
Test name
Test status
Simulation time	83041940 ps
CPU time	1.08 seconds
Started	Feb 07 12:50:16 PM PST 24
Finished	Feb 07 12:50:18 PM PST 24
Peak memory	215260 kb
Host	smart-b6b25c2e-60c9-4826-8f90-1f4da2b7de19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3566932440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3566932440
Directory	/workspace/233.edn_genbits/latest

Test location	/workspace/coverage/default/234.edn_genbits.3042779178
Short name	T632
Test name
Test status
Simulation time	33126032 ps
CPU time	1.39 seconds
Started	Feb 07 12:49:52 PM PST 24
Finished	Feb 07 12:49:54 PM PST 24
Peak memory	216516 kb
Host	smart-7dbc6d78-ad2a-4ab0-8a34-419bea20e200
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3042779178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3042779178
Directory	/workspace/234.edn_genbits/latest

Test location	/workspace/coverage/default/235.edn_genbits.2673018018
Short name	T805
Test name
Test status
Simulation time	39627144 ps
CPU time	1.45 seconds
Started	Feb 07 12:49:55 PM PST 24
Finished	Feb 07 12:49:58 PM PST 24
Peak memory	216724 kb
Host	smart-10188110-a533-490f-85a6-3ecc34682536
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2673018018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2673018018
Directory	/workspace/235.edn_genbits/latest

Test location	/workspace/coverage/default/236.edn_genbits.3238311512
Short name	T180
Test name
Test status
Simulation time	113489477 ps
CPU time	1.68 seconds
Started	Feb 07 12:49:52 PM PST 24
Finished	Feb 07 12:49:55 PM PST 24
Peak memory	215676 kb
Host	smart-c331c8c9-e138-4ece-a184-3e253d4f5df3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3238311512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3238311512
Directory	/workspace/236.edn_genbits/latest

Test location	/workspace/coverage/default/237.edn_genbits.2481932781
Short name	T559
Test name
Test status
Simulation time	42295401 ps
CPU time	1.29 seconds
Started	Feb 07 12:50:13 PM PST 24
Finished	Feb 07 12:50:16 PM PST 24
Peak memory	216892 kb
Host	smart-f251e9b7-8a99-4783-88b4-4a2104f76f6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2481932781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2481932781
Directory	/workspace/237.edn_genbits/latest

Test location	/workspace/coverage/default/238.edn_genbits.3654380775
Short name	T639
Test name
Test status
Simulation time	33816211 ps
CPU time	1.26 seconds
Started	Feb 07 12:50:09 PM PST 24
Finished	Feb 07 12:50:12 PM PST 24
Peak memory	215360 kb
Host	smart-90e7fdd4-399e-4d09-90ef-8488033f938a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3654380775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3654380775
Directory	/workspace/238.edn_genbits/latest

Test location	/workspace/coverage/default/239.edn_genbits.3955570371
Short name	T451
Test name
Test status
Simulation time	109675173 ps
CPU time	1.18 seconds
Started	Feb 07 12:49:59 PM PST 24
Finished	Feb 07 12:50:02 PM PST 24
Peak memory	215464 kb
Host	smart-9fc11b40-fcce-4369-ab1d-e20950424d32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3955570371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3955570371
Directory	/workspace/239.edn_genbits/latest

Test location	/workspace/coverage/default/24.edn_alert.2141697672
Short name	T225
Test name
Test status
Simulation time	45245250 ps
CPU time	0.99 seconds
Started	Feb 07 12:48:37 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	206224 kb
Host	smart-82e26197-d556-4cab-a916-7c28a8f4822d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2141697672 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2141697672
Directory	/workspace/24.edn_alert/latest

Test location	/workspace/coverage/default/24.edn_alert_test.2514783927
Short name	T99
Test name
Test status
Simulation time	49278325 ps
CPU time	0.9 seconds
Started	Feb 07 12:48:24 PM PST 24
Finished	Feb 07 12:48:35 PM PST 24
Peak memory	205372 kb
Host	smart-ba80acae-5232-4143-91a9-b9fc9dd08028
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514783927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2514783927
Directory	/workspace/24.edn_alert_test/latest

Test location	/workspace/coverage/default/24.edn_disable.1997831447
Short name	T112
Test name
Test status
Simulation time	13239574 ps
CPU time	0.92 seconds
Started	Feb 07 12:48:39 PM PST 24
Finished	Feb 07 12:48:45 PM PST 24
Peak memory	215264 kb
Host	smart-63bfb5ff-614c-4db0-bc3f-8168889e1422
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997831447 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1997831447
Directory	/workspace/24.edn_disable/latest

Test location	/workspace/coverage/default/24.edn_disable_auto_req_mode.1510798039
Short name	T577
Test name
Test status
Simulation time	39912876 ps
CPU time	1.05 seconds
Started	Feb 07 12:48:30 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	215356 kb
Host	smart-c28094b4-c63e-4640-88c2-e7134d0d1c93
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510798039 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d isable_auto_req_mode.1510798039
Directory	/workspace/24.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/24.edn_err.3849946694
Short name	T596
Test name
Test status
Simulation time	30567455 ps
CPU time	0.88 seconds
Started	Feb 07 12:48:26 PM PST 24
Finished	Feb 07 12:48:36 PM PST 24
Peak memory	216544 kb
Host	smart-52f88e7a-f97a-4505-bb9b-aac4f541d150
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3849946694 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3849946694
Directory	/workspace/24.edn_err/latest

Test location	/workspace/coverage/default/24.edn_intr.2282518583
Short name	T3
Test name
Test status
Simulation time	30971103 ps
CPU time	1 seconds
Started	Feb 07 12:48:42 PM PST 24
Finished	Feb 07 12:48:46 PM PST 24
Peak memory	222524 kb
Host	smart-b6e8d55e-83fc-4dff-9a5a-8bb9ef45c06b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2282518583 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2282518583
Directory	/workspace/24.edn_intr/latest

Test location	/workspace/coverage/default/24.edn_smoke.1552010113
Short name	T645
Test name
Test status
Simulation time	43059243 ps
CPU time	0.93 seconds
Started	Feb 07 12:48:37 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	215036 kb
Host	smart-7f2c6d1f-0502-438e-af42-bb455bd7df51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1552010113 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1552010113
Directory	/workspace/24.edn_smoke/latest

Test location	/workspace/coverage/default/24.edn_stress_all.1498859672
Short name	T489
Test name
Test status
Simulation time	166842688 ps
CPU time	3.58 seconds
Started	Feb 07 12:48:29 PM PST 24
Finished	Feb 07 12:48:40 PM PST 24
Peak memory	215052 kb
Host	smart-27d6d46a-84c8-40fa-9633-db949dedead8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498859672 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1498859672
Directory	/workspace/24.edn_stress_all/latest

Test location	/workspace/coverage/default/24.edn_stress_all_with_rand_reset.1046783506
Short name	T861
Test name
Test status
Simulation time	120008570188 ps
CPU time	929.27 seconds
Started	Feb 07 12:48:26 PM PST 24
Finished	Feb 07 01:04:05 PM PST 24
Peak memory	219236 kb
Host	smart-ccd8d564-8ec4-4dec-8173-4c6fca33d5ef
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046783506 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1046783506
Directory	/workspace/24.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/240.edn_genbits.4023088272
Short name	T685
Test name
Test status
Simulation time	56280148 ps
CPU time	1.88 seconds
Started	Feb 07 12:49:53 PM PST 24
Finished	Feb 07 12:49:56 PM PST 24
Peak memory	216436 kb
Host	smart-12f58b5f-029a-4e9b-af6a-51efab5784cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4023088272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.4023088272
Directory	/workspace/240.edn_genbits/latest

Test location	/workspace/coverage/default/241.edn_genbits.416228222
Short name	T197
Test name
Test status
Simulation time	134350429 ps
CPU time	1.19 seconds
Started	Feb 07 12:50:15 PM PST 24
Finished	Feb 07 12:50:17 PM PST 24
Peak memory	215660 kb
Host	smart-7dc0d865-4127-4d8f-b9ff-38766a111ad0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=416228222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.416228222
Directory	/workspace/241.edn_genbits/latest

Test location	/workspace/coverage/default/242.edn_genbits.1061190076
Short name	T239
Test name
Test status
Simulation time	79736572 ps
CPU time	2.81 seconds
Started	Feb 07 12:50:16 PM PST 24
Finished	Feb 07 12:50:20 PM PST 24
Peak memory	217604 kb
Host	smart-fc71f53d-7767-4042-b8c2-87be304b2761
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1061190076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1061190076
Directory	/workspace/242.edn_genbits/latest

Test location	/workspace/coverage/default/243.edn_genbits.1948867205
Short name	T807
Test name
Test status
Simulation time	26811088 ps
CPU time	1.21 seconds
Started	Feb 07 12:49:49 PM PST 24
Finished	Feb 07 12:49:52 PM PST 24
Peak memory	215452 kb
Host	smart-bad4ecec-a933-45e4-a948-35fa6cb98cc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1948867205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1948867205
Directory	/workspace/243.edn_genbits/latest

Test location	/workspace/coverage/default/244.edn_genbits.1196559636
Short name	T774
Test name
Test status
Simulation time	49948908 ps
CPU time	1.43 seconds
Started	Feb 07 12:49:58 PM PST 24
Finished	Feb 07 12:50:00 PM PST 24
Peak memory	216668 kb
Host	smart-c4ef8909-968c-4485-9903-a24b604df3f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1196559636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1196559636
Directory	/workspace/244.edn_genbits/latest

Test location	/workspace/coverage/default/245.edn_genbits.1280986292
Short name	T398
Test name
Test status
Simulation time	103058877 ps
CPU time	1.41 seconds
Started	Feb 07 12:50:05 PM PST 24
Finished	Feb 07 12:50:07 PM PST 24
Peak memory	216880 kb
Host	smart-2d002b1f-8a22-474a-899e-a44d6ade0f3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1280986292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1280986292
Directory	/workspace/245.edn_genbits/latest

Test location	/workspace/coverage/default/246.edn_genbits.3474539195
Short name	T177
Test name
Test status
Simulation time	88528276 ps
CPU time	1.21 seconds
Started	Feb 07 12:50:13 PM PST 24
Finished	Feb 07 12:50:16 PM PST 24
Peak memory	215400 kb
Host	smart-26325449-fc56-4e62-a469-c0e00cccc509
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3474539195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3474539195
Directory	/workspace/246.edn_genbits/latest

Test location	/workspace/coverage/default/247.edn_genbits.259642761
Short name	T190
Test name
Test status
Simulation time	52853071 ps
CPU time	1.2 seconds
Started	Feb 07 12:50:15 PM PST 24
Finished	Feb 07 12:50:17 PM PST 24
Peak memory	215548 kb
Host	smart-f78c0c0b-e23c-4ccb-90c8-fd219bca17a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=259642761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.259642761
Directory	/workspace/247.edn_genbits/latest

Test location	/workspace/coverage/default/248.edn_genbits.4081989228
Short name	T899
Test name
Test status
Simulation time	71737907 ps
CPU time	1.07 seconds
Started	Feb 07 12:50:16 PM PST 24
Finished	Feb 07 12:50:18 PM PST 24
Peak memory	215468 kb
Host	smart-6b8b7601-ad0f-4a18-b568-5525405196a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4081989228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.4081989228
Directory	/workspace/248.edn_genbits/latest

Test location	/workspace/coverage/default/249.edn_genbits.3141914511
Short name	T358
Test name
Test status
Simulation time	72292595 ps
CPU time	1.19 seconds
Started	Feb 07 12:50:00 PM PST 24
Finished	Feb 07 12:50:03 PM PST 24
Peak memory	216960 kb
Host	smart-5c138c67-c5f8-4468-a30b-16f2cb03be94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3141914511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3141914511
Directory	/workspace/249.edn_genbits/latest

Test location	/workspace/coverage/default/25.edn_alert_test.479811144
Short name	T449
Test name
Test status
Simulation time	23874357 ps
CPU time	0.84 seconds
Started	Feb 07 12:48:33 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	205676 kb
Host	smart-91b63492-715e-4e84-90fd-7213dcd829fd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479811144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.479811144
Directory	/workspace/25.edn_alert_test/latest

Test location	/workspace/coverage/default/25.edn_disable.603244067
Short name	T491
Test name
Test status
Simulation time	12943911 ps
CPU time	0.9 seconds
Started	Feb 07 12:48:38 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	214784 kb
Host	smart-82c6fae2-a2b7-4d89-9b34-032c96774671
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603244067 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.603244067
Directory	/workspace/25.edn_disable/latest

Test location	/workspace/coverage/default/25.edn_disable_auto_req_mode.1551496300
Short name	T531
Test name
Test status
Simulation time	35866570 ps
CPU time	1.53 seconds
Started	Feb 07 12:48:43 PM PST 24
Finished	Feb 07 12:48:47 PM PST 24
Peak memory	214612 kb
Host	smart-49cca86d-f9d0-4f2d-9c8b-24c711d19501
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551496300 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d isable_auto_req_mode.1551496300
Directory	/workspace/25.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/25.edn_err.3228474176
Short name	T388
Test name
Test status
Simulation time	19738747 ps
CPU time	1 seconds
Started	Feb 07 12:48:43 PM PST 24
Finished	Feb 07 12:48:47 PM PST 24
Peak memory	216644 kb
Host	smart-271b5419-3416-4e4f-a136-1ef3ba050d1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3228474176 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3228474176
Directory	/workspace/25.edn_err/latest

Test location	/workspace/coverage/default/25.edn_genbits.2242003990
Short name	T569
Test name
Test status
Simulation time	31482984 ps
CPU time	1.47 seconds
Started	Feb 07 12:48:30 PM PST 24
Finished	Feb 07 12:48:38 PM PST 24
Peak memory	215660 kb
Host	smart-d2d2e23a-91a9-4503-a216-011592d04486
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2242003990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2242003990
Directory	/workspace/25.edn_genbits/latest

Test location	/workspace/coverage/default/25.edn_intr.2520012249
Short name	T942
Test name
Test status
Simulation time	23324720 ps
CPU time	1.08 seconds
Started	Feb 07 12:48:33 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	214944 kb
Host	smart-d8a55ce5-14e8-48b6-84af-8f7829d17793
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2520012249 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2520012249
Directory	/workspace/25.edn_intr/latest

Test location	/workspace/coverage/default/25.edn_smoke.4219410685
Short name	T418
Test name
Test status
Simulation time	160229228 ps
CPU time	0.92 seconds
Started	Feb 07 12:48:37 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	215016 kb
Host	smart-a2341ed0-e8cc-4721-8c79-ae04c20ef01e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4219410685 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.4219410685
Directory	/workspace/25.edn_smoke/latest

Test location	/workspace/coverage/default/25.edn_stress_all.4190196880
Short name	T500
Test name
Test status
Simulation time	292571428 ps
CPU time	5.84 seconds
Started	Feb 07 12:48:42 PM PST 24
Finished	Feb 07 12:48:51 PM PST 24
Peak memory	215296 kb
Host	smart-638bfcc4-beed-4035-be17-99862d6af6f5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190196880 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.4190196880
Directory	/workspace/25.edn_stress_all/latest

Test location	/workspace/coverage/default/25.edn_stress_all_with_rand_reset.2527109692
Short name	T670
Test name
Test status
Simulation time	8436888082 ps
CPU time	175.53 seconds
Started	Feb 07 12:48:43 PM PST 24
Finished	Feb 07 12:51:41 PM PST 24
Peak memory	216880 kb
Host	smart-fdac0d6c-1827-430b-ae7e-9c81d68ba073
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527109692 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2527109692
Directory	/workspace/25.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/250.edn_genbits.2481866697
Short name	T952
Test name
Test status
Simulation time	111859334 ps
CPU time	1.57 seconds
Started	Feb 07 12:50:12 PM PST 24
Finished	Feb 07 12:50:15 PM PST 24
Peak memory	217088 kb
Host	smart-349f325a-4f18-49a9-9e65-5fe2117c16b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2481866697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2481866697
Directory	/workspace/250.edn_genbits/latest

Test location	/workspace/coverage/default/251.edn_genbits.3065336088
Short name	T551
Test name
Test status
Simulation time	61742389 ps
CPU time	1.14 seconds
Started	Feb 07 12:50:11 PM PST 24
Finished	Feb 07 12:50:14 PM PST 24
Peak memory	216744 kb
Host	smart-44192418-0ad7-498a-8b15-0bee56a91588
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3065336088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3065336088
Directory	/workspace/251.edn_genbits/latest

Test location	/workspace/coverage/default/252.edn_genbits.2581606759
Short name	T719
Test name
Test status
Simulation time	77368811 ps
CPU time	1.89 seconds
Started	Feb 07 12:50:08 PM PST 24
Finished	Feb 07 12:50:12 PM PST 24
Peak memory	216736 kb
Host	smart-bb049e00-306d-4809-8e95-24d1fdb30f51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2581606759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2581606759
Directory	/workspace/252.edn_genbits/latest

Test location	/workspace/coverage/default/253.edn_genbits.3578383680
Short name	T417
Test name
Test status
Simulation time	51683686 ps
CPU time	1.36 seconds
Started	Feb 07 12:50:18 PM PST 24
Finished	Feb 07 12:50:20 PM PST 24
Peak memory	215672 kb
Host	smart-e9004bc9-aedf-4612-8683-e4f7dc5df815
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3578383680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3578383680
Directory	/workspace/253.edn_genbits/latest

Test location	/workspace/coverage/default/254.edn_genbits.3686889569
Short name	T182
Test name
Test status
Simulation time	39832346 ps
CPU time	1.03 seconds
Started	Feb 07 12:50:03 PM PST 24
Finished	Feb 07 12:50:06 PM PST 24
Peak memory	215472 kb
Host	smart-2faa4fb7-2868-4878-8b0d-f4fee8c6e64b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3686889569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3686889569
Directory	/workspace/254.edn_genbits/latest

Test location	/workspace/coverage/default/255.edn_genbits.1194607906
Short name	T382
Test name
Test status
Simulation time	67975385 ps
CPU time	1.71 seconds
Started	Feb 07 12:50:06 PM PST 24
Finished	Feb 07 12:50:10 PM PST 24
Peak memory	216904 kb
Host	smart-8ab771b6-5716-4ec2-a8a4-513a8f99a125
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1194607906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1194607906
Directory	/workspace/255.edn_genbits/latest

Test location	/workspace/coverage/default/256.edn_genbits.1207826879
Short name	T538
Test name
Test status
Simulation time	58907289 ps
CPU time	2.23 seconds
Started	Feb 07 12:50:21 PM PST 24
Finished	Feb 07 12:50:24 PM PST 24
Peak memory	218232 kb
Host	smart-ebc1c022-337a-4ab3-9137-d150f3e2fba2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1207826879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1207826879
Directory	/workspace/256.edn_genbits/latest

Test location	/workspace/coverage/default/257.edn_genbits.4032951434
Short name	T795
Test name
Test status
Simulation time	50455695 ps
CPU time	1.32 seconds
Started	Feb 07 12:50:09 PM PST 24
Finished	Feb 07 12:50:12 PM PST 24
Peak memory	217868 kb
Host	smart-447dadec-5291-4b03-975f-eab5363a34d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4032951434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.4032951434
Directory	/workspace/257.edn_genbits/latest

Test location	/workspace/coverage/default/258.edn_genbits.548835461
Short name	T870
Test name
Test status
Simulation time	177719113 ps
CPU time	1.12 seconds
Started	Feb 07 12:50:14 PM PST 24
Finished	Feb 07 12:50:16 PM PST 24
Peak memory	215212 kb
Host	smart-f32db544-e80f-45c1-9d86-b32cb28fddc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=548835461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.548835461
Directory	/workspace/258.edn_genbits/latest

Test location	/workspace/coverage/default/259.edn_genbits.1246454481
Short name	T404
Test name
Test status
Simulation time	29825361 ps
CPU time	1.11 seconds
Started	Feb 07 12:50:07 PM PST 24
Finished	Feb 07 12:50:10 PM PST 24
Peak memory	215356 kb
Host	smart-14548f62-1baf-407d-9fa6-ca5ef8fc3646
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1246454481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1246454481
Directory	/workspace/259.edn_genbits/latest

Test location	/workspace/coverage/default/26.edn_alert.2748588327
Short name	T229
Test name
Test status
Simulation time	21032232 ps
CPU time	1.09 seconds
Started	Feb 07 12:48:39 PM PST 24
Finished	Feb 07 12:48:45 PM PST 24
Peak memory	205708 kb
Host	smart-b5bb3fbb-d0e5-47d9-9cd4-9ae800d891b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2748588327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2748588327
Directory	/workspace/26.edn_alert/latest

Test location	/workspace/coverage/default/26.edn_alert_test.2015168641
Short name	T419
Test name
Test status
Simulation time	26506644 ps
CPU time	0.93 seconds
Started	Feb 07 12:48:39 PM PST 24
Finished	Feb 07 12:48:45 PM PST 24
Peak memory	206152 kb
Host	smart-e60b2c5f-f208-4926-a1a6-093e0f596fc6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015168641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2015168641
Directory	/workspace/26.edn_alert_test/latest

Test location	/workspace/coverage/default/26.edn_disable.2206384687
Short name	T760
Test name
Test status
Simulation time	38339156 ps
CPU time	0.82 seconds
Started	Feb 07 12:48:39 PM PST 24
Finished	Feb 07 12:48:45 PM PST 24
Peak memory	214940 kb
Host	smart-9f2a4a8e-fb06-4fa1-ba3c-83d523c8bfa7
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206384687 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2206384687
Directory	/workspace/26.edn_disable/latest

Test location	/workspace/coverage/default/26.edn_disable_auto_req_mode.1033691603
Short name	T889
Test name
Test status
Simulation time	120306767 ps
CPU time	1.17 seconds
Started	Feb 07 12:48:34 PM PST 24
Finished	Feb 07 12:48:40 PM PST 24
Peak memory	215316 kb
Host	smart-8b521bf3-3014-4573-8874-eaf9fd308f1c
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033691603 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d isable_auto_req_mode.1033691603
Directory	/workspace/26.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/26.edn_err.1212154582
Short name	T459
Test name
Test status
Simulation time	29595280 ps
CPU time	1.16 seconds
Started	Feb 07 12:48:39 PM PST 24
Finished	Feb 07 12:48:45 PM PST 24
Peak memory	217860 kb
Host	smart-eb9a1d59-5c35-4253-963a-d523bca878e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1212154582 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1212154582
Directory	/workspace/26.edn_err/latest

Test location	/workspace/coverage/default/26.edn_genbits.1203216189
Short name	T207
Test name
Test status
Simulation time	20019597 ps
CPU time	1.01 seconds
Started	Feb 07 12:48:30 PM PST 24
Finished	Feb 07 12:48:38 PM PST 24
Peak memory	215480 kb
Host	smart-aad575d6-a294-4604-8b44-88939b748e78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1203216189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1203216189
Directory	/workspace/26.edn_genbits/latest

Test location	/workspace/coverage/default/26.edn_smoke.3232939386
Short name	T378
Test name
Test status
Simulation time	33105644 ps
CPU time	0.9 seconds
Started	Feb 07 12:48:35 PM PST 24
Finished	Feb 07 12:48:43 PM PST 24
Peak memory	215048 kb
Host	smart-169d38b5-6636-41af-9ad7-8a445b12b0f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3232939386 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3232939386
Directory	/workspace/26.edn_smoke/latest

Test location	/workspace/coverage/default/26.edn_stress_all.1542858999
Short name	T201
Test name
Test status
Simulation time	279649467 ps
CPU time	3.3 seconds
Started	Feb 07 12:48:39 PM PST 24
Finished	Feb 07 12:48:47 PM PST 24
Peak memory	215364 kb
Host	smart-6a2dfc61-a020-4bf9-8908-238e9b57ada4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542858999 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1542858999
Directory	/workspace/26.edn_stress_all/latest

Test location	/workspace/coverage/default/26.edn_stress_all_with_rand_reset.2438271131
Short name	T536
Test name
Test status
Simulation time	45162725061 ps
CPU time	1001.94 seconds
Started	Feb 07 12:48:24 PM PST 24
Finished	Feb 07 01:05:17 PM PST 24
Peak memory	223404 kb
Host	smart-62149204-38ac-4524-bb1f-6d4f0b01a590
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438271131 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2438271131
Directory	/workspace/26.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/261.edn_genbits.2751220128
Short name	T415
Test name
Test status
Simulation time	121451822 ps
CPU time	1.67 seconds
Started	Feb 07 12:50:02 PM PST 24
Finished	Feb 07 12:50:05 PM PST 24
Peak memory	216912 kb
Host	smart-ffeca175-8577-40bc-b048-1723e84c953e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2751220128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2751220128
Directory	/workspace/261.edn_genbits/latest

Test location	/workspace/coverage/default/262.edn_genbits.4273395549
Short name	T200
Test name
Test status
Simulation time	114124612 ps
CPU time	1.72 seconds
Started	Feb 07 12:50:08 PM PST 24
Finished	Feb 07 12:50:11 PM PST 24
Peak memory	216772 kb
Host	smart-ea8dc0bd-6d5d-4db2-a5af-8c56f6786cd3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4273395549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.4273395549
Directory	/workspace/262.edn_genbits/latest

Test location	/workspace/coverage/default/263.edn_genbits.3360816639
Short name	T548
Test name
Test status
Simulation time	348897844 ps
CPU time	3.62 seconds
Started	Feb 07 12:50:06 PM PST 24
Finished	Feb 07 12:50:11 PM PST 24
Peak memory	218216 kb
Host	smart-071ff269-b31c-463e-b656-ad15a7e4650e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3360816639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3360816639
Directory	/workspace/263.edn_genbits/latest

Test location	/workspace/coverage/default/264.edn_genbits.3608173963
Short name	T609
Test name
Test status
Simulation time	92053330 ps
CPU time	1.41 seconds
Started	Feb 07 12:50:10 PM PST 24
Finished	Feb 07 12:50:13 PM PST 24
Peak memory	217100 kb
Host	smart-526b253c-afea-4d26-b6e6-5b9b270b09a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3608173963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3608173963
Directory	/workspace/264.edn_genbits/latest

Test location	/workspace/coverage/default/265.edn_genbits.820100083
Short name	T392
Test name
Test status
Simulation time	71622373 ps
CPU time	1.34 seconds
Started	Feb 07 12:50:02 PM PST 24
Finished	Feb 07 12:50:05 PM PST 24
Peak memory	216956 kb
Host	smart-437c679f-b6a4-4074-beb3-116c37328b56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=820100083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.820100083
Directory	/workspace/265.edn_genbits/latest

Test location	/workspace/coverage/default/266.edn_genbits.2384815101
Short name	T437
Test name
Test status
Simulation time	40772173 ps
CPU time	1.5 seconds
Started	Feb 07 12:50:18 PM PST 24
Finished	Feb 07 12:50:20 PM PST 24
Peak memory	214972 kb
Host	smart-f0399ea2-1ede-43da-aaf2-ed87ced6162f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2384815101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2384815101
Directory	/workspace/266.edn_genbits/latest

Test location	/workspace/coverage/default/267.edn_genbits.958058404
Short name	T496
Test name
Test status
Simulation time	45169045 ps
CPU time	1.54 seconds
Started	Feb 07 12:50:09 PM PST 24
Finished	Feb 07 12:50:12 PM PST 24
Peak memory	216696 kb
Host	smart-89668518-b1db-4d09-bac4-57a6a7ae2afc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=958058404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.958058404
Directory	/workspace/267.edn_genbits/latest

Test location	/workspace/coverage/default/268.edn_genbits.1099422570
Short name	T28
Test name
Test status
Simulation time	50851627 ps
CPU time	1.48 seconds
Started	Feb 07 12:50:09 PM PST 24
Finished	Feb 07 12:50:12 PM PST 24
Peak memory	216624 kb
Host	smart-26726d44-a940-4039-a009-0016101c8231
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1099422570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1099422570
Directory	/workspace/268.edn_genbits/latest

Test location	/workspace/coverage/default/269.edn_genbits.351543339
Short name	T630
Test name
Test status
Simulation time	57252603 ps
CPU time	1.07 seconds
Started	Feb 07 12:50:08 PM PST 24
Finished	Feb 07 12:50:11 PM PST 24
Peak memory	215644 kb
Host	smart-0831d7b5-3c26-4121-955f-8ef7fd3ba4bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=351543339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.351543339
Directory	/workspace/269.edn_genbits/latest

Test location	/workspace/coverage/default/27.edn_alert.2579952387
Short name	T887
Test name
Test status
Simulation time	31572144 ps
CPU time	1.02 seconds
Started	Feb 07 12:48:31 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	205960 kb
Host	smart-fd638bc1-e98f-4ac7-8776-c9802a1392bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2579952387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2579952387
Directory	/workspace/27.edn_alert/latest

Test location	/workspace/coverage/default/27.edn_alert_test.901904745
Short name	T348
Test name
Test status
Simulation time	14261965 ps
CPU time	0.9 seconds
Started	Feb 07 12:48:34 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	205400 kb
Host	smart-6157699d-6d6a-4e05-970c-92ed01c6d24c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901904745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.901904745
Directory	/workspace/27.edn_alert_test/latest

Test location	/workspace/coverage/default/27.edn_disable.2447903903
Short name	T755
Test name
Test status
Simulation time	11574793 ps
CPU time	0.87 seconds
Started	Feb 07 12:48:39 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	215060 kb
Host	smart-acd56060-71af-4038-9f55-a1c330b5ccaa
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447903903 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2447903903
Directory	/workspace/27.edn_disable/latest

Test location	/workspace/coverage/default/27.edn_disable_auto_req_mode.3948594502
Short name	T901
Test name
Test status
Simulation time	52283834 ps
CPU time	1.16 seconds
Started	Feb 07 12:48:36 PM PST 24
Finished	Feb 07 12:48:43 PM PST 24
Peak memory	216664 kb
Host	smart-9a5bc0c9-6c86-430c-8416-056f7cccc837
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948594502 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d isable_auto_req_mode.3948594502
Directory	/workspace/27.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/27.edn_err.2390483376
Short name	T375
Test name
Test status
Simulation time	155576284 ps
CPU time	1.04 seconds
Started	Feb 07 12:48:34 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	217712 kb
Host	smart-c71b4adc-9793-4f0f-afaf-942bac97017f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2390483376 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2390483376
Directory	/workspace/27.edn_err/latest

Test location	/workspace/coverage/default/27.edn_genbits.4004576201
Short name	T633
Test name
Test status
Simulation time	115695923 ps
CPU time	2.39 seconds
Started	Feb 07 12:48:29 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	217756 kb
Host	smart-03e4542e-33af-4d74-b8b2-a7b63b05891b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4004576201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.4004576201
Directory	/workspace/27.edn_genbits/latest

Test location	/workspace/coverage/default/27.edn_intr.815144155
Short name	T778
Test name
Test status
Simulation time	60559205 ps
CPU time	0.82 seconds
Started	Feb 07 12:48:33 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	215052 kb
Host	smart-6e94e1ea-0e9f-4802-bf79-973649677db9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=815144155 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.815144155
Directory	/workspace/27.edn_intr/latest

Test location	/workspace/coverage/default/27.edn_smoke.4291119148
Short name	T347
Test name
Test status
Simulation time	15176341 ps
CPU time	0.99 seconds
Started	Feb 07 12:48:31 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	214980 kb
Host	smart-7312b0d6-d3ec-4d8a-b520-e9d8ccafd10d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4291119148 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.4291119148
Directory	/workspace/27.edn_smoke/latest

Test location	/workspace/coverage/default/27.edn_stress_all.1349162106
Short name	T836
Test name
Test status
Simulation time	471530419 ps
CPU time	4.68 seconds
Started	Feb 07 12:48:37 PM PST 24
Finished	Feb 07 12:48:48 PM PST 24
Peak memory	216768 kb
Host	smart-19a16c48-2f4a-4207-a9b2-1a881fc4952f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349162106 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1349162106
Directory	/workspace/27.edn_stress_all/latest

Test location	/workspace/coverage/default/27.edn_stress_all_with_rand_reset.184270684
Short name	T763
Test name
Test status
Simulation time	161609035417 ps
CPU time	1018.23 seconds
Started	Feb 07 12:48:38 PM PST 24
Finished	Feb 07 01:05:42 PM PST 24
Peak memory	221032 kb
Host	smart-eb6d38b8-7e9e-4290-9bd9-ad0816a37ad8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184270684 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.184270684
Directory	/workspace/27.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/270.edn_genbits.937128877
Short name	T172
Test name
Test status
Simulation time	67609625 ps
CPU time	1.41 seconds
Started	Feb 07 12:50:05 PM PST 24
Finished	Feb 07 12:50:07 PM PST 24
Peak memory	216640 kb
Host	smart-92e10c4f-fd16-41c2-87ac-118cf89b72f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=937128877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.937128877
Directory	/workspace/270.edn_genbits/latest

Test location	/workspace/coverage/default/271.edn_genbits.2180074802
Short name	T371
Test name
Test status
Simulation time	105128331 ps
CPU time	1.14 seconds
Started	Feb 07 12:50:12 PM PST 24
Finished	Feb 07 12:50:14 PM PST 24
Peak memory	216780 kb
Host	smart-4bace080-e267-41a8-8582-b67bcfb5e2e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2180074802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2180074802
Directory	/workspace/271.edn_genbits/latest

Test location	/workspace/coverage/default/272.edn_genbits.835035349
Short name	T89
Test name
Test status
Simulation time	32286003 ps
CPU time	1.39 seconds
Started	Feb 07 12:50:00 PM PST 24
Finished	Feb 07 12:50:04 PM PST 24
Peak memory	215656 kb
Host	smart-9be283da-4c9c-47bd-a9fe-8646d5f356dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=835035349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.835035349
Directory	/workspace/272.edn_genbits/latest

Test location	/workspace/coverage/default/273.edn_genbits.2601720888
Short name	T940
Test name
Test status
Simulation time	125171467 ps
CPU time	1.66 seconds
Started	Feb 07 12:50:02 PM PST 24
Finished	Feb 07 12:50:05 PM PST 24
Peak memory	215484 kb
Host	smart-a6e229f3-7828-40d5-ae8a-1c768ab306b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2601720888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2601720888
Directory	/workspace/273.edn_genbits/latest

Test location	/workspace/coverage/default/274.edn_genbits.1697935772
Short name	T873
Test name
Test status
Simulation time	54066907 ps
CPU time	1.69 seconds
Started	Feb 07 12:50:13 PM PST 24
Finished	Feb 07 12:50:16 PM PST 24
Peak memory	216584 kb
Host	smart-6f061b77-91a1-45d4-b315-3174c114bd54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1697935772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1697935772
Directory	/workspace/274.edn_genbits/latest

Test location	/workspace/coverage/default/275.edn_genbits.592218006
Short name	T927
Test name
Test status
Simulation time	45424621 ps
CPU time	1.59 seconds
Started	Feb 07 12:50:12 PM PST 24
Finished	Feb 07 12:50:15 PM PST 24
Peak memory	216668 kb
Host	smart-0a5754a3-5597-46cd-9154-504324685949
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592218006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.592218006
Directory	/workspace/275.edn_genbits/latest

Test location	/workspace/coverage/default/276.edn_genbits.1862123497
Short name	T381
Test name
Test status
Simulation time	46093256 ps
CPU time	1.15 seconds
Started	Feb 07 12:50:12 PM PST 24
Finished	Feb 07 12:50:14 PM PST 24
Peak memory	215672 kb
Host	smart-f65236ba-9b1a-429b-abca-02ecfeaa34f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1862123497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1862123497
Directory	/workspace/276.edn_genbits/latest

Test location	/workspace/coverage/default/277.edn_genbits.4065441777
Short name	T751
Test name
Test status
Simulation time	30604746 ps
CPU time	1.29 seconds
Started	Feb 07 12:50:13 PM PST 24
Finished	Feb 07 12:50:15 PM PST 24
Peak memory	216612 kb
Host	smart-bd2d49c7-3955-4059-879e-c06f08445787
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4065441777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.4065441777
Directory	/workspace/277.edn_genbits/latest

Test location	/workspace/coverage/default/278.edn_genbits.157728122
Short name	T770
Test name
Test status
Simulation time	32549150 ps
CPU time	1.26 seconds
Started	Feb 07 12:50:21 PM PST 24
Finished	Feb 07 12:50:23 PM PST 24
Peak memory	216568 kb
Host	smart-bbaf4477-debf-4fb1-915b-bc7c3aeac324
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=157728122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.157728122
Directory	/workspace/278.edn_genbits/latest

Test location	/workspace/coverage/default/279.edn_genbits.802962762
Short name	T421
Test name
Test status
Simulation time	41442202 ps
CPU time	1.41 seconds
Started	Feb 07 12:50:05 PM PST 24
Finished	Feb 07 12:50:08 PM PST 24
Peak memory	216768 kb
Host	smart-5695f421-0e1c-4fa2-a098-1780ed5d8c8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=802962762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.802962762
Directory	/workspace/279.edn_genbits/latest

Test location	/workspace/coverage/default/28.edn_alert.2873568669
Short name	T12
Test name
Test status
Simulation time	25224577 ps
CPU time	0.98 seconds
Started	Feb 07 12:48:31 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	206200 kb
Host	smart-b6ec11e4-1eb1-4490-9662-a73e336a47fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2873568669 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2873568669
Directory	/workspace/28.edn_alert/latest

Test location	/workspace/coverage/default/28.edn_alert_test.898097416
Short name	T954
Test name
Test status
Simulation time	19474549 ps
CPU time	0.97 seconds
Started	Feb 07 12:48:38 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	205956 kb
Host	smart-95539743-d46e-489a-9026-72beef38fed8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898097416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.898097416
Directory	/workspace/28.edn_alert_test/latest

Test location	/workspace/coverage/default/28.edn_disable.1532814061
Short name	T430
Test name
Test status
Simulation time	45783059 ps
CPU time	0.88 seconds
Started	Feb 07 12:48:39 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	214792 kb
Host	smart-1ed04557-a6d9-42f1-9bb0-9e2364acef7a
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532814061 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1532814061
Directory	/workspace/28.edn_disable/latest

Test location	/workspace/coverage/default/28.edn_disable_auto_req_mode.659442667
Short name	T660
Test name
Test status
Simulation time	86093332 ps
CPU time	0.99 seconds
Started	Feb 07 12:48:35 PM PST 24
Finished	Feb 07 12:48:41 PM PST 24
Peak memory	215268 kb
Host	smart-3e73d5bf-8f13-424c-a3fb-863271a2bec7
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659442667 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di sable_auto_req_mode.659442667
Directory	/workspace/28.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/28.edn_err.2971220325
Short name	T590
Test name
Test status
Simulation time	21884328 ps
CPU time	1.19 seconds
Started	Feb 07 12:48:37 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	222464 kb
Host	smart-c280a1f7-f415-42bb-b393-aafeae9a2954
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2971220325 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2971220325
Directory	/workspace/28.edn_err/latest

Test location	/workspace/coverage/default/28.edn_genbits.2511847471
Short name	T833
Test name
Test status
Simulation time	58884411 ps
CPU time	2.13 seconds
Started	Feb 07 12:48:41 PM PST 24
Finished	Feb 07 12:48:46 PM PST 24
Peak memory	216532 kb
Host	smart-510b4071-962e-4f77-a709-8d084a460204
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2511847471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2511847471
Directory	/workspace/28.edn_genbits/latest

Test location	/workspace/coverage/default/28.edn_intr.262647102
Short name	T912
Test name
Test status
Simulation time	37426952 ps
CPU time	0.89 seconds
Started	Feb 07 12:48:37 PM PST 24
Finished	Feb 07 12:48:43 PM PST 24
Peak memory	214972 kb
Host	smart-c684ccf3-d896-45b4-9cd7-0bf0399b7121
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=262647102 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.262647102
Directory	/workspace/28.edn_intr/latest

Test location	/workspace/coverage/default/28.edn_smoke.1589128637
Short name	T416
Test name
Test status
Simulation time	63114588 ps
CPU time	0.93 seconds
Started	Feb 07 12:48:43 PM PST 24
Finished	Feb 07 12:48:47 PM PST 24
Peak memory	214924 kb
Host	smart-dfc28c5f-947d-4d48-a30e-9d2436890158
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1589128637 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1589128637
Directory	/workspace/28.edn_smoke/latest

Test location	/workspace/coverage/default/28.edn_stress_all.3329027550
Short name	T490
Test name
Test status
Simulation time	518751857 ps
CPU time	5.4 seconds
Started	Feb 07 12:48:39 PM PST 24
Finished	Feb 07 12:48:50 PM PST 24
Peak memory	215108 kb
Host	smart-77665811-355f-4c38-b22d-f3585f8ac64d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329027550 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3329027550
Directory	/workspace/28.edn_stress_all/latest

Test location	/workspace/coverage/default/28.edn_stress_all_with_rand_reset.3936538048
Short name	T775
Test name
Test status
Simulation time	100976001275 ps
CPU time	654.63 seconds
Started	Feb 07 12:48:37 PM PST 24
Finished	Feb 07 12:59:37 PM PST 24
Peak memory	219944 kb
Host	smart-a98309bf-7c6a-404c-8e11-10ecdc3cd72f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936538048 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3936538048
Directory	/workspace/28.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/280.edn_genbits.3290414653
Short name	T9
Test name
Test status
Simulation time	86899600 ps
CPU time	1.22 seconds
Started	Feb 07 12:50:16 PM PST 24
Finished	Feb 07 12:50:18 PM PST 24
Peak memory	217380 kb
Host	smart-0a607318-87fe-4722-a172-3cf072a35b50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3290414653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3290414653
Directory	/workspace/280.edn_genbits/latest

Test location	/workspace/coverage/default/281.edn_genbits.3077589037
Short name	T602
Test name
Test status
Simulation time	116441781 ps
CPU time	1.02 seconds
Started	Feb 07 12:50:20 PM PST 24
Finished	Feb 07 12:50:22 PM PST 24
Peak memory	215440 kb
Host	smart-dd8cb88b-f9eb-4230-ad32-faf3a4343f70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3077589037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3077589037
Directory	/workspace/281.edn_genbits/latest

Test location	/workspace/coverage/default/282.edn_genbits.551102300
Short name	T881
Test name
Test status
Simulation time	87441215 ps
CPU time	1.18 seconds
Started	Feb 07 12:50:11 PM PST 24
Finished	Feb 07 12:50:14 PM PST 24
Peak memory	217548 kb
Host	smart-443a4f75-66e3-4625-b559-41bb401ef9c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=551102300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.551102300
Directory	/workspace/282.edn_genbits/latest

Test location	/workspace/coverage/default/283.edn_genbits.1084359884
Short name	T738
Test name
Test status
Simulation time	211232380 ps
CPU time	1.03 seconds
Started	Feb 07 12:50:06 PM PST 24
Finished	Feb 07 12:50:09 PM PST 24
Peak memory	215356 kb
Host	smart-b23456b8-ffba-4399-b2dd-01cb076310e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1084359884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1084359884
Directory	/workspace/283.edn_genbits/latest

Test location	/workspace/coverage/default/284.edn_genbits.2435542234
Short name	T438
Test name
Test status
Simulation time	23778441 ps
CPU time	1.09 seconds
Started	Feb 07 12:50:16 PM PST 24
Finished	Feb 07 12:50:19 PM PST 24
Peak memory	215400 kb
Host	smart-592a0525-6d00-42fb-b569-4a41a1dac171
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2435542234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2435542234
Directory	/workspace/284.edn_genbits/latest

Test location	/workspace/coverage/default/285.edn_genbits.2798292913
Short name	T842
Test name
Test status
Simulation time	32285765 ps
CPU time	1.4 seconds
Started	Feb 07 12:50:20 PM PST 24
Finished	Feb 07 12:50:22 PM PST 24
Peak memory	216828 kb
Host	smart-9da409f1-4061-42cd-becf-0f3e97880fc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2798292913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2798292913
Directory	/workspace/285.edn_genbits/latest

Test location	/workspace/coverage/default/286.edn_genbits.3650002655
Short name	T217
Test name
Test status
Simulation time	73709089 ps
CPU time	1.1 seconds
Started	Feb 07 12:50:12 PM PST 24
Finished	Feb 07 12:50:14 PM PST 24
Peak memory	215396 kb
Host	smart-030930b2-8add-41da-bb8d-4987e6a0abea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3650002655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3650002655
Directory	/workspace/286.edn_genbits/latest

Test location	/workspace/coverage/default/287.edn_genbits.2816724753
Short name	T743
Test name
Test status
Simulation time	41642677 ps
CPU time	1.34 seconds
Started	Feb 07 12:50:15 PM PST 24
Finished	Feb 07 12:50:17 PM PST 24
Peak memory	216344 kb
Host	smart-82ce48e0-5c6e-4b94-98b4-07cd3270bcad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2816724753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2816724753
Directory	/workspace/287.edn_genbits/latest

Test location	/workspace/coverage/default/288.edn_genbits.3516623659
Short name	T844
Test name
Test status
Simulation time	42484093 ps
CPU time	1.51 seconds
Started	Feb 07 12:50:01 PM PST 24
Finished	Feb 07 12:50:05 PM PST 24
Peak memory	216608 kb
Host	smart-403ace7e-cc52-4928-8652-c0287ed7f844
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3516623659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3516623659
Directory	/workspace/288.edn_genbits/latest

Test location	/workspace/coverage/default/289.edn_genbits.1674329215
Short name	T840
Test name
Test status
Simulation time	46627272 ps
CPU time	1.18 seconds
Started	Feb 07 12:50:20 PM PST 24
Finished	Feb 07 12:50:22 PM PST 24
Peak memory	215420 kb
Host	smart-5e3c0576-7391-4ffd-95d4-c7f9127509a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1674329215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1674329215
Directory	/workspace/289.edn_genbits/latest

Test location	/workspace/coverage/default/29.edn_alert.238890489
Short name	T92
Test name
Test status
Simulation time	68456187 ps
CPU time	0.99 seconds
Started	Feb 07 12:48:34 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	205932 kb
Host	smart-ae0305de-5d4b-4992-b616-18548480acef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=238890489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.238890489
Directory	/workspace/29.edn_alert/latest

Test location	/workspace/coverage/default/29.edn_alert_test.4180119559
Short name	T903
Test name
Test status
Simulation time	47594775 ps
CPU time	0.86 seconds
Started	Feb 07 12:48:40 PM PST 24
Finished	Feb 07 12:48:45 PM PST 24
Peak memory	205452 kb
Host	smart-872c1798-a6ab-4f80-9d22-911ae8ac9992
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180119559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.4180119559
Directory	/workspace/29.edn_alert_test/latest

Test location	/workspace/coverage/default/29.edn_disable.4156591558
Short name	T116
Test name
Test status
Simulation time	21849806 ps
CPU time	0.87 seconds
Started	Feb 07 12:48:40 PM PST 24
Finished	Feb 07 12:48:45 PM PST 24
Peak memory	215108 kb
Host	smart-f512f98c-e072-4c0e-a1e2-6e488c020984
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156591558 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.4156591558
Directory	/workspace/29.edn_disable/latest

Test location	/workspace/coverage/default/29.edn_err.120318567
Short name	T846
Test name
Test status
Simulation time	21529533 ps
CPU time	0.99 seconds
Started	Feb 07 12:48:35 PM PST 24
Finished	Feb 07 12:48:40 PM PST 24
Peak memory	216808 kb
Host	smart-31f0ef31-cd49-43f8-885e-94565de185cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=120318567 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.120318567
Directory	/workspace/29.edn_err/latest

Test location	/workspace/coverage/default/29.edn_genbits.4056650223
Short name	T589
Test name
Test status
Simulation time	42158733 ps
CPU time	1.22 seconds
Started	Feb 07 12:48:39 PM PST 24
Finished	Feb 07 12:48:45 PM PST 24
Peak memory	215568 kb
Host	smart-f02a8658-8d1d-49a6-8bff-b3802feb9c4b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4056650223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.4056650223
Directory	/workspace/29.edn_genbits/latest

Test location	/workspace/coverage/default/29.edn_intr.3368575877
Short name	T573
Test name
Test status
Simulation time	41045276 ps
CPU time	0.9 seconds
Started	Feb 07 12:48:41 PM PST 24
Finished	Feb 07 12:48:45 PM PST 24
Peak memory	215216 kb
Host	smart-ff2d59d8-eda1-4967-a45c-79f3f34e6ec7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3368575877 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3368575877
Directory	/workspace/29.edn_intr/latest

Test location	/workspace/coverage/default/29.edn_smoke.1136402287
Short name	T949
Test name
Test status
Simulation time	32761741 ps
CPU time	0.86 seconds
Started	Feb 07 12:48:50 PM PST 24
Finished	Feb 07 12:48:52 PM PST 24
Peak memory	215012 kb
Host	smart-e0bcaced-61d4-443b-bcd3-6dd0da00aa2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1136402287 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1136402287
Directory	/workspace/29.edn_smoke/latest

Test location	/workspace/coverage/default/29.edn_stress_all.3972840446
Short name	T677
Test name
Test status
Simulation time	1339322964 ps
CPU time	4.1 seconds
Started	Feb 07 12:48:38 PM PST 24
Finished	Feb 07 12:48:48 PM PST 24
Peak memory	215036 kb
Host	smart-71a51bb9-a3cc-443a-823e-93e54ab14eed
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972840446 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3972840446
Directory	/workspace/29.edn_stress_all/latest

Test location	/workspace/coverage/default/29.edn_stress_all_with_rand_reset.1806328612
Short name	T210
Test name
Test status
Simulation time	38477687000 ps
CPU time	839.28 seconds
Started	Feb 07 12:48:39 PM PST 24
Finished	Feb 07 01:02:43 PM PST 24
Peak memory	216964 kb
Host	smart-4f34ccce-a5a7-47a8-99db-313984260bad
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806328612 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1806328612
Directory	/workspace/29.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/290.edn_genbits.1624010745
Short name	T212
Test name
Test status
Simulation time	94882264 ps
CPU time	1.33 seconds
Started	Feb 07 12:50:13 PM PST 24
Finished	Feb 07 12:50:16 PM PST 24
Peak memory	216872 kb
Host	smart-43ccfd18-eb7e-4d43-ac24-3ef88a3b411d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1624010745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1624010745
Directory	/workspace/290.edn_genbits/latest

Test location	/workspace/coverage/default/291.edn_genbits.2356629127
Short name	T495
Test name
Test status
Simulation time	66289202 ps
CPU time	1.03 seconds
Started	Feb 07 12:50:06 PM PST 24
Finished	Feb 07 12:50:09 PM PST 24
Peak memory	215424 kb
Host	smart-3d75aed1-c7fa-4a32-a507-982c4d6a8662
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2356629127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2356629127
Directory	/workspace/291.edn_genbits/latest

Test location	/workspace/coverage/default/292.edn_genbits.1827663290
Short name	T350
Test name
Test status
Simulation time	55212664 ps
CPU time	1.16 seconds
Started	Feb 07 12:50:13 PM PST 24
Finished	Feb 07 12:50:15 PM PST 24
Peak memory	215244 kb
Host	smart-3ea31568-7c77-446c-ab1c-f5518a56f097
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1827663290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1827663290
Directory	/workspace/292.edn_genbits/latest

Test location	/workspace/coverage/default/293.edn_genbits.2529333752
Short name	T753
Test name
Test status
Simulation time	134667886 ps
CPU time	2.72 seconds
Started	Feb 07 12:50:13 PM PST 24
Finished	Feb 07 12:50:16 PM PST 24
Peak memory	217584 kb
Host	smart-4320b45d-2e57-4759-b380-7bc0397cf79c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2529333752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2529333752
Directory	/workspace/293.edn_genbits/latest

Test location	/workspace/coverage/default/294.edn_genbits.334152715
Short name	T170
Test name
Test status
Simulation time	41243823 ps
CPU time	1.51 seconds
Started	Feb 07 12:50:21 PM PST 24
Finished	Feb 07 12:50:23 PM PST 24
Peak memory	215412 kb
Host	smart-4ea96edf-dd06-42c7-ac02-20979b85158d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=334152715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.334152715
Directory	/workspace/294.edn_genbits/latest

Test location	/workspace/coverage/default/295.edn_genbits.606586879
Short name	T78
Test name
Test status
Simulation time	55151717 ps
CPU time	1.31 seconds
Started	Feb 07 12:50:19 PM PST 24
Finished	Feb 07 12:50:22 PM PST 24
Peak memory	216868 kb
Host	smart-f822efd8-d6fc-4c19-92cb-1f5193c96817
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=606586879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.606586879
Directory	/workspace/295.edn_genbits/latest

Test location	/workspace/coverage/default/296.edn_genbits.3810974405
Short name	T806
Test name
Test status
Simulation time	288715897 ps
CPU time	1.4 seconds
Started	Feb 07 12:50:10 PM PST 24
Finished	Feb 07 12:50:13 PM PST 24
Peak memory	215628 kb
Host	smart-22082c34-9cd7-452f-b80e-06f89ba0eb1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3810974405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3810974405
Directory	/workspace/296.edn_genbits/latest

Test location	/workspace/coverage/default/297.edn_genbits.112182917
Short name	T76
Test name
Test status
Simulation time	131144470 ps
CPU time	1.24 seconds
Started	Feb 07 12:50:22 PM PST 24
Finished	Feb 07 12:50:24 PM PST 24
Peak memory	215480 kb
Host	smart-437ce742-fb3a-4c97-9d3e-04f255699220
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=112182917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.112182917
Directory	/workspace/297.edn_genbits/latest

Test location	/workspace/coverage/default/298.edn_genbits.3884941750
Short name	T892
Test name
Test status
Simulation time	42051706 ps
CPU time	1.66 seconds
Started	Feb 07 12:50:22 PM PST 24
Finished	Feb 07 12:50:24 PM PST 24
Peak memory	217460 kb
Host	smart-30c84e28-1d4d-4ea8-8d78-aaf126e0882f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3884941750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3884941750
Directory	/workspace/298.edn_genbits/latest

Test location	/workspace/coverage/default/299.edn_genbits.3689781173
Short name	T724
Test name
Test status
Simulation time	68102490 ps
CPU time	1.06 seconds
Started	Feb 07 12:50:12 PM PST 24
Finished	Feb 07 12:50:14 PM PST 24
Peak memory	215608 kb
Host	smart-bd71e601-4d4c-4a76-ba35-16b6e99d25bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3689781173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3689781173
Directory	/workspace/299.edn_genbits/latest

Test location	/workspace/coverage/default/3.edn_alert.2620718418
Short name	T231
Test name
Test status
Simulation time	23116318 ps
CPU time	1.05 seconds
Started	Feb 07 12:47:49 PM PST 24
Finished	Feb 07 12:47:51 PM PST 24
Peak memory	205896 kb
Host	smart-2fbe8fee-adbe-4c5b-b3ff-432e3ed19667
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2620718418 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2620718418
Directory	/workspace/3.edn_alert/latest

Test location	/workspace/coverage/default/3.edn_alert_test.668688942
Short name	T385
Test name
Test status
Simulation time	64381057 ps
CPU time	0.85 seconds
Started	Feb 07 12:47:58 PM PST 24
Finished	Feb 07 12:48:00 PM PST 24
Peak memory	206140 kb
Host	smart-80373158-8f3d-4327-a9d5-bd704222fc07
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668688942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.668688942
Directory	/workspace/3.edn_alert_test/latest

Test location	/workspace/coverage/default/3.edn_disable_auto_req_mode.1735709546
Short name	T923
Test name
Test status
Simulation time	39320996 ps
CPU time	1.21 seconds
Started	Feb 07 12:47:50 PM PST 24
Finished	Feb 07 12:47:52 PM PST 24
Peak memory	215164 kb
Host	smart-dd5aff26-6707-46af-b4aa-70271ce8eca6
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735709546 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di sable_auto_req_mode.1735709546
Directory	/workspace/3.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/3.edn_err.2603097275
Short name	T443
Test name
Test status
Simulation time	28005525 ps
CPU time	0.97 seconds
Started	Feb 07 12:47:49 PM PST 24
Finished	Feb 07 12:47:51 PM PST 24
Peak memory	222480 kb
Host	smart-5177b8df-57fd-4c84-9cb8-98c7873fd002
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2603097275 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2603097275
Directory	/workspace/3.edn_err/latest

Test location	/workspace/coverage/default/3.edn_genbits.2907959450
Short name	T697
Test name
Test status
Simulation time	80586844 ps
CPU time	1.28 seconds
Started	Feb 07 12:47:45 PM PST 24
Finished	Feb 07 12:47:47 PM PST 24
Peak memory	216988 kb
Host	smart-46bcf50b-8c4b-44ca-a8e7-0285e658c45f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2907959450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2907959450
Directory	/workspace/3.edn_genbits/latest

Test location	/workspace/coverage/default/3.edn_intr.732673662
Short name	T771
Test name
Test status
Simulation time	26939515 ps
CPU time	0.92 seconds
Started	Feb 07 12:47:50 PM PST 24
Finished	Feb 07 12:47:51 PM PST 24
Peak memory	215052 kb
Host	smart-b65282c5-d722-4b62-870f-7d3459923d73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=732673662 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.732673662
Directory	/workspace/3.edn_intr/latest

Test location	/workspace/coverage/default/3.edn_sec_cm.1935570444
Short name	T15
Test name
Test status
Simulation time	207706757 ps
CPU time	3.67 seconds
Started	Feb 07 12:47:47 PM PST 24
Finished	Feb 07 12:47:52 PM PST 24
Peak memory	232444 kb
Host	smart-23dc2a11-f654-4179-b67a-9542486e83ea
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935570444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1935570444
Directory	/workspace/3.edn_sec_cm/latest

Test location	/workspace/coverage/default/3.edn_smoke.3831318983
Short name	T395
Test name
Test status
Simulation time	14406006 ps
CPU time	0.94 seconds
Started	Feb 07 12:47:49 PM PST 24
Finished	Feb 07 12:47:50 PM PST 24
Peak memory	214952 kb
Host	smart-41624854-b349-464f-abd8-cc5221e3569e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3831318983 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3831318983
Directory	/workspace/3.edn_smoke/latest

Test location	/workspace/coverage/default/3.edn_stress_all.1853826878
Short name	T658
Test name
Test status
Simulation time	905989172 ps
CPU time	5.09 seconds
Started	Feb 07 12:47:49 PM PST 24
Finished	Feb 07 12:47:55 PM PST 24
Peak memory	215312 kb
Host	smart-26bff11c-f29a-4993-930f-333a089f63e2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853826878 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1853826878
Directory	/workspace/3.edn_stress_all/latest

Test location	/workspace/coverage/default/3.edn_stress_all_with_rand_reset.1017018988
Short name	T891
Test name
Test status
Simulation time	194463004454 ps
CPU time	866.97 seconds
Started	Feb 07 12:47:47 PM PST 24
Finished	Feb 07 01:02:14 PM PST 24
Peak memory	221364 kb
Host	smart-6a54f9c5-7980-40d5-b849-f749efda09cd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017018988 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1017018988
Directory	/workspace/3.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.edn_alert.3993398825
Short name	T432
Test name
Test status
Simulation time	64734715 ps
CPU time	0.92 seconds
Started	Feb 07 12:48:38 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	205844 kb
Host	smart-e8fc2006-6486-4fa2-8a9b-b22f43ca5e48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3993398825 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3993398825
Directory	/workspace/30.edn_alert/latest

Test location	/workspace/coverage/default/30.edn_alert_test.593274600
Short name	T571
Test name
Test status
Simulation time	30493336 ps
CPU time	0.95 seconds
Started	Feb 07 12:48:43 PM PST 24
Finished	Feb 07 12:48:47 PM PST 24
Peak memory	205908 kb
Host	smart-12e5d349-5f72-47ee-a072-8ed2e3a5bdc1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593274600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.593274600
Directory	/workspace/30.edn_alert_test/latest

Test location	/workspace/coverage/default/30.edn_disable.3048608812
Short name	T103
Test name
Test status
Simulation time	35425846 ps
CPU time	0.84 seconds
Started	Feb 07 12:48:44 PM PST 24
Finished	Feb 07 12:48:48 PM PST 24
Peak memory	214988 kb
Host	smart-65557579-c6cc-4530-8a6a-7e0e0012667d
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048608812 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3048608812
Directory	/workspace/30.edn_disable/latest

Test location	/workspace/coverage/default/30.edn_disable_auto_req_mode.1507895555
Short name	T616
Test name
Test status
Simulation time	107476128 ps
CPU time	0.94 seconds
Started	Feb 07 12:48:37 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	216300 kb
Host	smart-17683863-3a14-48f5-bea7-c9fbd98b86e4
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507895555 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d isable_auto_req_mode.1507895555
Directory	/workspace/30.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/30.edn_err.1990859836
Short name	T790
Test name
Test status
Simulation time	27386651 ps
CPU time	1.08 seconds
Started	Feb 07 12:48:37 PM PST 24
Finished	Feb 07 12:48:44 PM PST 24
Peak memory	215392 kb
Host	smart-5b34ad82-c281-4a01-b213-bb17d8928b53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1990859836 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1990859836
Directory	/workspace/30.edn_err/latest

Test location	/workspace/coverage/default/30.edn_genbits.1145438972
Short name	T174
Test name
Test status
Simulation time	103746869 ps
CPU time	1.19 seconds
Started	Feb 07 12:48:39 PM PST 24
Finished	Feb 07 12:48:45 PM PST 24
Peak memory	215468 kb
Host	smart-e5491b47-6e50-454b-978b-c62ba30f804d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1145438972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1145438972
Directory	/workspace/30.edn_genbits/latest

Test location	/workspace/coverage/default/30.edn_intr.3123680310
Short name	T924
Test name
Test status
Simulation time	22385789 ps
CPU time	1.07 seconds
Started	Feb 07 12:48:39 PM PST 24
Finished	Feb 07 12:48:45 PM PST 24
Peak memory	215184 kb
Host	smart-bda0f93e-80a6-469f-bdd4-fba3230a2cbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3123680310 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3123680310
Directory	/workspace/30.edn_intr/latest

Test location	/workspace/coverage/default/30.edn_smoke.555259471
Short name	T587
Test name
Test status
Simulation time	20871391 ps
CPU time	0.98 seconds
Started	Feb 07 12:48:32 PM PST 24
Finished	Feb 07 12:48:39 PM PST 24
Peak memory	215020 kb
Host	smart-98d618e3-6a92-42a2-8f62-9060bf769899
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=555259471 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.555259471
Directory	/workspace/30.edn_smoke/latest

Test location	/workspace/coverage/default/30.edn_stress_all.590094114
Short name	T343
Test name
Test status
Simulation time	67524196 ps
CPU time	1.77 seconds
Started	Feb 07 12:48:40 PM PST 24
Finished	Feb 07 12:48:46 PM PST 24
Peak memory	215008 kb
Host	smart-325e24aa-fb9a-42fa-a866-3abdfb7ca41e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590094114 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.590094114
Directory	/workspace/30.edn_stress_all/latest

Test location	/workspace/coverage/default/30.edn_stress_all_with_rand_reset.2207785289
Short name	T82
Test name
Test status
Simulation time	53944291742 ps
CPU time	1187.26 seconds
Started	Feb 07 12:48:34 PM PST 24
Finished	Feb 07 01:08:26 PM PST 24
Peak memory	218492 kb
Host	smart-e872d1ca-da5e-483c-943d-7a2c35d7c783
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207785289 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2207785289
Directory	/workspace/30.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.edn_alert.511523150
Short name	T526
Test name
Test status
Simulation time	21585420 ps
CPU time	1.03 seconds
Started	Feb 07 12:48:50 PM PST 24
Finished	Feb 07 12:48:53 PM PST 24
Peak memory	206060 kb
Host	smart-f103b422-bc7b-45fd-90e7-29e02dcef8b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=511523150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.511523150
Directory	/workspace/31.edn_alert/latest

Test location	/workspace/coverage/default/31.edn_alert_test.2435644201
Short name	T916
Test name
Test status
Simulation time	77568631 ps
CPU time	0.86 seconds
Started	Feb 07 12:48:55 PM PST 24
Finished	Feb 07 12:48:57 PM PST 24
Peak memory	206324 kb
Host	smart-24dc46be-4891-432b-afb3-755f9e17c96c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435644201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2435644201
Directory	/workspace/31.edn_alert_test/latest

Test location	/workspace/coverage/default/31.edn_disable.3689214523
Short name	T86
Test name
Test status
Simulation time	21591010 ps
CPU time	0.88 seconds
Started	Feb 07 12:48:43 PM PST 24
Finished	Feb 07 12:48:47 PM PST 24
Peak memory	215148 kb
Host	smart-0e6576fe-1604-4ba4-ad9f-02dce951bc80
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689214523 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3689214523
Directory	/workspace/31.edn_disable/latest

Test location	/workspace/coverage/default/31.edn_err.153671199
Short name	T2
Test name
Test status
Simulation time	25774274 ps
CPU time	1.06 seconds
Started	Feb 07 12:48:45 PM PST 24
Finished	Feb 07 12:48:49 PM PST 24
Peak memory	229392 kb
Host	smart-dee85d7e-2031-45c2-ac30-c0ce928c379b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=153671199 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.153671199
Directory	/workspace/31.edn_err/latest

Test location	/workspace/coverage/default/31.edn_genbits.2699542329
Short name	T464
Test name
Test status
Simulation time	24685616 ps
CPU time	1.11 seconds
Started	Feb 07 12:48:43 PM PST 24
Finished	Feb 07 12:48:48 PM PST 24
Peak memory	215472 kb
Host	smart-5a57b80e-4e38-4a9d-a8a0-81fd9c7cb34d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2699542329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2699542329
Directory	/workspace/31.edn_genbits/latest

Test location	/workspace/coverage/default/31.edn_intr.139245601
Short name	T391
Test name
Test status
Simulation time	24205271 ps
CPU time	1.17 seconds
Started	Feb 07 12:48:44 PM PST 24
Finished	Feb 07 12:48:48 PM PST 24
Peak memory	215124 kb
Host	smart-ee88746b-5229-4467-b737-0a50b3706b40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=139245601 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.139245601
Directory	/workspace/31.edn_intr/latest

Test location	/workspace/coverage/default/31.edn_smoke.624549044
Short name	T628
Test name
Test status
Simulation time	41808662 ps
CPU time	0.87 seconds
Started	Feb 07 12:48:36 PM PST 24
Finished	Feb 07 12:48:43 PM PST 24
Peak memory	215024 kb
Host	smart-239ce555-5bf8-47a9-8bdb-03e1ef067c72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=624549044 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.624549044
Directory	/workspace/31.edn_smoke/latest

Test location	/workspace/coverage/default/31.edn_stress_all.193740057
Short name	T829
Test name
Test status
Simulation time	137623846 ps
CPU time	1.06 seconds
Started	Feb 07 12:48:43 PM PST 24
Finished	Feb 07 12:48:48 PM PST 24
Peak memory	215024 kb
Host	smart-be5a6135-adc6-4f82-aa24-2705762fd863
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193740057 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.193740057
Directory	/workspace/31.edn_stress_all/latest

Test location	/workspace/coverage/default/31.edn_stress_all_with_rand_reset.4090931297
Short name	T614
Test name
Test status
Simulation time	40350993947 ps
CPU time	877.09 seconds
Started	Feb 07 12:48:44 PM PST 24
Finished	Feb 07 01:03:24 PM PST 24
Peak memory	216948 kb
Host	smart-36acbdb9-c12f-45b9-bcc9-c43dd575098f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090931297 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.4090931297
Directory	/workspace/31.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.edn_alert.4161351435
Short name	T937
Test name
Test status
Simulation time	39970949 ps
CPU time	1.03 seconds
Started	Feb 07 12:48:48 PM PST 24
Finished	Feb 07 12:48:50 PM PST 24
Peak memory	205892 kb
Host	smart-0400c818-603b-4e2c-9903-b3c1a6cbbd36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4161351435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.4161351435
Directory	/workspace/32.edn_alert/latest

Test location	/workspace/coverage/default/32.edn_alert_test.1033669610
Short name	T363
Test name
Test status
Simulation time	42174354 ps
CPU time	0.82 seconds
Started	Feb 07 12:48:46 PM PST 24
Finished	Feb 07 12:48:49 PM PST 24
Peak memory	205924 kb
Host	smart-c2223798-c8e9-48e0-a135-24e2622f0107
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033669610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1033669610
Directory	/workspace/32.edn_alert_test/latest

Test location	/workspace/coverage/default/32.edn_disable.293414588
Short name	T634
Test name
Test status
Simulation time	22128919 ps
CPU time	0.93 seconds
Started	Feb 07 12:48:39 PM PST 24
Finished	Feb 07 12:48:45 PM PST 24
Peak memory	215004 kb
Host	smart-576a8d16-1ac6-4ea5-91e9-79a52fac7325
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293414588 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.293414588
Directory	/workspace/32.edn_disable/latest

Test location	/workspace/coverage/default/32.edn_disable_auto_req_mode.3088942892
Short name	T700
Test name
Test status
Simulation time	87855074 ps
CPU time	1.41 seconds
Started	Feb 07 12:48:47 PM PST 24
Finished	Feb 07 12:48:50 PM PST 24
Peak memory	215324 kb
Host	smart-35538d98-000e-4847-a19c-aae7b5097f1f
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088942892 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d isable_auto_req_mode.3088942892
Directory	/workspace/32.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/32.edn_err.4025396786
Short name	T535
Test name
Test status
Simulation time	41691588 ps
CPU time	1.09 seconds
Started	Feb 07 12:48:56 PM PST 24
Finished	Feb 07 12:48:58 PM PST 24
Peak memory	218104 kb
Host	smart-f7db1c17-ed7b-45d3-9d8e-023324a21a0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4025396786 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.4025396786
Directory	/workspace/32.edn_err/latest

Test location	/workspace/coverage/default/32.edn_genbits.2819607081
Short name	T393
Test name
Test status
Simulation time	109693881 ps
CPU time	1.88 seconds
Started	Feb 07 12:48:46 PM PST 24
Finished	Feb 07 12:48:50 PM PST 24
Peak memory	216768 kb
Host	smart-0dedf68d-2c2c-409b-8f0e-6d7bff411cae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2819607081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2819607081
Directory	/workspace/32.edn_genbits/latest

Test location	/workspace/coverage/default/32.edn_intr.903041953
Short name	T725
Test name
Test status
Simulation time	40680923 ps
CPU time	0.83 seconds
Started	Feb 07 12:48:43 PM PST 24
Finished	Feb 07 12:48:47 PM PST 24
Peak memory	214752 kb
Host	smart-bfc1fea1-4e2e-4bd0-8c4f-90ff3ce60812
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=903041953 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.903041953
Directory	/workspace/32.edn_intr/latest

Test location	/workspace/coverage/default/32.edn_smoke.2370182841
Short name	T390
Test name
Test status
Simulation time	136431175 ps
CPU time	0.86 seconds
Started	Feb 07 12:48:45 PM PST 24
Finished	Feb 07 12:48:48 PM PST 24
Peak memory	215016 kb
Host	smart-91f683a8-fece-4405-9b85-4d4045bc2d08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2370182841 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2370182841
Directory	/workspace/32.edn_smoke/latest

Test location	/workspace/coverage/default/32.edn_stress_all.819664498
Short name	T803
Test name
Test status
Simulation time	268313346 ps
CPU time	5.28 seconds
Started	Feb 07 12:48:44 PM PST 24
Finished	Feb 07 12:48:52 PM PST 24
Peak memory	216608 kb
Host	smart-04af6f73-39e1-48b8-a868-9756c29c0987
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819664498 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.819664498
Directory	/workspace/32.edn_stress_all/latest

Test location	/workspace/coverage/default/32.edn_stress_all_with_rand_reset.2349093351
Short name	T671
Test name
Test status
Simulation time	112305074110 ps
CPU time	770.17 seconds
Started	Feb 07 12:48:45 PM PST 24
Finished	Feb 07 01:01:38 PM PST 24
Peak memory	223416 kb
Host	smart-6ae535b0-858e-48e9-a976-08a2ca03c0ab
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349093351 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2349093351
Directory	/workspace/32.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.edn_alert_test.4246675118
Short name	T579
Test name
Test status
Simulation time	78853657 ps
CPU time	0.87 seconds
Started	Feb 07 12:48:42 PM PST 24
Finished	Feb 07 12:48:46 PM PST 24
Peak memory	205440 kb
Host	smart-59663c1a-f284-48cc-83de-8f2cf5f672d6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246675118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.4246675118
Directory	/workspace/33.edn_alert_test/latest

Test location	/workspace/coverage/default/33.edn_disable.4062546610
Short name	T370
Test name
Test status
Simulation time	21019526 ps
CPU time	0.83 seconds
Started	Feb 07 12:48:45 PM PST 24
Finished	Feb 07 12:48:49 PM PST 24
Peak memory	214984 kb
Host	smart-2d816645-f3cd-4f10-bf9f-f741df6d4ac5
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062546610 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.4062546610
Directory	/workspace/33.edn_disable/latest

Test location	/workspace/coverage/default/33.edn_disable_auto_req_mode.1602331901
Short name	T586
Test name
Test status
Simulation time	262268380 ps
CPU time	1.14 seconds
Started	Feb 07 12:48:46 PM PST 24
Finished	Feb 07 12:48:50 PM PST 24
Peak memory	215188 kb
Host	smart-38138c82-38be-462b-9055-daa5a6f03435
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602331901 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d isable_auto_req_mode.1602331901
Directory	/workspace/33.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/33.edn_err.3027632768
Short name	T597
Test name
Test status
Simulation time	33180493 ps
CPU time	0.84 seconds
Started	Feb 07 12:48:47 PM PST 24
Finished	Feb 07 12:48:50 PM PST 24
Peak memory	216544 kb
Host	smart-be6eb99a-9f36-437b-b337-eb5a2611bfd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3027632768 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3027632768
Directory	/workspace/33.edn_err/latest

Test location	/workspace/coverage/default/33.edn_genbits.944569360
Short name	T766
Test name
Test status
Simulation time	36374489 ps
CPU time	1.39 seconds
Started	Feb 07 12:48:48 PM PST 24
Finished	Feb 07 12:48:51 PM PST 24
Peak memory	215656 kb
Host	smart-4976c1bb-9a99-4c08-adc3-b5e224e7e70d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=944569360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.944569360
Directory	/workspace/33.edn_genbits/latest

Test location	/workspace/coverage/default/33.edn_intr.4146418226
Short name	T59
Test name
Test status
Simulation time	34859311 ps
CPU time	0.89 seconds
Started	Feb 07 12:48:56 PM PST 24
Finished	Feb 07 12:48:58 PM PST 24
Peak memory	215020 kb
Host	smart-423ca483-60aa-4138-af19-80e18b68f54c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4146418226 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.4146418226
Directory	/workspace/33.edn_intr/latest

Test location	/workspace/coverage/default/33.edn_smoke.1143900099
Short name	T914
Test name
Test status
Simulation time	43402102 ps
CPU time	0.93 seconds
Started	Feb 07 12:48:44 PM PST 24
Finished	Feb 07 12:48:48 PM PST 24
Peak memory	215036 kb
Host	smart-f29ae182-86e3-476d-b0ce-6e24680553f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1143900099 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1143900099
Directory	/workspace/33.edn_smoke/latest

Test location	/workspace/coverage/default/33.edn_stress_all.1676938359
Short name	T960
Test name
Test status
Simulation time	237463396 ps
CPU time	4.63 seconds
Started	Feb 07 12:48:42 PM PST 24
Finished	Feb 07 12:48:50 PM PST 24
Peak memory	215236 kb
Host	smart-72d010d9-c803-4fc2-84a3-b9303d3f50d0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676938359 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1676938359
Directory	/workspace/33.edn_stress_all/latest

Test location	/workspace/coverage/default/33.edn_stress_all_with_rand_reset.1022281260
Short name	T446
Test name
Test status
Simulation time	270515814923 ps
CPU time	1584.16 seconds
Started	Feb 07 12:48:43 PM PST 24
Finished	Feb 07 01:15:11 PM PST 24
Peak memory	223128 kb
Host	smart-554969a1-4573-4ace-8712-a5e8b34de9c7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022281260 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1022281260
Directory	/workspace/33.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.edn_alert.3743561843
Short name	T94
Test name
Test status
Simulation time	64301840 ps
CPU time	0.98 seconds
Started	Feb 07 12:48:55 PM PST 24
Finished	Feb 07 12:48:58 PM PST 24
Peak memory	206240 kb
Host	smart-40efd9b0-9447-458f-bcac-e68bb289077a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3743561843 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3743561843
Directory	/workspace/34.edn_alert/latest

Test location	/workspace/coverage/default/34.edn_alert_test.2766918030
Short name	T740
Test name
Test status
Simulation time	44943812 ps
CPU time	0.8 seconds
Started	Feb 07 12:48:43 PM PST 24
Finished	Feb 07 12:48:47 PM PST 24
Peak memory	205952 kb
Host	smart-ea4a85a7-abe5-4887-9c39-586a79635d84
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766918030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2766918030
Directory	/workspace/34.edn_alert_test/latest

Test location	/workspace/coverage/default/34.edn_disable.938309921
Short name	T607
Test name
Test status
Simulation time	14176467 ps
CPU time	0.91 seconds
Started	Feb 07 12:48:47 PM PST 24
Finished	Feb 07 12:48:50 PM PST 24
Peak memory	215260 kb
Host	smart-ae74b0b8-637c-4755-94b0-67a7b6ba31ac
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938309921 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.938309921
Directory	/workspace/34.edn_disable/latest

Test location	/workspace/coverage/default/34.edn_err.452283843
Short name	T399
Test name
Test status
Simulation time	18625045 ps
CPU time	1.02 seconds
Started	Feb 07 12:48:42 PM PST 24
Finished	Feb 07 12:48:46 PM PST 24
Peak memory	216700 kb
Host	smart-3278a4dd-b41e-427d-9f51-d02a93e18532
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=452283843 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.452283843
Directory	/workspace/34.edn_err/latest

Test location	/workspace/coverage/default/34.edn_genbits.1190469748
Short name	T237
Test name
Test status
Simulation time	167012668 ps
CPU time	2.04 seconds
Started	Feb 07 12:48:45 PM PST 24
Finished	Feb 07 12:48:50 PM PST 24
Peak memory	216680 kb
Host	smart-dd1ba185-3331-47db-9e05-729d8b169e70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1190469748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1190469748
Directory	/workspace/34.edn_genbits/latest

Test location	/workspace/coverage/default/34.edn_intr.3592347231
Short name	T676
Test name
Test status
Simulation time	28825807 ps
CPU time	0.84 seconds
Started	Feb 07 12:48:49 PM PST 24
Finished	Feb 07 12:48:51 PM PST 24
Peak memory	215180 kb
Host	smart-68021465-7377-4522-a8f6-d319c3186254
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3592347231 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3592347231
Directory	/workspace/34.edn_intr/latest

Test location	/workspace/coverage/default/34.edn_smoke.241588461
Short name	T367
Test name
Test status
Simulation time	26435324 ps
CPU time	0.96 seconds
Started	Feb 07 12:48:56 PM PST 24
Finished	Feb 07 12:48:58 PM PST 24
Peak memory	214772 kb
Host	smart-0410fa62-7888-48b0-827b-717a770be1ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=241588461 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.241588461
Directory	/workspace/34.edn_smoke/latest

Test location	/workspace/coverage/default/34.edn_stress_all.1662837126
Short name	T681
Test name
Test status
Simulation time	461503360 ps
CPU time	2.66 seconds
Started	Feb 07 12:48:43 PM PST 24
Finished	Feb 07 12:48:49 PM PST 24
Peak memory	216588 kb
Host	smart-f605edc6-9e4d-4890-937e-94d3d4241d1e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662837126 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1662837126
Directory	/workspace/34.edn_stress_all/latest

Test location	/workspace/coverage/default/34.edn_stress_all_with_rand_reset.4255534992
Short name	T643
Test name
Test status
Simulation time	201596142522 ps
CPU time	1071.63 seconds
Started	Feb 07 12:48:40 PM PST 24
Finished	Feb 07 01:06:36 PM PST 24
Peak memory	219176 kb
Host	smart-f11db7dc-4325-4fed-a13b-12b5ce5e29c4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255534992 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.4255534992
Directory	/workspace/34.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.edn_alert.782385120
Short name	T226
Test name
Test status
Simulation time	31206115 ps
CPU time	0.99 seconds
Started	Feb 07 12:48:44 PM PST 24
Finished	Feb 07 12:48:48 PM PST 24
Peak memory	205928 kb
Host	smart-8cba5b41-620b-49b1-a4f9-78328a2797e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=782385120 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.782385120
Directory	/workspace/35.edn_alert/latest

Test location	/workspace/coverage/default/35.edn_alert_test.81875514
Short name	T584
Test name
Test status
Simulation time	20390061 ps
CPU time	1.03 seconds
Started	Feb 07 12:48:44 PM PST 24
Finished	Feb 07 12:48:48 PM PST 24
Peak memory	205516 kb
Host	smart-031e57e3-1c13-4d88-a5fc-dfc288ad99ec
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81875514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.81875514
Directory	/workspace/35.edn_alert_test/latest

Test location	/workspace/coverage/default/35.edn_disable.2215084937
Short name	T110
Test name
Test status
Simulation time	45326641 ps
CPU time	0.81 seconds
Started	Feb 07 12:48:47 PM PST 24
Finished	Feb 07 12:48:50 PM PST 24
Peak memory	215100 kb
Host	smart-1ae36cbd-fc14-4e84-9f53-4f551555dde2
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215084937 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2215084937
Directory	/workspace/35.edn_disable/latest

Test location	/workspace/coverage/default/35.edn_err.1418633107
Short name	T799
Test name
Test status
Simulation time	31676888 ps
CPU time	1.08 seconds
Started	Feb 07 12:48:44 PM PST 24
Finished	Feb 07 12:48:48 PM PST 24
Peak memory	215520 kb
Host	smart-7d1881ca-e968-422d-836e-3278465d12ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1418633107 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1418633107
Directory	/workspace/35.edn_err/latest

Test location	/workspace/coverage/default/35.edn_genbits.405643194
Short name	T179
Test name
Test status
Simulation time	163606403 ps
CPU time	1.01 seconds
Started	Feb 07 12:48:49 PM PST 24
Finished	Feb 07 12:48:51 PM PST 24
Peak memory	215332 kb
Host	smart-f9854766-49ae-4074-bf4e-cd24d4ca0c2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=405643194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.405643194
Directory	/workspace/35.edn_genbits/latest

Test location	/workspace/coverage/default/35.edn_intr.3837854335
Short name	T362
Test name
Test status
Simulation time	25967965 ps
CPU time	1.11 seconds
Started	Feb 07 12:48:41 PM PST 24
Finished	Feb 07 12:48:46 PM PST 24
Peak memory	222560 kb
Host	smart-7176918b-b8ce-4eff-8a03-a12e7f9806c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3837854335 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3837854335
Directory	/workspace/35.edn_intr/latest

Test location	/workspace/coverage/default/35.edn_smoke.3290729712
Short name	T105
Test name
Test status
Simulation time	14515725 ps
CPU time	0.96 seconds
Started	Feb 07 12:48:49 PM PST 24
Finished	Feb 07 12:48:51 PM PST 24
Peak memory	215020 kb
Host	smart-3998d0ef-f143-4617-a10d-1bf6d068d7a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3290729712 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3290729712
Directory	/workspace/35.edn_smoke/latest

Test location	/workspace/coverage/default/35.edn_stress_all.3376647147
Short name	T816
Test name
Test status
Simulation time	128338061 ps
CPU time	1.9 seconds
Started	Feb 07 12:48:40 PM PST 24
Finished	Feb 07 12:48:46 PM PST 24
Peak memory	218128 kb
Host	smart-4a933cca-7270-4582-a99e-398f8330320b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376647147 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.3376647147
Directory	/workspace/35.edn_stress_all/latest

Test location	/workspace/coverage/default/35.edn_stress_all_with_rand_reset.162928385
Short name	T471
Test name
Test status
Simulation time	138410024874 ps
CPU time	1743.98 seconds
Started	Feb 07 12:48:40 PM PST 24
Finished	Feb 07 01:17:49 PM PST 24
Peak memory	226308 kb
Host	smart-db485179-596c-4658-860f-715de3ce9be5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162928385 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.162928385
Directory	/workspace/35.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.edn_alert.2070963610
Short name	T95
Test name
Test status
Simulation time	22724250 ps
CPU time	1.1 seconds
Started	Feb 07 12:48:46 PM PST 24
Finished	Feb 07 12:48:50 PM PST 24
Peak memory	205824 kb
Host	smart-f522c6cb-fade-4863-b8a7-559d0b1e7107
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2070963610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2070963610
Directory	/workspace/36.edn_alert/latest

Test location	/workspace/coverage/default/36.edn_alert_test.1567777844
Short name	T648
Test name
Test status
Simulation time	97721524 ps
CPU time	0.85 seconds
Started	Feb 07 12:48:50 PM PST 24
Finished	Feb 07 12:48:53 PM PST 24
Peak memory	205420 kb
Host	smart-ec037b74-6916-468c-9587-da499fb4be6b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567777844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1567777844
Directory	/workspace/36.edn_alert_test/latest

Test location	/workspace/coverage/default/36.edn_disable.1733428940
Short name	T785
Test name
Test status
Simulation time	27609478 ps
CPU time	0.81 seconds
Started	Feb 07 12:48:52 PM PST 24
Finished	Feb 07 12:48:54 PM PST 24
Peak memory	215076 kb
Host	smart-de831106-a028-4f51-89cc-0b5330659659
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733428940 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1733428940
Directory	/workspace/36.edn_disable/latest

Test location	/workspace/coverage/default/36.edn_disable_auto_req_mode.2868671409
Short name	T890
Test name
Test status
Simulation time	75208186 ps
CPU time	1.13 seconds
Started	Feb 07 12:48:49 PM PST 24
Finished	Feb 07 12:48:52 PM PST 24
Peak memory	216660 kb
Host	smart-3c9d53b4-cc4d-4f17-a07a-97b7816c5305
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868671409 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d isable_auto_req_mode.2868671409
Directory	/workspace/36.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/36.edn_err.2902867832
Short name	T422
Test name
Test status
Simulation time	92301360 ps
CPU time	1.02 seconds
Started	Feb 07 12:48:49 PM PST 24
Finished	Feb 07 12:48:53 PM PST 24
Peak memory	215672 kb
Host	smart-860a1708-0bfe-40e0-b962-d0f290cf294b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2902867832 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2902867832
Directory	/workspace/36.edn_err/latest

Test location	/workspace/coverage/default/36.edn_intr.2322314708
Short name	T837
Test name
Test status
Simulation time	30116490 ps
CPU time	0.89 seconds
Started	Feb 07 12:48:48 PM PST 24
Finished	Feb 07 12:48:50 PM PST 24
Peak memory	215132 kb
Host	smart-2d495b11-01f4-428c-8269-98972613dc55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2322314708 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2322314708
Directory	/workspace/36.edn_intr/latest

Test location	/workspace/coverage/default/36.edn_smoke.4160730629
Short name	T87
Test name
Test status
Simulation time	19451647 ps
CPU time	0.99 seconds
Started	Feb 07 12:48:52 PM PST 24
Finished	Feb 07 12:48:54 PM PST 24
Peak memory	206744 kb
Host	smart-d8a8e04e-3991-4c89-9608-85ad40f537b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4160730629 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.4160730629
Directory	/workspace/36.edn_smoke/latest

Test location	/workspace/coverage/default/36.edn_stress_all.1938356263
Short name	T400
Test name
Test status
Simulation time	2256755028 ps
CPU time	4.18 seconds
Started	Feb 07 12:48:43 PM PST 24
Finished	Feb 07 12:48:50 PM PST 24
Peak memory	215120 kb
Host	smart-7593ee61-7f6f-4764-918f-e77b222de90e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938356263 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1938356263
Directory	/workspace/36.edn_stress_all/latest

Test location	/workspace/coverage/default/36.edn_stress_all_with_rand_reset.2029010436
Short name	T918
Test name
Test status
Simulation time	74990153018 ps
CPU time	1122.1 seconds
Started	Feb 07 12:48:46 PM PST 24
Finished	Feb 07 01:07:31 PM PST 24
Peak memory	221696 kb
Host	smart-c70e54ea-d529-4a24-9de5-9737865676cd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029010436 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2029010436
Directory	/workspace/36.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.edn_alert.2735952451
Short name	T764
Test name
Test status
Simulation time	47976614 ps
CPU time	1.02 seconds
Started	Feb 07 12:48:52 PM PST 24
Finished	Feb 07 12:48:54 PM PST 24
Peak memory	206064 kb
Host	smart-d43abc38-ccd3-40fe-9a10-84ab7f954377
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2735952451 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2735952451
Directory	/workspace/37.edn_alert/latest

Test location	/workspace/coverage/default/37.edn_alert_test.1065524949
Short name	T897
Test name
Test status
Simulation time	53082450 ps
CPU time	0.87 seconds
Started	Feb 07 12:48:51 PM PST 24
Finished	Feb 07 12:48:53 PM PST 24
Peak memory	206280 kb
Host	smart-839a078e-9873-4e05-a0f9-f0d6290dc00a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065524949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1065524949
Directory	/workspace/37.edn_alert_test/latest

Test location	/workspace/coverage/default/37.edn_disable.2041685259
Short name	T122
Test name
Test status
Simulation time	27355887 ps
CPU time	0.84 seconds
Started	Feb 07 12:48:52 PM PST 24
Finished	Feb 07 12:48:55 PM PST 24
Peak memory	214984 kb
Host	smart-afc16458-c27a-488b-ba41-4cebffc7ce3f
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041685259 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2041685259
Directory	/workspace/37.edn_disable/latest

Test location	/workspace/coverage/default/37.edn_disable_auto_req_mode.4232283406
Short name	T692
Test name
Test status
Simulation time	93057887 ps
CPU time	1.1 seconds
Started	Feb 07 12:48:49 PM PST 24
Finished	Feb 07 12:48:51 PM PST 24
Peak memory	216532 kb
Host	smart-5687e501-b231-4753-9f15-d21b6e450591
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232283406 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d isable_auto_req_mode.4232283406
Directory	/workspace/37.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/37.edn_err.1390768837
Short name	T547
Test name
Test status
Simulation time	30536648 ps
CPU time	0.96 seconds
Started	Feb 07 12:48:52 PM PST 24
Finished	Feb 07 12:48:54 PM PST 24
Peak memory	222504 kb
Host	smart-fb81786f-6eaf-4632-94e8-7749a00343f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1390768837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1390768837
Directory	/workspace/37.edn_err/latest

Test location	/workspace/coverage/default/37.edn_genbits.1725514275
Short name	T214
Test name
Test status
Simulation time	40817408 ps
CPU time	1.62 seconds
Started	Feb 07 12:48:56 PM PST 24
Finished	Feb 07 12:49:00 PM PST 24
Peak memory	218096 kb
Host	smart-3a3088b5-9f0c-472b-8265-e51709d72644
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1725514275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1725514275
Directory	/workspace/37.edn_genbits/latest

Test location	/workspace/coverage/default/37.edn_intr.542499325
Short name	T51
Test name
Test status
Simulation time	27255967 ps
CPU time	1.04 seconds
Started	Feb 07 12:48:51 PM PST 24
Finished	Feb 07 12:48:54 PM PST 24
Peak memory	222652 kb
Host	smart-85a37fc3-37a1-45e4-85db-e4558e93de8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=542499325 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.542499325
Directory	/workspace/37.edn_intr/latest

Test location	/workspace/coverage/default/37.edn_smoke.2107476756
Short name	T711
Test name
Test status
Simulation time	53570547 ps
CPU time	0.93 seconds
Started	Feb 07 12:48:47 PM PST 24
Finished	Feb 07 12:48:50 PM PST 24
Peak memory	214996 kb
Host	smart-b1afc382-860b-4987-803d-c78f809c0144
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2107476756 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2107476756
Directory	/workspace/37.edn_smoke/latest

Test location	/workspace/coverage/default/37.edn_stress_all.3532801343
Short name	T493
Test name
Test status
Simulation time	259023067 ps
CPU time	1.39 seconds
Started	Feb 07 12:48:48 PM PST 24
Finished	Feb 07 12:48:51 PM PST 24
Peak memory	215028 kb
Host	smart-6b1f8d0a-d007-4850-bb74-7f7703f36d18
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532801343 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3532801343
Directory	/workspace/37.edn_stress_all/latest

Test location	/workspace/coverage/default/37.edn_stress_all_with_rand_reset.4190525434
Short name	T841
Test name
Test status
Simulation time	43613734786 ps
CPU time	1139.21 seconds
Started	Feb 07 12:48:49 PM PST 24
Finished	Feb 07 01:07:50 PM PST 24
Peak memory	220176 kb
Host	smart-b1a003ed-5300-4a2b-93d6-0673d7a1c4d3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190525434 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.4190525434
Directory	/workspace/37.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.edn_alert.855792084
Short name	T894
Test name
Test status
Simulation time	35007243 ps
CPU time	1.01 seconds
Started	Feb 07 12:49:03 PM PST 24
Finished	Feb 07 12:49:05 PM PST 24
Peak memory	206152 kb
Host	smart-eb8f1dbe-d800-43f5-ad59-e07cfc1a7a59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=855792084 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.855792084
Directory	/workspace/38.edn_alert/latest

Test location	/workspace/coverage/default/38.edn_alert_test.2256367154
Short name	T509
Test name
Test status
Simulation time	103661707 ps
CPU time	0.79 seconds
Started	Feb 07 12:48:57 PM PST 24
Finished	Feb 07 12:48:59 PM PST 24
Peak memory	205756 kb
Host	smart-bb4498a9-777c-46de-9c5f-7acb9293277a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256367154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2256367154
Directory	/workspace/38.edn_alert_test/latest

Test location	/workspace/coverage/default/38.edn_disable_auto_req_mode.2568288390
Short name	T346
Test name
Test status
Simulation time	64281333 ps
CPU time	1.14 seconds
Started	Feb 07 12:48:53 PM PST 24
Finished	Feb 07 12:48:55 PM PST 24
Peak memory	215252 kb
Host	smart-f37bab42-af74-448d-9964-931adb77ec84
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568288390 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d isable_auto_req_mode.2568288390
Directory	/workspace/38.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/38.edn_err.2281978585
Short name	T919
Test name
Test status
Simulation time	19664398 ps
CPU time	1 seconds
Started	Feb 07 12:48:53 PM PST 24
Finished	Feb 07 12:48:55 PM PST 24
Peak memory	216524 kb
Host	smart-9ce050d8-20d2-4ff2-b7b7-e512dcc4e0aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2281978585 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2281978585
Directory	/workspace/38.edn_err/latest

Test location	/workspace/coverage/default/38.edn_genbits.1027524648
Short name	T441
Test name
Test status
Simulation time	70069542 ps
CPU time	1.56 seconds
Started	Feb 07 12:48:53 PM PST 24
Finished	Feb 07 12:48:56 PM PST 24
Peak memory	216804 kb
Host	smart-340e8705-7694-4180-8d01-66a50227d75e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1027524648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1027524648
Directory	/workspace/38.edn_genbits/latest

Test location	/workspace/coverage/default/38.edn_intr.4093019855
Short name	T699
Test name
Test status
Simulation time	20589535 ps
CPU time	1.08 seconds
Started	Feb 07 12:48:52 PM PST 24
Finished	Feb 07 12:48:54 PM PST 24
Peak memory	215344 kb
Host	smart-66ee4a1b-1adb-4541-acd4-9d2b20309d96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4093019855 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.4093019855
Directory	/workspace/38.edn_intr/latest

Test location	/workspace/coverage/default/38.edn_smoke.2431986672
Short name	T593
Test name
Test status
Simulation time	46755908 ps
CPU time	0.85 seconds
Started	Feb 07 12:48:50 PM PST 24
Finished	Feb 07 12:48:53 PM PST 24
Peak memory	214972 kb
Host	smart-57cccc2b-418f-49d4-a45e-47b019821e2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2431986672 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.2431986672
Directory	/workspace/38.edn_smoke/latest

Test location	/workspace/coverage/default/38.edn_stress_all.4000722467
Short name	T651
Test name
Test status
Simulation time	172190310 ps
CPU time	3.47 seconds
Started	Feb 07 12:48:50 PM PST 24
Finished	Feb 07 12:48:55 PM PST 24
Peak memory	216640 kb
Host	smart-3d4d4b98-bb89-47ae-a19f-1c23a33547e8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000722467 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.4000722467
Directory	/workspace/38.edn_stress_all/latest

Test location	/workspace/coverage/default/38.edn_stress_all_with_rand_reset.2157331142
Short name	T428
Test name
Test status
Simulation time	19154631995 ps
CPU time	245.62 seconds
Started	Feb 07 12:49:01 PM PST 24
Finished	Feb 07 12:53:08 PM PST 24
Peak memory	216276 kb
Host	smart-10d296da-7311-4f4b-ba9d-e91157c282f2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157331142 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2157331142
Directory	/workspace/38.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.edn_alert.2650045444
Short name	T825
Test name
Test status
Simulation time	75339314 ps
CPU time	0.94 seconds
Started	Feb 07 12:48:57 PM PST 24
Finished	Feb 07 12:48:59 PM PST 24
Peak memory	205848 kb
Host	smart-b6e08859-9e71-4d51-94c0-03dedc3589c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2650045444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2650045444
Directory	/workspace/39.edn_alert/latest

Test location	/workspace/coverage/default/39.edn_alert_test.895523129
Short name	T507
Test name
Test status
Simulation time	17618343 ps
CPU time	0.97 seconds
Started	Feb 07 12:49:04 PM PST 24
Finished	Feb 07 12:49:06 PM PST 24
Peak memory	205408 kb
Host	smart-3c57d443-b777-431c-8e55-059d7d496cd5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895523129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.895523129
Directory	/workspace/39.edn_alert_test/latest

Test location	/workspace/coverage/default/39.edn_disable.3338220396
Short name	T109
Test name
Test status
Simulation time	10885006 ps
CPU time	0.85 seconds
Started	Feb 07 12:48:54 PM PST 24
Finished	Feb 07 12:48:55 PM PST 24
Peak memory	215072 kb
Host	smart-71f332e7-ff9d-437f-8646-c25163f0d805
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338220396 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3338220396
Directory	/workspace/39.edn_disable/latest

Test location	/workspace/coverage/default/39.edn_err.3857085613
Short name	T732
Test name
Test status
Simulation time	18413784 ps
CPU time	1.1 seconds
Started	Feb 07 12:48:55 PM PST 24
Finished	Feb 07 12:48:58 PM PST 24
Peak memory	222600 kb
Host	smart-965de0a9-55c3-4d58-bcfe-60128060065e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3857085613 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3857085613
Directory	/workspace/39.edn_err/latest

Test location	/workspace/coverage/default/39.edn_genbits.784000881
Short name	T513
Test name
Test status
Simulation time	48254106 ps
CPU time	1.48 seconds
Started	Feb 07 12:48:54 PM PST 24
Finished	Feb 07 12:48:57 PM PST 24
Peak memory	216320 kb
Host	smart-c889b309-9896-4ce4-aeab-1a9269383d76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=784000881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.784000881
Directory	/workspace/39.edn_genbits/latest

Test location	/workspace/coverage/default/39.edn_intr.1561721397
Short name	T580
Test name
Test status
Simulation time	25899126 ps
CPU time	0.92 seconds
Started	Feb 07 12:48:53 PM PST 24
Finished	Feb 07 12:48:55 PM PST 24
Peak memory	215204 kb
Host	smart-0a05693b-34c9-47ec-bc0c-3d816aab20ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1561721397 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1561721397
Directory	/workspace/39.edn_intr/latest

Test location	/workspace/coverage/default/39.edn_smoke.1324124356
Short name	T555
Test name
Test status
Simulation time	148759257 ps
CPU time	0.83 seconds
Started	Feb 07 12:48:55 PM PST 24
Finished	Feb 07 12:48:58 PM PST 24
Peak memory	214932 kb
Host	smart-06bfbf26-2732-435b-bde8-f5eb786d41f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1324124356 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1324124356
Directory	/workspace/39.edn_smoke/latest

Test location	/workspace/coverage/default/39.edn_stress_all.3942346580
Short name	T209
Test name
Test status
Simulation time	220832634 ps
CPU time	4.52 seconds
Started	Feb 07 12:48:54 PM PST 24
Finished	Feb 07 12:48:59 PM PST 24
Peak memory	216684 kb
Host	smart-24d3fee9-8c10-4b33-a967-c7663e7987a9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942346580 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3942346580
Directory	/workspace/39.edn_stress_all/latest

Test location	/workspace/coverage/default/39.edn_stress_all_with_rand_reset.3750763464
Short name	T871
Test name
Test status
Simulation time	85032869890 ps
CPU time	477.4 seconds
Started	Feb 07 12:48:54 PM PST 24
Finished	Feb 07 12:56:52 PM PST 24
Peak memory	216972 kb
Host	smart-a30d9ce9-a0b5-4012-9b31-22c8e07710a3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750763464 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3750763464
Directory	/workspace/39.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.edn_alert.3247253514
Short name	T788
Test name
Test status
Simulation time	21476865 ps
CPU time	1.05 seconds
Started	Feb 07 12:47:58 PM PST 24
Finished	Feb 07 12:48:00 PM PST 24
Peak memory	206092 kb
Host	smart-b8f4f8d3-e4f0-431e-b029-edd681faf06c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3247253514 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3247253514
Directory	/workspace/4.edn_alert/latest

Test location	/workspace/coverage/default/4.edn_alert_test.3689397220
Short name	T849
Test name
Test status
Simulation time	20087070 ps
CPU time	0.97 seconds
Started	Feb 07 12:47:56 PM PST 24
Finished	Feb 07 12:47:58 PM PST 24
Peak memory	205452 kb
Host	smart-316845e3-2542-47c4-bdc9-00d16be71e98
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689397220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3689397220
Directory	/workspace/4.edn_alert_test/latest

Test location	/workspace/coverage/default/4.edn_disable.3882718400
Short name	T874
Test name
Test status
Simulation time	73746683 ps
CPU time	0.82 seconds
Started	Feb 07 12:47:53 PM PST 24
Finished	Feb 07 12:47:54 PM PST 24
Peak memory	215136 kb
Host	smart-7310f708-213a-4081-813a-c2dae6e19699
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882718400 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3882718400
Directory	/workspace/4.edn_disable/latest

Test location	/workspace/coverage/default/4.edn_disable_auto_req_mode.3652260000
Short name	T423
Test name
Test status
Simulation time	156192993 ps
CPU time	1.06 seconds
Started	Feb 07 12:47:58 PM PST 24
Finished	Feb 07 12:48:00 PM PST 24
Peak memory	215408 kb
Host	smart-f3f19c1d-5d1d-489c-981e-821f841b40ff
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652260000 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di sable_auto_req_mode.3652260000
Directory	/workspace/4.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/4.edn_err.3341135339
Short name	T369
Test name
Test status
Simulation time	30177979 ps
CPU time	0.91 seconds
Started	Feb 07 12:47:58 PM PST 24
Finished	Feb 07 12:48:00 PM PST 24
Peak memory	216912 kb
Host	smart-2546ca3d-9ceb-4fd1-a947-2379881c0a26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3341135339 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3341135339
Directory	/workspace/4.edn_err/latest

Test location	/workspace/coverage/default/4.edn_genbits.3290474813
Short name	T655
Test name
Test status
Simulation time	66082328 ps
CPU time	1.07 seconds
Started	Feb 07 12:47:58 PM PST 24
Finished	Feb 07 12:48:00 PM PST 24
Peak memory	215084 kb
Host	smart-f1f407d0-4ba6-4e0d-b957-f280870387c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3290474813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3290474813
Directory	/workspace/4.edn_genbits/latest

Test location	/workspace/coverage/default/4.edn_intr.2019361858
Short name	T52
Test name
Test status
Simulation time	22239219 ps
CPU time	1.18 seconds
Started	Feb 07 12:48:00 PM PST 24
Finished	Feb 07 12:48:02 PM PST 24
Peak memory	222700 kb
Host	smart-cf2498bc-f63e-4cef-ae31-30fcd38e6ed2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2019361858 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2019361858
Directory	/workspace/4.edn_intr/latest

Test location	/workspace/coverage/default/4.edn_regwen.2693032292
Short name	T223
Test name
Test status
Simulation time	43341478 ps
CPU time	0.86 seconds
Started	Feb 07 12:47:59 PM PST 24
Finished	Feb 07 12:48:01 PM PST 24
Peak memory	206740 kb
Host	smart-b97e5356-8d36-4fe9-a00c-343be9f51a6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2693032292 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2693032292
Directory	/workspace/4.edn_regwen/latest

Test location	/workspace/coverage/default/4.edn_sec_cm.3422261302
Short name	T54
Test name
Test status
Simulation time	374627244 ps
CPU time	5.89 seconds
Started	Feb 07 12:47:56 PM PST 24
Finished	Feb 07 12:48:03 PM PST 24
Peak memory	233084 kb
Host	smart-6bcb6fd7-79f4-4999-b21b-4f2cbbbcb75e
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422261302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3422261302
Directory	/workspace/4.edn_sec_cm/latest

Test location	/workspace/coverage/default/4.edn_smoke.3799168226
Short name	T364
Test name
Test status
Simulation time	18609953 ps
CPU time	1.05 seconds
Started	Feb 07 12:47:57 PM PST 24
Finished	Feb 07 12:47:59 PM PST 24
Peak memory	215032 kb
Host	smart-4eb841a9-7a88-4539-b5e7-e76b2639275e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3799168226 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3799168226
Directory	/workspace/4.edn_smoke/latest

Test location	/workspace/coverage/default/4.edn_stress_all.3999355032
Short name	T812
Test name
Test status
Simulation time	160234150 ps
CPU time	1.97 seconds
Started	Feb 07 12:47:55 PM PST 24
Finished	Feb 07 12:47:57 PM PST 24
Peak memory	206828 kb
Host	smart-b24a3b98-2e09-45a4-93e6-efee67936281
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999355032 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3999355032
Directory	/workspace/4.edn_stress_all/latest

Test location	/workspace/coverage/default/4.edn_stress_all_with_rand_reset.3542000626
Short name	T541
Test name
Test status
Simulation time	93435307048 ps
CPU time	378.54 seconds
Started	Feb 07 12:47:58 PM PST 24
Finished	Feb 07 12:54:17 PM PST 24
Peak memory	216968 kb
Host	smart-d14d1d17-5e3a-4c3e-be32-6e82dabef10c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542000626 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3542000626
Directory	/workspace/4.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.edn_alert.3296761851
Short name	T518
Test name
Test status
Simulation time	40281267 ps
CPU time	1.06 seconds
Started	Feb 07 12:49:00 PM PST 24
Finished	Feb 07 12:49:03 PM PST 24
Peak memory	206004 kb
Host	smart-e33b2534-ec5b-4002-8c5f-e82c4ea1a399
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3296761851 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3296761851
Directory	/workspace/40.edn_alert/latest

Test location	/workspace/coverage/default/40.edn_alert_test.1986961808
Short name	T939
Test name
Test status
Simulation time	15631514 ps
CPU time	0.94 seconds
Started	Feb 07 12:48:59 PM PST 24
Finished	Feb 07 12:49:02 PM PST 24
Peak memory	205420 kb
Host	smart-37c05154-53fd-4aec-808e-4e4132bb9dc7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986961808 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1986961808
Directory	/workspace/40.edn_alert_test/latest

Test location	/workspace/coverage/default/40.edn_disable.4043161744
Short name	T682
Test name
Test status
Simulation time	18762919 ps
CPU time	0.8 seconds
Started	Feb 07 12:49:14 PM PST 24
Finished	Feb 07 12:49:19 PM PST 24
Peak memory	214820 kb
Host	smart-9faf3018-1f50-413a-a32f-b2a52dac4baa
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043161744 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.4043161744
Directory	/workspace/40.edn_disable/latest

Test location	/workspace/coverage/default/40.edn_disable_auto_req_mode.3025505497
Short name	T961
Test name
Test status
Simulation time	88486337 ps
CPU time	1.18 seconds
Started	Feb 07 12:49:10 PM PST 24
Finished	Feb 07 12:49:16 PM PST 24
Peak memory	215328 kb
Host	smart-bae28811-c011-4aab-8d7d-0ad405ca93bc
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025505497 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d isable_auto_req_mode.3025505497
Directory	/workspace/40.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/40.edn_genbits.2012258216
Short name	T963
Test name
Test status
Simulation time	77803194 ps
CPU time	2.4 seconds
Started	Feb 07 12:48:56 PM PST 24
Finished	Feb 07 12:49:00 PM PST 24
Peak memory	216792 kb
Host	smart-602a1e81-c62b-4f4f-b28e-be40de22a465
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2012258216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2012258216
Directory	/workspace/40.edn_genbits/latest

Test location	/workspace/coverage/default/40.edn_intr.3481696511
Short name	T359
Test name
Test status
Simulation time	30258142 ps
CPU time	0.87 seconds
Started	Feb 07 12:49:14 PM PST 24
Finished	Feb 07 12:49:19 PM PST 24
Peak memory	215068 kb
Host	smart-061ac000-faf6-4a7a-8aa0-1e6e37a4db06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3481696511 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3481696511
Directory	/workspace/40.edn_intr/latest

Test location	/workspace/coverage/default/40.edn_smoke.1361735396
Short name	T85
Test name
Test status
Simulation time	62850861 ps
CPU time	0.87 seconds
Started	Feb 07 12:49:10 PM PST 24
Finished	Feb 07 12:49:15 PM PST 24
Peak memory	215056 kb
Host	smart-9abea1be-45b5-4fbe-a630-3541897b39e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1361735396 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1361735396
Directory	/workspace/40.edn_smoke/latest

Test location	/workspace/coverage/default/40.edn_stress_all.1832468515
Short name	T690
Test name
Test status
Simulation time	172654199 ps
CPU time	3.85 seconds
Started	Feb 07 12:48:59 PM PST 24
Finished	Feb 07 12:49:05 PM PST 24
Peak memory	216632 kb
Host	smart-f9fb66a1-9895-4251-95cb-ecfaed890808
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832468515 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1832468515
Directory	/workspace/40.edn_stress_all/latest

Test location	/workspace/coverage/default/40.edn_stress_all_with_rand_reset.1001175205
Short name	T484
Test name
Test status
Simulation time	92302075028 ps
CPU time	2061.22 seconds
Started	Feb 07 12:49:06 PM PST 24
Finished	Feb 07 01:23:29 PM PST 24
Peak memory	225448 kb
Host	smart-9ed7ce22-d43b-4371-975b-990fdcb2aa4b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001175205 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1001175205
Directory	/workspace/40.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.edn_alert.1998024910
Short name	T90
Test name
Test status
Simulation time	246835260 ps
CPU time	1.11 seconds
Started	Feb 07 12:49:06 PM PST 24
Finished	Feb 07 12:49:08 PM PST 24
Peak memory	205752 kb
Host	smart-9c37f556-e189-4cfa-acf4-50974dbedca3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1998024910 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1998024910
Directory	/workspace/41.edn_alert/latest

Test location	/workspace/coverage/default/41.edn_alert_test.196165079
Short name	T368
Test name
Test status
Simulation time	52901219 ps
CPU time	0.91 seconds
Started	Feb 07 12:48:59 PM PST 24
Finished	Feb 07 12:49:01 PM PST 24
Peak memory	205360 kb
Host	smart-33ef62ac-35f5-4645-8c73-87c68f964ade
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196165079 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.196165079
Directory	/workspace/41.edn_alert_test/latest

Test location	/workspace/coverage/default/41.edn_disable.3051867974
Short name	T115
Test name
Test status
Simulation time	52865118 ps
CPU time	0.79 seconds
Started	Feb 07 12:49:04 PM PST 24
Finished	Feb 07 12:49:06 PM PST 24
Peak memory	214992 kb
Host	smart-a07ef1d0-747a-4f24-b53a-bad813d504f7
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051867974 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3051867974
Directory	/workspace/41.edn_disable/latest

Test location	/workspace/coverage/default/41.edn_err.2641441584
Short name	T728
Test name
Test status
Simulation time	31266959 ps
CPU time	0.91 seconds
Started	Feb 07 12:49:15 PM PST 24
Finished	Feb 07 12:49:20 PM PST 24
Peak memory	221836 kb
Host	smart-7abce9f7-01db-482b-9562-d3b0ae2f130a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2641441584 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2641441584
Directory	/workspace/41.edn_err/latest

Test location	/workspace/coverage/default/41.edn_genbits.2965556290
Short name	T563
Test name
Test status
Simulation time	70033055 ps
CPU time	1.04 seconds
Started	Feb 07 12:49:08 PM PST 24
Finished	Feb 07 12:49:14 PM PST 24
Peak memory	215052 kb
Host	smart-d6eef784-0e55-4566-be2f-f87f22ab624e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2965556290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2965556290
Directory	/workspace/41.edn_genbits/latest

Test location	/workspace/coverage/default/41.edn_intr.2948787
Short name	T58
Test name
Test status
Simulation time	106495389 ps
CPU time	0.83 seconds
Started	Feb 07 12:49:08 PM PST 24
Finished	Feb 07 12:49:14 PM PST 24
Peak memory	214912 kb
Host	smart-efade80e-e657-4add-8da5-cbcf2d01231c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2948787 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2948787
Directory	/workspace/41.edn_intr/latest

Test location	/workspace/coverage/default/41.edn_smoke.2693880988
Short name	T745
Test name
Test status
Simulation time	18186761 ps
CPU time	1.02 seconds
Started	Feb 07 12:49:09 PM PST 24
Finished	Feb 07 12:49:15 PM PST 24
Peak memory	206800 kb
Host	smart-d20821e8-f8c6-4a1d-8964-fd224724762f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2693880988 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2693880988
Directory	/workspace/41.edn_smoke/latest

Test location	/workspace/coverage/default/41.edn_stress_all.2426558841
Short name	T879
Test name
Test status
Simulation time	515317321 ps
CPU time	5.3 seconds
Started	Feb 07 12:49:07 PM PST 24
Finished	Feb 07 12:49:14 PM PST 24
Peak memory	215360 kb
Host	smart-f0f83603-0dc8-482e-bfa7-e9321c00e265
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426558841 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2426558841
Directory	/workspace/41.edn_stress_all/latest

Test location	/workspace/coverage/default/41.edn_stress_all_with_rand_reset.299845367
Short name	T748
Test name
Test status
Simulation time	85661108103 ps
CPU time	299.33 seconds
Started	Feb 07 12:49:09 PM PST 24
Finished	Feb 07 12:54:14 PM PST 24
Peak memory	216868 kb
Host	smart-f43861d3-5567-4921-a7fd-6289f1a21f8b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299845367 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.299845367
Directory	/workspace/41.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.edn_alert.736357649
Short name	T883
Test name
Test status
Simulation time	39277048 ps
CPU time	1.06 seconds
Started	Feb 07 12:49:06 PM PST 24
Finished	Feb 07 12:49:09 PM PST 24
Peak memory	206080 kb
Host	smart-135a7390-208a-4caa-831b-f514cb270cf5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=736357649 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.736357649
Directory	/workspace/42.edn_alert/latest

Test location	/workspace/coverage/default/42.edn_alert_test.1334744106
Short name	T510
Test name
Test status
Simulation time	38695255 ps
CPU time	0.79 seconds
Started	Feb 07 12:49:12 PM PST 24
Finished	Feb 07 12:49:15 PM PST 24
Peak memory	205212 kb
Host	smart-dac38d6e-1e7f-4066-8583-7312f2493cbe
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334744106 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1334744106
Directory	/workspace/42.edn_alert_test/latest

Test location	/workspace/coverage/default/42.edn_disable.2776394486
Short name	T117
Test name
Test status
Simulation time	22369062 ps
CPU time	0.88 seconds
Started	Feb 07 12:49:10 PM PST 24
Finished	Feb 07 12:49:15 PM PST 24
Peak memory	215092 kb
Host	smart-b6d61371-387b-4768-b7d2-1a418d5897fe
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776394486 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2776394486
Directory	/workspace/42.edn_disable/latest

Test location	/workspace/coverage/default/42.edn_disable_auto_req_mode.804708852
Short name	T483
Test name
Test status
Simulation time	16846649 ps
CPU time	1.01 seconds
Started	Feb 07 12:49:07 PM PST 24
Finished	Feb 07 12:49:13 PM PST 24
Peak memory	215272 kb
Host	smart-dc39ca94-811e-465e-81ae-36e876274ec0
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804708852 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di sable_auto_req_mode.804708852
Directory	/workspace/42.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/42.edn_err.1750701548
Short name	T49
Test name
Test status
Simulation time	23377499 ps
CPU time	1.07 seconds
Started	Feb 07 12:49:05 PM PST 24
Finished	Feb 07 12:49:08 PM PST 24
Peak memory	222416 kb
Host	smart-5760b04c-6dfd-44cd-87af-2d198ff69472
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1750701548 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1750701548
Directory	/workspace/42.edn_err/latest

Test location	/workspace/coverage/default/42.edn_genbits.1233927430
Short name	T953
Test name
Test status
Simulation time	66550217 ps
CPU time	1.47 seconds
Started	Feb 07 12:49:09 PM PST 24
Finished	Feb 07 12:49:16 PM PST 24
Peak memory	218072 kb
Host	smart-d0e029e5-4775-4807-ba21-bc2abb6f4f4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1233927430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1233927430
Directory	/workspace/42.edn_genbits/latest

Test location	/workspace/coverage/default/42.edn_smoke.3456270098
Short name	T792
Test name
Test status
Simulation time	20744629 ps
CPU time	0.94 seconds
Started	Feb 07 12:49:08 PM PST 24
Finished	Feb 07 12:49:14 PM PST 24
Peak memory	214896 kb
Host	smart-39caeecb-c419-49e1-aacb-7f765e8af7ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3456270098 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3456270098
Directory	/workspace/42.edn_smoke/latest

Test location	/workspace/coverage/default/42.edn_stress_all.4160189507
Short name	T832
Test name
Test status
Simulation time	310477918 ps
CPU time	5.95 seconds
Started	Feb 07 12:49:09 PM PST 24
Finished	Feb 07 12:49:20 PM PST 24
Peak memory	215140 kb
Host	smart-c5566f04-60b3-4a64-85ac-ba417ee12e14
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160189507 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.4160189507
Directory	/workspace/42.edn_stress_all/latest

Test location	/workspace/coverage/default/42.edn_stress_all_with_rand_reset.59047228
Short name	T955
Test name
Test status
Simulation time	91708174796 ps
CPU time	608.17 seconds
Started	Feb 07 12:49:07 PM PST 24
Finished	Feb 07 12:59:16 PM PST 24
Peak memory	223476 kb
Host	smart-b71d7728-c806-45d5-a5b1-884963ba7f34
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59047228 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.59047228
Directory	/workspace/42.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.edn_alert.2801716681
Short name	T93
Test name
Test status
Simulation time	34042524 ps
CPU time	0.99 seconds
Started	Feb 07 12:49:17 PM PST 24
Finished	Feb 07 12:49:21 PM PST 24
Peak memory	206140 kb
Host	smart-2ba39422-5004-405b-ad17-9dd835f41d5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2801716681 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2801716681
Directory	/workspace/43.edn_alert/latest

Test location	/workspace/coverage/default/43.edn_alert_test.313276727
Short name	T622
Test name
Test status
Simulation time	27506819 ps
CPU time	0.93 seconds
Started	Feb 07 12:49:08 PM PST 24
Finished	Feb 07 12:49:14 PM PST 24
Peak memory	205888 kb
Host	smart-8482d494-b5a2-4504-a191-994fdb783692
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313276727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.313276727
Directory	/workspace/43.edn_alert_test/latest

Test location	/workspace/coverage/default/43.edn_disable.2581569169
Short name	T456
Test name
Test status
Simulation time	11510018 ps
CPU time	0.9 seconds
Started	Feb 07 12:49:16 PM PST 24
Finished	Feb 07 12:49:20 PM PST 24
Peak memory	215036 kb
Host	smart-16e29c47-61a6-4bba-afa5-484c2babad5a
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581569169 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2581569169
Directory	/workspace/43.edn_disable/latest

Test location	/workspace/coverage/default/43.edn_disable_auto_req_mode.3007725080
Short name	T657
Test name
Test status
Simulation time	71008318 ps
CPU time	0.98 seconds
Started	Feb 07 12:49:11 PM PST 24
Finished	Feb 07 12:49:16 PM PST 24
Peak memory	216780 kb
Host	smart-f9ecd10c-5f55-474f-97b6-6056c1c10e79
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007725080 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d isable_auto_req_mode.3007725080
Directory	/workspace/43.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/43.edn_err.3337586227
Short name	T554
Test name
Test status
Simulation time	30951474 ps
CPU time	0.86 seconds
Started	Feb 07 12:49:08 PM PST 24
Finished	Feb 07 12:49:14 PM PST 24
Peak memory	216560 kb
Host	smart-ecf617b2-12f7-4ce9-b3b1-1ff490082b54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3337586227 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3337586227
Directory	/workspace/43.edn_err/latest

Test location	/workspace/coverage/default/43.edn_intr.1982902507
Short name	T71
Test name
Test status
Simulation time	22666876 ps
CPU time	0.89 seconds
Started	Feb 07 12:48:59 PM PST 24
Finished	Feb 07 12:49:01 PM PST 24
Peak memory	215312 kb
Host	smart-b68bbc61-6a26-483a-b98e-8c029fd409b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1982902507 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1982902507
Directory	/workspace/43.edn_intr/latest

Test location	/workspace/coverage/default/43.edn_smoke.2892450770
Short name	T882
Test name
Test status
Simulation time	33237752 ps
CPU time	0.91 seconds
Started	Feb 07 12:49:09 PM PST 24
Finished	Feb 07 12:49:15 PM PST 24
Peak memory	215020 kb
Host	smart-aba01099-e586-48db-b296-350b018796bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2892450770 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2892450770
Directory	/workspace/43.edn_smoke/latest

Test location	/workspace/coverage/default/43.edn_stress_all.1265700174
Short name	T885
Test name
Test status
Simulation time	1348101754 ps
CPU time	4.89 seconds
Started	Feb 07 12:49:01 PM PST 24
Finished	Feb 07 12:49:07 PM PST 24
Peak memory	215256 kb
Host	smart-04096584-6159-41ba-ac12-6dd696a5ee8d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265700174 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1265700174
Directory	/workspace/43.edn_stress_all/latest

Test location	/workspace/coverage/default/43.edn_stress_all_with_rand_reset.1134331086
Short name	T175
Test name
Test status
Simulation time	209241877881 ps
CPU time	2375.64 seconds
Started	Feb 07 12:49:02 PM PST 24
Finished	Feb 07 01:28:39 PM PST 24
Peak memory	234560 kb
Host	smart-a5c2fcdd-fe26-4e5d-b407-5453afd17344
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134331086 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1134331086
Directory	/workspace/43.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.edn_alert.726932861
Short name	T14
Test name
Test status
Simulation time	23569522 ps
CPU time	1.01 seconds
Started	Feb 07 12:49:08 PM PST 24
Finished	Feb 07 12:49:14 PM PST 24
Peak memory	206060 kb
Host	smart-92c04974-5e33-453f-a406-9fdbb3a64394
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=726932861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.726932861
Directory	/workspace/44.edn_alert/latest

Test location	/workspace/coverage/default/44.edn_alert_test.2539261534
Short name	T781
Test name
Test status
Simulation time	17503609 ps
CPU time	1.08 seconds
Started	Feb 07 12:49:06 PM PST 24
Finished	Feb 07 12:49:09 PM PST 24
Peak memory	205380 kb
Host	smart-0969b197-fa1e-49b4-ae00-20e9a900ae0d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539261534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2539261534
Directory	/workspace/44.edn_alert_test/latest

Test location	/workspace/coverage/default/44.edn_disable.545039722
Short name	T425
Test name
Test status
Simulation time	31056748 ps
CPU time	0.79 seconds
Started	Feb 07 12:49:15 PM PST 24
Finished	Feb 07 12:49:20 PM PST 24
Peak memory	214796 kb
Host	smart-ece6ee1d-60e3-491d-89ae-37dee2d0efee
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545039722 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.545039722
Directory	/workspace/44.edn_disable/latest

Test location	/workspace/coverage/default/44.edn_disable_auto_req_mode.535796409
Short name	T720
Test name
Test status
Simulation time	110448161 ps
CPU time	1.08 seconds
Started	Feb 07 12:49:18 PM PST 24
Finished	Feb 07 12:49:22 PM PST 24
Peak memory	215260 kb
Host	smart-5f24b520-3647-4949-95aa-42cfdf57e184
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535796409 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di sable_auto_req_mode.535796409
Directory	/workspace/44.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/44.edn_err.1732923652
Short name	T6
Test name
Test status
Simulation time	23297017 ps
CPU time	1.11 seconds
Started	Feb 07 12:49:10 PM PST 24
Finished	Feb 07 12:49:16 PM PST 24
Peak memory	216720 kb
Host	smart-b0d0f21b-06b5-4c0f-93b2-148192dfcffc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1732923652 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1732923652
Directory	/workspace/44.edn_err/latest

Test location	/workspace/coverage/default/44.edn_genbits.470775195
Short name	T196
Test name
Test status
Simulation time	42444034 ps
CPU time	1.4 seconds
Started	Feb 07 12:49:04 PM PST 24
Finished	Feb 07 12:49:06 PM PST 24
Peak memory	215540 kb
Host	smart-6a6fc1bf-1cc2-49a4-b3b9-459784265527
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=470775195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.470775195
Directory	/workspace/44.edn_genbits/latest

Test location	/workspace/coverage/default/44.edn_intr.2090867168
Short name	T773
Test name
Test status
Simulation time	20786871 ps
CPU time	1.01 seconds
Started	Feb 07 12:49:14 PM PST 24
Finished	Feb 07 12:49:20 PM PST 24
Peak memory	215236 kb
Host	smart-377d276b-b205-411c-967f-9eedf3154170
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2090867168 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2090867168
Directory	/workspace/44.edn_intr/latest

Test location	/workspace/coverage/default/44.edn_smoke.4272582631
Short name	T673
Test name
Test status
Simulation time	104712476 ps
CPU time	0.89 seconds
Started	Feb 07 12:49:15 PM PST 24
Finished	Feb 07 12:49:20 PM PST 24
Peak memory	214992 kb
Host	smart-bf515c3c-a7a4-4c6a-a525-1c8458695336
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4272582631 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.4272582631
Directory	/workspace/44.edn_smoke/latest

Test location	/workspace/coverage/default/44.edn_stress_all.2992756108
Short name	T716
Test name
Test status
Simulation time	228732162 ps
CPU time	2.74 seconds
Started	Feb 07 12:49:18 PM PST 24
Finished	Feb 07 12:49:23 PM PST 24
Peak memory	215504 kb
Host	smart-6387acbc-4989-4a30-b41e-86c3da8585d3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992756108 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2992756108
Directory	/workspace/44.edn_stress_all/latest

Test location	/workspace/coverage/default/44.edn_stress_all_with_rand_reset.2269978236
Short name	T933
Test name
Test status
Simulation time	133278475196 ps
CPU time	867.21 seconds
Started	Feb 07 12:49:14 PM PST 24
Finished	Feb 07 01:03:46 PM PST 24
Peak memory	221088 kb
Host	smart-0469a4dc-bc18-43fd-8dcd-31054a708068
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269978236 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2269978236
Directory	/workspace/44.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.edn_alert.39133068
Short name	T235
Test name
Test status
Simulation time	20626881 ps
CPU time	1.03 seconds
Started	Feb 07 12:49:08 PM PST 24
Finished	Feb 07 12:49:14 PM PST 24
Peak memory	206064 kb
Host	smart-f3c281b5-5f53-4faa-b4aa-9f4418dfed89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=39133068 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.39133068
Directory	/workspace/45.edn_alert/latest

Test location	/workspace/coverage/default/45.edn_alert_test.2388308071
Short name	T907
Test name
Test status
Simulation time	70088267 ps
CPU time	0.91 seconds
Started	Feb 07 12:49:04 PM PST 24
Finished	Feb 07 12:49:06 PM PST 24
Peak memory	205984 kb
Host	smart-38f76c89-9be5-446c-8a94-c6983bbe4ffb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388308071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2388308071
Directory	/workspace/45.edn_alert_test/latest

Test location	/workspace/coverage/default/45.edn_disable.187063159
Short name	T911
Test name
Test status
Simulation time	36434032 ps
CPU time	0.83 seconds
Started	Feb 07 12:49:10 PM PST 24
Finished	Feb 07 12:49:15 PM PST 24
Peak memory	215092 kb
Host	smart-7dd364b3-d3b5-4169-958d-e8562d241858
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187063159 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.187063159
Directory	/workspace/45.edn_disable/latest

Test location	/workspace/coverage/default/45.edn_err.597084773
Short name	T734
Test name
Test status
Simulation time	24292833 ps
CPU time	1.16 seconds
Started	Feb 07 12:49:19 PM PST 24
Finished	Feb 07 12:49:23 PM PST 24
Peak memory	215608 kb
Host	smart-c253e0b4-1746-465b-be08-73b23e1c0986
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=597084773 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.597084773
Directory	/workspace/45.edn_err/latest

Test location	/workspace/coverage/default/45.edn_genbits.3895940495
Short name	T854
Test name
Test status
Simulation time	136907169 ps
CPU time	2.7 seconds
Started	Feb 07 12:49:21 PM PST 24
Finished	Feb 07 12:49:25 PM PST 24
Peak memory	216628 kb
Host	smart-ca1ee3c8-fd5c-4da9-85a1-c06e235f299f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3895940495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3895940495
Directory	/workspace/45.edn_genbits/latest

Test location	/workspace/coverage/default/45.edn_intr.1604370189
Short name	T687
Test name
Test status
Simulation time	22152230 ps
CPU time	1.04 seconds
Started	Feb 07 12:49:15 PM PST 24
Finished	Feb 07 12:49:20 PM PST 24
Peak memory	215360 kb
Host	smart-d2afc7d7-bcda-4109-b5b0-5f12bf9d017b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1604370189 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1604370189
Directory	/workspace/45.edn_intr/latest

Test location	/workspace/coverage/default/45.edn_smoke.3033119215
Short name	T497
Test name
Test status
Simulation time	27250440 ps
CPU time	0.94 seconds
Started	Feb 07 12:49:14 PM PST 24
Finished	Feb 07 12:49:19 PM PST 24
Peak memory	215000 kb
Host	smart-b3124e16-f863-4a92-b186-8687ee331d47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3033119215 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3033119215
Directory	/workspace/45.edn_smoke/latest

Test location	/workspace/coverage/default/45.edn_stress_all.3542372212
Short name	T592
Test name
Test status
Simulation time	330114286 ps
CPU time	3.89 seconds
Started	Feb 07 12:49:08 PM PST 24
Finished	Feb 07 12:49:17 PM PST 24
Peak memory	218168 kb
Host	smart-b05e59e6-a4eb-42c0-b5a1-40216c41e0f8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542372212 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3542372212
Directory	/workspace/45.edn_stress_all/latest

Test location	/workspace/coverage/default/45.edn_stress_all_with_rand_reset.2905058706
Short name	T498
Test name
Test status
Simulation time	160037952729 ps
CPU time	737.36 seconds
Started	Feb 07 12:49:04 PM PST 24
Finished	Feb 07 01:01:23 PM PST 24
Peak memory	223424 kb
Host	smart-0bb0bb77-13e2-4565-a704-befc4e00cec1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905058706 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2905058706
Directory	/workspace/45.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.edn_alert_test.3425941810
Short name	T435
Test name
Test status
Simulation time	14529594 ps
CPU time	0.8 seconds
Started	Feb 07 12:49:28 PM PST 24
Finished	Feb 07 12:49:31 PM PST 24
Peak memory	205148 kb
Host	smart-f2e485e1-6555-4ef8-b0d0-19abd825a295
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425941810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3425941810
Directory	/workspace/46.edn_alert_test/latest

Test location	/workspace/coverage/default/46.edn_disable.1216911175
Short name	T930
Test name
Test status
Simulation time	14027775 ps
CPU time	0.85 seconds
Started	Feb 07 12:49:23 PM PST 24
Finished	Feb 07 12:49:25 PM PST 24
Peak memory	214844 kb
Host	smart-6c93851f-4b9e-478c-8fc5-71a81f1d397a
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216911175 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1216911175
Directory	/workspace/46.edn_disable/latest

Test location	/workspace/coverage/default/46.edn_disable_auto_req_mode.3302855139
Short name	T533
Test name
Test status
Simulation time	64507251 ps
CPU time	1.14 seconds
Started	Feb 07 12:49:15 PM PST 24
Finished	Feb 07 12:49:20 PM PST 24
Peak memory	215256 kb
Host	smart-6f9bce8f-a330-46bc-812c-8d79501252f0
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302855139 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d isable_auto_req_mode.3302855139
Directory	/workspace/46.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/46.edn_err.2718307370
Short name	T600
Test name
Test status
Simulation time	24628641 ps
CPU time	1.05 seconds
Started	Feb 07 12:49:29 PM PST 24
Finished	Feb 07 12:49:31 PM PST 24
Peak memory	222024 kb
Host	smart-543e4718-5b01-4926-8e1a-32709dc9f92e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2718307370 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2718307370
Directory	/workspace/46.edn_err/latest

Test location	/workspace/coverage/default/46.edn_genbits.1261961475
Short name	T601
Test name
Test status
Simulation time	263488083 ps
CPU time	2.14 seconds
Started	Feb 07 12:49:17 PM PST 24
Finished	Feb 07 12:49:22 PM PST 24
Peak memory	216600 kb
Host	smart-1b3c2993-b2d3-42c8-8266-af8850ee13e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1261961475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1261961475
Directory	/workspace/46.edn_genbits/latest

Test location	/workspace/coverage/default/46.edn_intr.673192693
Short name	T69
Test name
Test status
Simulation time	22779466 ps
CPU time	0.97 seconds
Started	Feb 07 12:49:16 PM PST 24
Finished	Feb 07 12:49:20 PM PST 24
Peak memory	215340 kb
Host	smart-b42d704d-a769-4972-bdba-db0883d80279
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=673192693 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.673192693
Directory	/workspace/46.edn_intr/latest

Test location	/workspace/coverage/default/46.edn_smoke.2609556755
Short name	T801
Test name
Test status
Simulation time	16351676 ps
CPU time	0.94 seconds
Started	Feb 07 12:49:17 PM PST 24
Finished	Feb 07 12:49:21 PM PST 24
Peak memory	214984 kb
Host	smart-ba29c963-e4ed-496d-820f-385e91535776
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2609556755 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2609556755
Directory	/workspace/46.edn_smoke/latest

Test location	/workspace/coverage/default/46.edn_stress_all.997540699
Short name	T517
Test name
Test status
Simulation time	98107238 ps
CPU time	1.08 seconds
Started	Feb 07 12:49:29 PM PST 24
Finished	Feb 07 12:49:31 PM PST 24
Peak memory	214480 kb
Host	smart-b7fcf2d8-b65d-45d6-b62d-b37ff1ce774d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997540699 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.997540699
Directory	/workspace/46.edn_stress_all/latest

Test location	/workspace/coverage/default/46.edn_stress_all_with_rand_reset.1450704568
Short name	T862
Test name
Test status
Simulation time	19046576618 ps
CPU time	423.48 seconds
Started	Feb 07 12:49:15 PM PST 24
Finished	Feb 07 12:56:22 PM PST 24
Peak memory	217660 kb
Host	smart-f099af71-1beb-4538-bc23-7c1269cb1c2d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450704568 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1450704568
Directory	/workspace/46.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.edn_alert.2744005892
Short name	T220
Test name
Test status
Simulation time	159434460 ps
CPU time	0.97 seconds
Started	Feb 07 12:49:13 PM PST 24
Finished	Feb 07 12:49:16 PM PST 24
Peak memory	206164 kb
Host	smart-d7b9e823-2837-4bb9-b8a0-f827997c5aa5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2744005892 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2744005892
Directory	/workspace/47.edn_alert/latest

Test location	/workspace/coverage/default/47.edn_alert_test.1167861822
Short name	T558
Test name
Test status
Simulation time	22090711 ps
CPU time	0.92 seconds
Started	Feb 07 12:49:25 PM PST 24
Finished	Feb 07 12:49:27 PM PST 24
Peak memory	205824 kb
Host	smart-ef0a0c8a-b248-4c84-a96c-2eca2cb3d708
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167861822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1167861822
Directory	/workspace/47.edn_alert_test/latest

Test location	/workspace/coverage/default/47.edn_disable.292405214
Short name	T863
Test name
Test status
Simulation time	11170792 ps
CPU time	0.9 seconds
Started	Feb 07 12:49:22 PM PST 24
Finished	Feb 07 12:49:24 PM PST 24
Peak memory	214976 kb
Host	smart-ade48443-4a02-40a6-bcf2-fb307d80e1fe
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292405214 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.292405214
Directory	/workspace/47.edn_disable/latest

Test location	/workspace/coverage/default/47.edn_err.1967194562
Short name	T667
Test name
Test status
Simulation time	37534310 ps
CPU time	0.92 seconds
Started	Feb 07 12:49:14 PM PST 24
Finished	Feb 07 12:49:20 PM PST 24
Peak memory	221988 kb
Host	smart-28fa5adf-5d18-4f38-a69c-53c8f6cc4c69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1967194562 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1967194562
Directory	/workspace/47.edn_err/latest

Test location	/workspace/coverage/default/47.edn_genbits.2831888383
Short name	T386
Test name
Test status
Simulation time	32455712 ps
CPU time	1.33 seconds
Started	Feb 07 12:49:14 PM PST 24
Finished	Feb 07 12:49:20 PM PST 24
Peak memory	217852 kb
Host	smart-6e8bf409-3fd6-4bb7-b244-9e678b3894c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2831888383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2831888383
Directory	/workspace/47.edn_genbits/latest

Test location	/workspace/coverage/default/47.edn_intr.30746607
Short name	T629
Test name
Test status
Simulation time	22817659 ps
CPU time	0.95 seconds
Started	Feb 07 12:49:13 PM PST 24
Finished	Feb 07 12:49:16 PM PST 24
Peak memory	215200 kb
Host	smart-9b0f99f1-b642-4563-9f4e-c043a4cfb34a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30746607 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.30746607
Directory	/workspace/47.edn_intr/latest

Test location	/workspace/coverage/default/47.edn_smoke.855770358
Short name	T813
Test name
Test status
Simulation time	16651494 ps
CPU time	0.96 seconds
Started	Feb 07 12:49:13 PM PST 24
Finished	Feb 07 12:49:16 PM PST 24
Peak memory	215020 kb
Host	smart-1206a967-be30-4b38-8e2e-fe60020630d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=855770358 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.855770358
Directory	/workspace/47.edn_smoke/latest

Test location	/workspace/coverage/default/47.edn_stress_all.840116350
Short name	T689
Test name
Test status
Simulation time	605359029 ps
CPU time	5.64 seconds
Started	Feb 07 12:49:30 PM PST 24
Finished	Feb 07 12:49:37 PM PST 24
Peak memory	215036 kb
Host	smart-2b88ad4e-f1b2-4c3c-8e75-ac22b54c3af3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840116350 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.840116350
Directory	/workspace/47.edn_stress_all/latest

Test location	/workspace/coverage/default/47.edn_stress_all_with_rand_reset.2720042150
Short name	T944
Test name
Test status
Simulation time	105971453880 ps
CPU time	667.25 seconds
Started	Feb 07 12:49:15 PM PST 24
Finished	Feb 07 01:00:26 PM PST 24
Peak memory	220284 kb
Host	smart-fed7f629-8ad6-438c-8659-4bbcc3afbd3a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720042150 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2720042150
Directory	/workspace/47.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.edn_alert.677411760
Short name	T13
Test name
Test status
Simulation time	35727114 ps
CPU time	1 seconds
Started	Feb 07 12:49:17 PM PST 24
Finished	Feb 07 12:49:21 PM PST 24
Peak memory	205980 kb
Host	smart-7b3acf2b-56f6-4f9a-b19f-019414e5a1c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=677411760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.677411760
Directory	/workspace/48.edn_alert/latest

Test location	/workspace/coverage/default/48.edn_alert_test.3954064095
Short name	T684
Test name
Test status
Simulation time	23650667 ps
CPU time	0.88 seconds
Started	Feb 07 12:49:16 PM PST 24
Finished	Feb 07 12:49:21 PM PST 24
Peak memory	205492 kb
Host	smart-53b030f3-406a-449f-b78f-6466b7a0547f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954064095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3954064095
Directory	/workspace/48.edn_alert_test/latest

Test location	/workspace/coverage/default/48.edn_disable.3235810201
Short name	T477
Test name
Test status
Simulation time	17125678 ps
CPU time	0.89 seconds
Started	Feb 07 12:49:31 PM PST 24
Finished	Feb 07 12:49:34 PM PST 24
Peak memory	214968 kb
Host	smart-434723ad-16d4-4c81-81f3-cf0f05374e3e
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235810201 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3235810201
Directory	/workspace/48.edn_disable/latest

Test location	/workspace/coverage/default/48.edn_err.2728668479
Short name	T869
Test name
Test status
Simulation time	25732828 ps
CPU time	0.86 seconds
Started	Feb 07 12:49:21 PM PST 24
Finished	Feb 07 12:49:23 PM PST 24
Peak memory	216440 kb
Host	smart-5cca1ff3-8f4b-4006-b0b1-7a8030a561e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2728668479 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2728668479
Directory	/workspace/48.edn_err/latest

Test location	/workspace/coverage/default/48.edn_genbits.2246569268
Short name	T906
Test name
Test status
Simulation time	65747220 ps
CPU time	1.19 seconds
Started	Feb 07 12:49:17 PM PST 24
Finished	Feb 07 12:49:21 PM PST 24
Peak memory	215488 kb
Host	smart-65c1432a-3bf7-49ed-88d1-469ea96dd314
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2246569268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2246569268
Directory	/workspace/48.edn_genbits/latest

Test location	/workspace/coverage/default/48.edn_intr.3185814951
Short name	T412
Test name
Test status
Simulation time	24963511 ps
CPU time	0.95 seconds
Started	Feb 07 12:49:13 PM PST 24
Finished	Feb 07 12:49:19 PM PST 24
Peak memory	215208 kb
Host	smart-dc7255da-cbc3-46e7-b1e8-f48c7891f12c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3185814951 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3185814951
Directory	/workspace/48.edn_intr/latest

Test location	/workspace/coverage/default/48.edn_smoke.423658861
Short name	T357
Test name
Test status
Simulation time	33898265 ps
CPU time	0.84 seconds
Started	Feb 07 12:49:27 PM PST 24
Finished	Feb 07 12:49:29 PM PST 24
Peak memory	215060 kb
Host	smart-fb2fd10f-ae94-43f1-a106-df3e22460c0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=423658861 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.423658861
Directory	/workspace/48.edn_smoke/latest

Test location	/workspace/coverage/default/48.edn_stress_all.4201474079
Short name	T809
Test name
Test status
Simulation time	105733608 ps
CPU time	1.67 seconds
Started	Feb 07 12:49:17 PM PST 24
Finished	Feb 07 12:49:22 PM PST 24
Peak memory	215424 kb
Host	smart-bc1a0173-6863-4303-afd2-ac3760b4752e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201474079 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.4201474079
Directory	/workspace/48.edn_stress_all/latest

Test location	/workspace/coverage/default/48.edn_stress_all_with_rand_reset.980828868
Short name	T191
Test name
Test status
Simulation time	105665325993 ps
CPU time	538.25 seconds
Started	Feb 07 12:49:31 PM PST 24
Finished	Feb 07 12:58:31 PM PST 24
Peak memory	218284 kb
Host	smart-45425b50-f7f9-4408-81e7-f04ab06f2b35
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980828868 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.980828868
Directory	/workspace/48.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.edn_alert.3693136577
Short name	T222
Test name
Test status
Simulation time	48844935 ps
CPU time	0.98 seconds
Started	Feb 07 12:49:16 PM PST 24
Finished	Feb 07 12:49:20 PM PST 24
Peak memory	206064 kb
Host	smart-d0834145-b21b-4ba4-b285-2c0d387283bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3693136577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3693136577
Directory	/workspace/49.edn_alert/latest

Test location	/workspace/coverage/default/49.edn_alert_test.4040809362
Short name	T621
Test name
Test status
Simulation time	14552102 ps
CPU time	0.87 seconds
Started	Feb 07 12:49:27 PM PST 24
Finished	Feb 07 12:49:30 PM PST 24
Peak memory	205432 kb
Host	smart-0f423b6c-75c5-475e-8887-6e86b464acef
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040809362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.4040809362
Directory	/workspace/49.edn_alert_test/latest

Test location	/workspace/coverage/default/49.edn_disable.2869176857
Short name	T56
Test name
Test status
Simulation time	21425978 ps
CPU time	0.86 seconds
Started	Feb 07 12:49:25 PM PST 24
Finished	Feb 07 12:49:27 PM PST 24
Peak memory	215008 kb
Host	smart-2d06692c-2024-4710-8330-cb1916c1769e
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869176857 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2869176857
Directory	/workspace/49.edn_disable/latest

Test location	/workspace/coverage/default/49.edn_disable_auto_req_mode.2608319798
Short name	T921
Test name
Test status
Simulation time	75360582 ps
CPU time	1.11 seconds
Started	Feb 07 12:49:24 PM PST 24
Finished	Feb 07 12:49:26 PM PST 24
Peak memory	216204 kb
Host	smart-2b80cb23-37b8-4850-82bd-1357e5cb5e03
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608319798 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d isable_auto_req_mode.2608319798
Directory	/workspace/49.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/49.edn_err.3340310579
Short name	T859
Test name
Test status
Simulation time	45723877 ps
CPU time	1.2 seconds
Started	Feb 07 12:49:29 PM PST 24
Finished	Feb 07 12:49:32 PM PST 24
Peak memory	222648 kb
Host	smart-8c89b27f-3af3-4db8-9963-6ceb9ebacc39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3340310579 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3340310579
Directory	/workspace/49.edn_err/latest

Test location	/workspace/coverage/default/49.edn_genbits.1204716889
Short name	T819
Test name
Test status
Simulation time	43926011 ps
CPU time	1.08 seconds
Started	Feb 07 12:49:26 PM PST 24
Finished	Feb 07 12:49:28 PM PST 24
Peak memory	215344 kb
Host	smart-0a65d301-8c1c-4bae-bee2-450fd1cfe723
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1204716889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1204716889
Directory	/workspace/49.edn_genbits/latest

Test location	/workspace/coverage/default/49.edn_intr.1770780598
Short name	T867
Test name
Test status
Simulation time	22200325 ps
CPU time	1.17 seconds
Started	Feb 07 12:49:22 PM PST 24
Finished	Feb 07 12:49:24 PM PST 24
Peak memory	222576 kb
Host	smart-cba64857-bce2-4409-bb40-9fc848288e47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1770780598 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1770780598
Directory	/workspace/49.edn_intr/latest

Test location	/workspace/coverage/default/49.edn_smoke.3339623808
Short name	T947
Test name
Test status
Simulation time	56746275 ps
CPU time	1 seconds
Started	Feb 07 12:49:13 PM PST 24
Finished	Feb 07 12:49:19 PM PST 24
Peak memory	215000 kb
Host	smart-3330dcfb-709e-42e4-996a-61134d30780d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3339623808 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3339623808
Directory	/workspace/49.edn_smoke/latest

Test location	/workspace/coverage/default/49.edn_stress_all.2694596302
Short name	T877
Test name
Test status
Simulation time	270697960 ps
CPU time	2.1 seconds
Started	Feb 07 12:49:14 PM PST 24
Finished	Feb 07 12:49:21 PM PST 24
Peak memory	215396 kb
Host	smart-094c3f71-b7f8-4c74-8949-5752b6e1ca06
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694596302 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2694596302
Directory	/workspace/49.edn_stress_all/latest

Test location	/workspace/coverage/default/49.edn_stress_all_with_rand_reset.2076305265
Short name	T951
Test name
Test status
Simulation time	26655129352 ps
CPU time	595.63 seconds
Started	Feb 07 12:49:30 PM PST 24
Finished	Feb 07 12:59:33 PM PST 24
Peak memory	216328 kb
Host	smart-813a6d2e-25ff-4a1b-8ae0-875ae4e6cea5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076305265 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2076305265
Directory	/workspace/49.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.edn_alert.618998253
Short name	T712
Test name
Test status
Simulation time	30002613 ps
CPU time	1.01 seconds
Started	Feb 07 12:47:56 PM PST 24
Finished	Feb 07 12:47:58 PM PST 24
Peak memory	206104 kb
Host	smart-5f65b283-ada0-4e8c-81f1-413f4cc3b8a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=618998253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.618998253
Directory	/workspace/5.edn_alert/latest

Test location	/workspace/coverage/default/5.edn_alert_test.3819125012
Short name	T494
Test name
Test status
Simulation time	35180656 ps
CPU time	0.81 seconds
Started	Feb 07 12:48:00 PM PST 24
Finished	Feb 07 12:48:02 PM PST 24
Peak memory	205244 kb
Host	smart-5c362cf2-86e8-4e7f-a41d-fc77f37f1577
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819125012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3819125012
Directory	/workspace/5.edn_alert_test/latest

Test location	/workspace/coverage/default/5.edn_disable.3525952453
Short name	T111
Test name
Test status
Simulation time	40323566 ps
CPU time	0.83 seconds
Started	Feb 07 12:47:59 PM PST 24
Finished	Feb 07 12:48:01 PM PST 24
Peak memory	215036 kb
Host	smart-32e5f6c4-1c94-421a-9a85-58a01d0cb8d8
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525952453 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3525952453
Directory	/workspace/5.edn_disable/latest

Test location	/workspace/coverage/default/5.edn_err.2004150404
Short name	T617
Test name
Test status
Simulation time	32437160 ps
CPU time	0.85 seconds
Started	Feb 07 12:47:56 PM PST 24
Finished	Feb 07 12:47:57 PM PST 24
Peak memory	216376 kb
Host	smart-f61a8f9b-c701-4150-af9a-4ac68bfe51ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2004150404 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2004150404
Directory	/workspace/5.edn_err/latest

Test location	/workspace/coverage/default/5.edn_genbits.3802979476
Short name	T675
Test name
Test status
Simulation time	186375121 ps
CPU time	1.17 seconds
Started	Feb 07 12:47:56 PM PST 24
Finished	Feb 07 12:47:58 PM PST 24
Peak memory	216556 kb
Host	smart-81dff333-3422-497c-b7fd-e2c24cdc20a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3802979476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3802979476
Directory	/workspace/5.edn_genbits/latest

Test location	/workspace/coverage/default/5.edn_intr.3190474056
Short name	T958
Test name
Test status
Simulation time	39046153 ps
CPU time	0.87 seconds
Started	Feb 07 12:47:58 PM PST 24
Finished	Feb 07 12:48:00 PM PST 24
Peak memory	215124 kb
Host	smart-8b6adc97-f194-496c-8d8d-0f648dcaea80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3190474056 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3190474056
Directory	/workspace/5.edn_intr/latest

Test location	/workspace/coverage/default/5.edn_regwen.3164389962
Short name	T224
Test name
Test status
Simulation time	24811913 ps
CPU time	0.93 seconds
Started	Feb 07 12:47:58 PM PST 24
Finished	Feb 07 12:48:00 PM PST 24
Peak memory	206804 kb
Host	smart-a98ce831-f5ac-4af9-aae5-1528128d0f2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3164389962 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3164389962
Directory	/workspace/5.edn_regwen/latest

Test location	/workspace/coverage/default/5.edn_smoke.4103478750
Short name	T384
Test name
Test status
Simulation time	17614459 ps
CPU time	1.01 seconds
Started	Feb 07 12:48:00 PM PST 24
Finished	Feb 07 12:48:02 PM PST 24
Peak memory	215008 kb
Host	smart-c00b9c07-8c9a-489b-ba6b-772d858fc409
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4103478750 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.4103478750
Directory	/workspace/5.edn_smoke/latest

Test location	/workspace/coverage/default/5.edn_stress_all.3799097421
Short name	T787
Test name
Test status
Simulation time	1633389403 ps
CPU time	4.73 seconds
Started	Feb 07 12:47:57 PM PST 24
Finished	Feb 07 12:48:02 PM PST 24
Peak memory	215168 kb
Host	smart-8a8ac675-1695-42da-819c-4dddc5620b91
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799097421 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3799097421
Directory	/workspace/5.edn_stress_all/latest

Test location	/workspace/coverage/default/5.edn_stress_all_with_rand_reset.2885063321
Short name	T184
Test name
Test status
Simulation time	105737753851 ps
CPU time	1133.67 seconds
Started	Feb 07 12:48:00 PM PST 24
Finished	Feb 07 01:06:55 PM PST 24
Peak memory	222884 kb
Host	smart-9eb100dd-64db-4b1f-bcb1-c39819a3d217
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885063321 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2885063321
Directory	/workspace/5.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/50.edn_err.2437286319
Short name	T377
Test name
Test status
Simulation time	37325793 ps
CPU time	0.84 seconds
Started	Feb 07 12:49:32 PM PST 24
Finished	Feb 07 12:49:34 PM PST 24
Peak memory	216712 kb
Host	smart-2f569f24-f60a-4096-8b56-5023636a4731
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2437286319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2437286319
Directory	/workspace/50.edn_err/latest

Test location	/workspace/coverage/default/50.edn_genbits.1701233370
Short name	T511
Test name
Test status
Simulation time	125963060 ps
CPU time	3.13 seconds
Started	Feb 07 12:49:34 PM PST 24
Finished	Feb 07 12:49:39 PM PST 24
Peak memory	218188 kb
Host	smart-46cd4c67-a328-4bf9-90e1-6020a3ce030d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1701233370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1701233370
Directory	/workspace/50.edn_genbits/latest

Test location	/workspace/coverage/default/51.edn_err.3492538568
Short name	T865
Test name
Test status
Simulation time	33457397 ps
CPU time	0.97 seconds
Started	Feb 07 12:49:24 PM PST 24
Finished	Feb 07 12:49:26 PM PST 24
Peak memory	222476 kb
Host	smart-d58f9ed4-d254-485f-a066-7740cb45d1b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492538568 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3492538568
Directory	/workspace/51.edn_err/latest

Test location	/workspace/coverage/default/51.edn_genbits.4257769467
Short name	T688
Test name
Test status
Simulation time	74216183 ps
CPU time	1.53 seconds
Started	Feb 07 12:49:29 PM PST 24
Finished	Feb 07 12:49:32 PM PST 24
Peak memory	216728 kb
Host	smart-d0d2f6a0-4d37-4add-8273-8da26f47abf9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4257769467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.4257769467
Directory	/workspace/51.edn_genbits/latest

Test location	/workspace/coverage/default/52.edn_err.3166131398
Short name	T379
Test name
Test status
Simulation time	42304806 ps
CPU time	1.21 seconds
Started	Feb 07 12:49:29 PM PST 24
Finished	Feb 07 12:49:32 PM PST 24
Peak memory	222660 kb
Host	smart-4ccef8d8-ed29-46b7-9549-8af246bac1ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3166131398 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3166131398
Directory	/workspace/52.edn_err/latest

Test location	/workspace/coverage/default/52.edn_genbits.1857249066
Short name	T176
Test name
Test status
Simulation time	30650951 ps
CPU time	1.22 seconds
Started	Feb 07 12:49:28 PM PST 24
Finished	Feb 07 12:49:31 PM PST 24
Peak memory	216688 kb
Host	smart-d800c477-c6eb-433d-b141-3aea917818f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1857249066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1857249066
Directory	/workspace/52.edn_genbits/latest

Test location	/workspace/coverage/default/53.edn_err.2825885368
Short name	T238
Test name
Test status
Simulation time	22324288 ps
CPU time	1.14 seconds
Started	Feb 07 12:49:27 PM PST 24
Finished	Feb 07 12:49:29 PM PST 24
Peak memory	216552 kb
Host	smart-41561b88-19a6-454c-b556-a3266747597e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2825885368 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2825885368
Directory	/workspace/53.edn_err/latest

Test location	/workspace/coverage/default/53.edn_genbits.2773191070
Short name	T427
Test name
Test status
Simulation time	36554164 ps
CPU time	1.28 seconds
Started	Feb 07 12:49:27 PM PST 24
Finished	Feb 07 12:49:29 PM PST 24
Peak memory	216620 kb
Host	smart-191456ef-6078-4c05-9abc-a047bc0af911
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2773191070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2773191070
Directory	/workspace/53.edn_genbits/latest

Test location	/workspace/coverage/default/54.edn_err.2777402736
Short name	T956
Test name
Test status
Simulation time	20769522 ps
CPU time	0.92 seconds
Started	Feb 07 12:49:30 PM PST 24
Finished	Feb 07 12:49:32 PM PST 24
Peak memory	216608 kb
Host	smart-0b78afb7-79a8-4bdd-b7f2-131e4d946da6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2777402736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2777402736
Directory	/workspace/54.edn_err/latest

Test location	/workspace/coverage/default/54.edn_genbits.2401203193
Short name	T872
Test name
Test status
Simulation time	71741183 ps
CPU time	1.01 seconds
Started	Feb 07 12:49:30 PM PST 24
Finished	Feb 07 12:49:33 PM PST 24
Peak memory	215220 kb
Host	smart-15243753-5657-435b-a7a5-1d768329d313
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2401203193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2401203193
Directory	/workspace/54.edn_genbits/latest

Test location	/workspace/coverage/default/55.edn_err.1022486465
Short name	T747
Test name
Test status
Simulation time	23155147 ps
CPU time	0.93 seconds
Started	Feb 07 12:49:26 PM PST 24
Finished	Feb 07 12:49:28 PM PST 24
Peak memory	216880 kb
Host	smart-2b651189-3ded-48ab-a2fc-2e3888eadb99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1022486465 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1022486465
Directory	/workspace/55.edn_err/latest

Test location	/workspace/coverage/default/55.edn_genbits.19718640
Short name	T79
Test name
Test status
Simulation time	34420409 ps
CPU time	1.38 seconds
Started	Feb 07 12:49:27 PM PST 24
Finished	Feb 07 12:49:29 PM PST 24
Peak memory	216624 kb
Host	smart-b45284f7-c9eb-4bf2-99dd-573399fddd47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=19718640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.19718640
Directory	/workspace/55.edn_genbits/latest

Test location	/workspace/coverage/default/56.edn_genbits.2436092851
Short name	T789
Test name
Test status
Simulation time	52494406 ps
CPU time	1.11 seconds
Started	Feb 07 12:49:26 PM PST 24
Finished	Feb 07 12:49:28 PM PST 24
Peak memory	216920 kb
Host	smart-195a519d-b7ac-405b-9ce8-8b5814ae81b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2436092851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2436092851
Directory	/workspace/56.edn_genbits/latest

Test location	/workspace/coverage/default/57.edn_err.1681026892
Short name	T938
Test name
Test status
Simulation time	101598546 ps
CPU time	0.87 seconds
Started	Feb 07 12:49:31 PM PST 24
Finished	Feb 07 12:49:34 PM PST 24
Peak memory	216760 kb
Host	smart-42427644-e89e-47ba-9381-666eb13ed915
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1681026892 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1681026892
Directory	/workspace/57.edn_err/latest

Test location	/workspace/coverage/default/57.edn_genbits.390495873
Short name	T542
Test name
Test status
Simulation time	41870867 ps
CPU time	1.31 seconds
Started	Feb 07 12:49:33 PM PST 24
Finished	Feb 07 12:49:36 PM PST 24
Peak memory	216312 kb
Host	smart-6a5e3326-4b7b-4f5e-93d3-e3d98b175c80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=390495873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.390495873
Directory	/workspace/57.edn_genbits/latest

Test location	/workspace/coverage/default/58.edn_err.2421194329
Short name	T624
Test name
Test status
Simulation time	30085956 ps
CPU time	0.91 seconds
Started	Feb 07 12:49:38 PM PST 24
Finished	Feb 07 12:49:42 PM PST 24
Peak memory	221332 kb
Host	smart-0f765998-3192-45eb-aac9-207c91b5de6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2421194329 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2421194329
Directory	/workspace/58.edn_err/latest

Test location	/workspace/coverage/default/58.edn_genbits.1482284473
Short name	T604
Test name
Test status
Simulation time	172991618 ps
CPU time	2.44 seconds
Started	Feb 07 12:49:35 PM PST 24
Finished	Feb 07 12:49:39 PM PST 24
Peak memory	216660 kb
Host	smart-b7f074ff-e6c2-4c83-9ee9-e4ae61a3a9a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1482284473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1482284473
Directory	/workspace/58.edn_genbits/latest

Test location	/workspace/coverage/default/59.edn_genbits.3973763449
Short name	T857
Test name
Test status
Simulation time	311163793 ps
CPU time	1.82 seconds
Started	Feb 07 12:49:32 PM PST 24
Finished	Feb 07 12:49:35 PM PST 24
Peak memory	217172 kb
Host	smart-1e62243d-3098-417c-835a-9cff5444a32a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3973763449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3973763449
Directory	/workspace/59.edn_genbits/latest

Test location	/workspace/coverage/default/6.edn_alert.2508020451
Short name	T962
Test name
Test status
Simulation time	22468172 ps
CPU time	1.04 seconds
Started	Feb 07 12:47:58 PM PST 24
Finished	Feb 07 12:48:00 PM PST 24
Peak memory	206044 kb
Host	smart-b8b0cfba-00a6-42ea-8770-c32b9dd90d91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2508020451 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2508020451
Directory	/workspace/6.edn_alert/latest

Test location	/workspace/coverage/default/6.edn_alert_test.928478921
Short name	T588
Test name
Test status
Simulation time	13069410 ps
CPU time	0.87 seconds
Started	Feb 07 12:48:01 PM PST 24
Finished	Feb 07 12:48:03 PM PST 24
Peak memory	205356 kb
Host	smart-fda4bd48-3827-499e-93d7-c4a0379655f3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928478921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.928478921
Directory	/workspace/6.edn_alert_test/latest

Test location	/workspace/coverage/default/6.edn_disable.4222334475
Short name	T107
Test name
Test status
Simulation time	10950902 ps
CPU time	0.88 seconds
Started	Feb 07 12:48:00 PM PST 24
Finished	Feb 07 12:48:02 PM PST 24
Peak memory	214996 kb
Host	smart-74f5faf3-923b-4353-b601-26256143d246
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222334475 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.4222334475
Directory	/workspace/6.edn_disable/latest

Test location	/workspace/coverage/default/6.edn_err.1553855054
Short name	T810
Test name
Test status
Simulation time	46774283 ps
CPU time	0.97 seconds
Started	Feb 07 12:47:59 PM PST 24
Finished	Feb 07 12:48:01 PM PST 24
Peak memory	215464 kb
Host	smart-ed464e4d-a534-456f-a05a-0a4f7a7150dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1553855054 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1553855054
Directory	/workspace/6.edn_err/latest

Test location	/workspace/coverage/default/6.edn_genbits.1230449065
Short name	T206
Test name
Test status
Simulation time	65904632 ps
CPU time	1.1 seconds
Started	Feb 07 12:47:57 PM PST 24
Finished	Feb 07 12:47:59 PM PST 24
Peak memory	216544 kb
Host	smart-a93eb753-3549-4f8d-9aec-600b13a23c9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1230449065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1230449065
Directory	/workspace/6.edn_genbits/latest

Test location	/workspace/coverage/default/6.edn_intr.872770249
Short name	T853
Test name
Test status
Simulation time	20511468 ps
CPU time	1.07 seconds
Started	Feb 07 12:47:57 PM PST 24
Finished	Feb 07 12:47:59 PM PST 24
Peak memory	215072 kb
Host	smart-43a3fc68-38b2-4e16-8606-675e8a680a4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872770249 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.872770249
Directory	/workspace/6.edn_intr/latest

Test location	/workspace/coverage/default/6.edn_regwen.3309176736
Short name	T166
Test name
Test status
Simulation time	42474389 ps
CPU time	0.87 seconds
Started	Feb 07 12:47:58 PM PST 24
Finished	Feb 07 12:48:00 PM PST 24
Peak memory	206808 kb
Host	smart-89197f4a-b6d5-4a11-a657-07056711b7aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3309176736 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3309176736
Directory	/workspace/6.edn_regwen/latest

Test location	/workspace/coverage/default/6.edn_smoke.2380713269
Short name	T666
Test name
Test status
Simulation time	37682519 ps
CPU time	0.86 seconds
Started	Feb 07 12:48:00 PM PST 24
Finished	Feb 07 12:48:02 PM PST 24
Peak memory	215000 kb
Host	smart-e2abf95c-f4c8-4fcf-bbbf-8b823373bebd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2380713269 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2380713269
Directory	/workspace/6.edn_smoke/latest

Test location	/workspace/coverage/default/6.edn_stress_all.172900364
Short name	T426
Test name
Test status
Simulation time	165188850 ps
CPU time	1.93 seconds
Started	Feb 07 12:47:58 PM PST 24
Finished	Feb 07 12:48:01 PM PST 24
Peak memory	214968 kb
Host	smart-98e5f17d-f19e-48ed-9f2c-80bfdb3cb1d0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172900364 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.172900364
Directory	/workspace/6.edn_stress_all/latest

Test location	/workspace/coverage/default/6.edn_stress_all_with_rand_reset.1641097673
Short name	T481
Test name
Test status
Simulation time	122037457934 ps
CPU time	1552.63 seconds
Started	Feb 07 12:48:02 PM PST 24
Finished	Feb 07 01:13:56 PM PST 24
Peak memory	225616 kb
Host	smart-f3968c79-f5b5-4749-87c7-d9706dd43404
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641097673 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1641097673
Directory	/workspace/6.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/60.edn_err.3441510419
Short name	T664
Test name
Test status
Simulation time	31222425 ps
CPU time	1.03 seconds
Started	Feb 07 12:49:32 PM PST 24
Finished	Feb 07 12:49:35 PM PST 24
Peak memory	215688 kb
Host	smart-3fc854f7-d8ae-47e1-bad3-82453f544668
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3441510419 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3441510419
Directory	/workspace/60.edn_err/latest

Test location	/workspace/coverage/default/60.edn_genbits.1577272450
Short name	T564
Test name
Test status
Simulation time	28314791 ps
CPU time	1.23 seconds
Started	Feb 07 12:49:34 PM PST 24
Finished	Feb 07 12:49:37 PM PST 24
Peak memory	216864 kb
Host	smart-73f74c14-782c-4945-a1f1-efde0ef67478
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1577272450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1577272450
Directory	/workspace/60.edn_genbits/latest

Test location	/workspace/coverage/default/61.edn_err.976917594
Short name	T703
Test name
Test status
Simulation time	20642356 ps
CPU time	1.01 seconds
Started	Feb 07 12:49:34 PM PST 24
Finished	Feb 07 12:49:37 PM PST 24
Peak memory	222424 kb
Host	smart-8af0d6be-de33-4192-b193-e890c93a6df9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=976917594 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.976917594
Directory	/workspace/61.edn_err/latest

Test location	/workspace/coverage/default/61.edn_genbits.3678508335
Short name	T698
Test name
Test status
Simulation time	44445339 ps
CPU time	1.43 seconds
Started	Feb 07 12:49:27 PM PST 24
Finished	Feb 07 12:49:29 PM PST 24
Peak memory	217444 kb
Host	smart-7b80f8d4-6928-45f4-b40e-33941769f5dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3678508335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3678508335
Directory	/workspace/61.edn_genbits/latest

Test location	/workspace/coverage/default/62.edn_err.2830919619
Short name	T729
Test name
Test status
Simulation time	18837637 ps
CPU time	1.02 seconds
Started	Feb 07 12:49:27 PM PST 24
Finished	Feb 07 12:49:30 PM PST 24
Peak memory	216536 kb
Host	smart-2e1c1c74-11de-4980-af77-4d079fe4a558
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2830919619 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2830919619
Directory	/workspace/62.edn_err/latest

Test location	/workspace/coverage/default/62.edn_genbits.988492591
Short name	T34
Test name
Test status
Simulation time	149371537 ps
CPU time	1.35 seconds
Started	Feb 07 12:49:40 PM PST 24
Finished	Feb 07 12:49:45 PM PST 24
Peak memory	215524 kb
Host	smart-f2efb082-dc00-4d40-b5e0-a365a091aed1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=988492591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.988492591
Directory	/workspace/62.edn_genbits/latest

Test location	/workspace/coverage/default/63.edn_err.3174294528
Short name	T219
Test name
Test status
Simulation time	20206672 ps
CPU time	0.97 seconds
Started	Feb 07 12:49:33 PM PST 24
Finished	Feb 07 12:49:35 PM PST 24
Peak memory	216812 kb
Host	smart-9b813599-8a59-45a2-aacd-4811d415662b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3174294528 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3174294528
Directory	/workspace/63.edn_err/latest

Test location	/workspace/coverage/default/63.edn_genbits.883292738
Short name	T791
Test name
Test status
Simulation time	240895697 ps
CPU time	1.11 seconds
Started	Feb 07 12:49:30 PM PST 24
Finished	Feb 07 12:49:33 PM PST 24
Peak memory	215244 kb
Host	smart-785470fb-a0b0-490b-aa0e-095b7207b540
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=883292738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.883292738
Directory	/workspace/63.edn_genbits/latest

Test location	/workspace/coverage/default/64.edn_err.1309480117
Short name	T406
Test name
Test status
Simulation time	32969330 ps
CPU time	0.83 seconds
Started	Feb 07 12:49:33 PM PST 24
Finished	Feb 07 12:49:36 PM PST 24
Peak memory	216468 kb
Host	smart-34c463de-1db0-41c3-88ae-37d0e9fe3a5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1309480117 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1309480117
Directory	/workspace/64.edn_err/latest

Test location	/workspace/coverage/default/64.edn_genbits.2147444457
Short name	T652
Test name
Test status
Simulation time	96844462 ps
CPU time	1.16 seconds
Started	Feb 07 12:49:35 PM PST 24
Finished	Feb 07 12:49:38 PM PST 24
Peak memory	215516 kb
Host	smart-68d5097e-bb79-455c-9f4f-d43b43a780ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2147444457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2147444457
Directory	/workspace/64.edn_genbits/latest

Test location	/workspace/coverage/default/65.edn_err.3515438242
Short name	T455
Test name
Test status
Simulation time	32300971 ps
CPU time	1.11 seconds
Started	Feb 07 12:49:40 PM PST 24
Finished	Feb 07 12:49:45 PM PST 24
Peak memory	229372 kb
Host	smart-89052908-2110-4832-83db-04ce3ca563f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3515438242 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3515438242
Directory	/workspace/65.edn_err/latest

Test location	/workspace/coverage/default/65.edn_genbits.3613149397
Short name	T827
Test name
Test status
Simulation time	108898430 ps
CPU time	1.24 seconds
Started	Feb 07 12:49:42 PM PST 24
Finished	Feb 07 12:49:46 PM PST 24
Peak memory	215564 kb
Host	smart-633075fe-e0e7-49d3-af46-4d0c006be6cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3613149397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3613149397
Directory	/workspace/65.edn_genbits/latest

Test location	/workspace/coverage/default/66.edn_err.1709317643
Short name	T741
Test name
Test status
Simulation time	18945286 ps
CPU time	0.97 seconds
Started	Feb 07 12:49:37 PM PST 24
Finished	Feb 07 12:49:42 PM PST 24
Peak memory	216664 kb
Host	smart-9cc95b69-7b1f-45c7-8f3c-a2e5f0d7b75e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1709317643 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1709317643
Directory	/workspace/66.edn_err/latest

Test location	/workspace/coverage/default/66.edn_genbits.1240838068
Short name	T411
Test name
Test status
Simulation time	35334735 ps
CPU time	1.31 seconds
Started	Feb 07 12:49:40 PM PST 24
Finished	Feb 07 12:49:45 PM PST 24
Peak memory	215388 kb
Host	smart-d8a0d88d-8e09-4230-86ff-5b7bfc30598b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1240838068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1240838068
Directory	/workspace/66.edn_genbits/latest

Test location	/workspace/coverage/default/67.edn_err.3298189228
Short name	T402
Test name
Test status
Simulation time	34707869 ps
CPU time	1 seconds
Started	Feb 07 12:49:33 PM PST 24
Finished	Feb 07 12:49:35 PM PST 24
Peak memory	222436 kb
Host	smart-4ee89d71-feee-4ddf-ba1c-10da940f2541
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3298189228 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3298189228
Directory	/workspace/67.edn_err/latest

Test location	/workspace/coverage/default/67.edn_genbits.1230527424
Short name	T893
Test name
Test status
Simulation time	57862088 ps
CPU time	1.34 seconds
Started	Feb 07 12:49:33 PM PST 24
Finished	Feb 07 12:49:36 PM PST 24
Peak memory	216988 kb
Host	smart-4a6ecc91-f7c4-4886-80a2-cc9130bb8682
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1230527424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1230527424
Directory	/workspace/67.edn_genbits/latest

Test location	/workspace/coverage/default/68.edn_err.2080057617
Short name	T458
Test name
Test status
Simulation time	34768081 ps
CPU time	0.9 seconds
Started	Feb 07 12:49:39 PM PST 24
Finished	Feb 07 12:49:43 PM PST 24
Peak memory	215528 kb
Host	smart-fad77cf5-cef9-4a5a-9389-db57bb4581c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2080057617 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2080057617
Directory	/workspace/68.edn_err/latest

Test location	/workspace/coverage/default/68.edn_genbits.3849880263
Short name	T10
Test name
Test status
Simulation time	288182372 ps
CPU time	1.32 seconds
Started	Feb 07 12:49:40 PM PST 24
Finished	Feb 07 12:49:45 PM PST 24
Peak memory	215556 kb
Host	smart-8f4fd870-c476-494f-a5b2-14df54d235d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3849880263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3849880263
Directory	/workspace/68.edn_genbits/latest

Test location	/workspace/coverage/default/69.edn_err.115724730
Short name	T567
Test name
Test status
Simulation time	30473375 ps
CPU time	0.89 seconds
Started	Feb 07 12:49:34 PM PST 24
Finished	Feb 07 12:49:37 PM PST 24
Peak memory	216356 kb
Host	smart-7ebeb4aa-2d81-496d-b45d-e149bc16be32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=115724730 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.115724730
Directory	/workspace/69.edn_err/latest

Test location	/workspace/coverage/default/69.edn_genbits.1217134988
Short name	T737
Test name
Test status
Simulation time	36536754 ps
CPU time	1.33 seconds
Started	Feb 07 12:49:33 PM PST 24
Finished	Feb 07 12:49:36 PM PST 24
Peak memory	216536 kb
Host	smart-5af5cc57-2993-4249-b6b9-ffe69fcfa1fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1217134988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1217134988
Directory	/workspace/69.edn_genbits/latest

Test location	/workspace/coverage/default/7.edn_alert.2151193435
Short name	T626
Test name
Test status
Simulation time	36720213 ps
CPU time	0.97 seconds
Started	Feb 07 12:48:07 PM PST 24
Finished	Feb 07 12:48:09 PM PST 24
Peak memory	206036 kb
Host	smart-10e2fe25-14e4-47d4-9abd-c07d7a092477
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2151193435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2151193435
Directory	/workspace/7.edn_alert/latest

Test location	/workspace/coverage/default/7.edn_alert_test.4143413552
Short name	T599
Test name
Test status
Simulation time	50715607 ps
CPU time	1.45 seconds
Started	Feb 07 12:48:05 PM PST 24
Finished	Feb 07 12:48:07 PM PST 24
Peak memory	205420 kb
Host	smart-71343146-577e-4191-a6e3-63f9c14f857f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143413552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.4143413552
Directory	/workspace/7.edn_alert_test/latest

Test location	/workspace/coverage/default/7.edn_disable.2836157582
Short name	T467
Test name
Test status
Simulation time	26627497 ps
CPU time	0.88 seconds
Started	Feb 07 12:48:05 PM PST 24
Finished	Feb 07 12:48:07 PM PST 24
Peak memory	214928 kb
Host	smart-80201aeb-8fa3-4a90-bf3f-c856f9dd2686
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836157582 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2836157582
Directory	/workspace/7.edn_disable/latest

Test location	/workspace/coverage/default/7.edn_disable_auto_req_mode.1930155086
Short name	T440
Test name
Test status
Simulation time	96807065 ps
CPU time	1.08 seconds
Started	Feb 07 12:48:07 PM PST 24
Finished	Feb 07 12:48:09 PM PST 24
Peak memory	215328 kb
Host	smart-fcb60b49-c2e5-4a96-ae70-d1be56f9d9be
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930155086 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di sable_auto_req_mode.1930155086
Directory	/workspace/7.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/7.edn_err.4210340278
Short name	T470
Test name
Test status
Simulation time	24121900 ps
CPU time	0.91 seconds
Started	Feb 07 12:48:04 PM PST 24
Finished	Feb 07 12:48:06 PM PST 24
Peak memory	216700 kb
Host	smart-bd0801b0-3acf-45bf-83e7-d011f0eb9598
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4210340278 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.4210340278
Directory	/workspace/7.edn_err/latest

Test location	/workspace/coverage/default/7.edn_genbits.607763492
Short name	T519
Test name
Test status
Simulation time	41995762 ps
CPU time	1.58 seconds
Started	Feb 07 12:47:58 PM PST 24
Finished	Feb 07 12:48:00 PM PST 24
Peak memory	215424 kb
Host	smart-f6c5c3dd-26f0-4afa-8785-6251b62fce6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=607763492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.607763492
Directory	/workspace/7.edn_genbits/latest

Test location	/workspace/coverage/default/7.edn_intr.935576765
Short name	T445
Test name
Test status
Simulation time	36201279 ps
CPU time	1 seconds
Started	Feb 07 12:48:06 PM PST 24
Finished	Feb 07 12:48:08 PM PST 24
Peak memory	222692 kb
Host	smart-cb8a3093-c881-4c87-8920-0e01d7338266
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=935576765 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.935576765
Directory	/workspace/7.edn_intr/latest

Test location	/workspace/coverage/default/7.edn_regwen.741561325
Short name	T746
Test name
Test status
Simulation time	24371167 ps
CPU time	0.93 seconds
Started	Feb 07 12:47:58 PM PST 24
Finished	Feb 07 12:47:59 PM PST 24
Peak memory	206848 kb
Host	smart-5476eb11-b08d-4e2c-bfd4-6416e76515d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=741561325 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.741561325
Directory	/workspace/7.edn_regwen/latest

Test location	/workspace/coverage/default/7.edn_smoke.1449642166
Short name	T583
Test name
Test status
Simulation time	16584544 ps
CPU time	0.96 seconds
Started	Feb 07 12:47:57 PM PST 24
Finished	Feb 07 12:47:59 PM PST 24
Peak memory	214920 kb
Host	smart-5b4f60be-3d41-4043-85c3-fbe6647ab451
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1449642166 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1449642166
Directory	/workspace/7.edn_smoke/latest

Test location	/workspace/coverage/default/7.edn_stress_all.3060156814
Short name	T731
Test name
Test status
Simulation time	344637806 ps
CPU time	5.68 seconds
Started	Feb 07 12:48:02 PM PST 24
Finished	Feb 07 12:48:09 PM PST 24
Peak memory	215120 kb
Host	smart-f7a8dfa3-ae8e-4bcc-a4ea-e2f16fa2be12
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060156814 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3060156814
Directory	/workspace/7.edn_stress_all/latest

Test location	/workspace/coverage/default/7.edn_stress_all_with_rand_reset.3597692153
Short name	T759
Test name
Test status
Simulation time	170090688371 ps
CPU time	1884.79 seconds
Started	Feb 07 12:47:54 PM PST 24
Finished	Feb 07 01:19:20 PM PST 24
Peak memory	227376 kb
Host	smart-db296940-20c0-4945-b544-5da4012f0935
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597692153 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3597692153
Directory	/workspace/7.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/70.edn_err.3843150718
Short name	T811
Test name
Test status
Simulation time	30025586 ps
CPU time	0.96 seconds
Started	Feb 07 12:49:34 PM PST 24
Finished	Feb 07 12:49:37 PM PST 24
Peak memory	222440 kb
Host	smart-230552fa-828a-46b3-a66f-b95e056ec39a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3843150718 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3843150718
Directory	/workspace/70.edn_err/latest

Test location	/workspace/coverage/default/70.edn_genbits.3351964781
Short name	T796
Test name
Test status
Simulation time	149040777 ps
CPU time	1.05 seconds
Started	Feb 07 12:49:28 PM PST 24
Finished	Feb 07 12:49:30 PM PST 24
Peak memory	215536 kb
Host	smart-edeb8a3b-83f7-4da3-a3a5-d37925f7eace
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3351964781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3351964781
Directory	/workspace/70.edn_genbits/latest

Test location	/workspace/coverage/default/71.edn_err.2275715757
Short name	T739
Test name
Test status
Simulation time	28871057 ps
CPU time	1.29 seconds
Started	Feb 07 12:49:29 PM PST 24
Finished	Feb 07 12:49:32 PM PST 24
Peak memory	222560 kb
Host	smart-b83e3015-7cdf-40d1-896c-2604f7821f62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2275715757 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2275715757
Directory	/workspace/71.edn_err/latest

Test location	/workspace/coverage/default/71.edn_genbits.2128153477
Short name	T701
Test name
Test status
Simulation time	32001990 ps
CPU time	1.36 seconds
Started	Feb 07 12:49:31 PM PST 24
Finished	Feb 07 12:49:34 PM PST 24
Peak memory	215596 kb
Host	smart-d1e4c936-5686-453a-a2a3-c2391b791c6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2128153477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2128153477
Directory	/workspace/71.edn_genbits/latest

Test location	/workspace/coverage/default/72.edn_err.3284970016
Short name	T50
Test name
Test status
Simulation time	24160000 ps
CPU time	0.97 seconds
Started	Feb 07 12:49:34 PM PST 24
Finished	Feb 07 12:49:37 PM PST 24
Peak memory	222320 kb
Host	smart-b28361e3-c03c-4925-afe3-20f280509090
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3284970016 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3284970016
Directory	/workspace/72.edn_err/latest

Test location	/workspace/coverage/default/73.edn_err.1009705031
Short name	T514
Test name
Test status
Simulation time	50703462 ps
CPU time	0.98 seconds
Started	Feb 07 12:49:30 PM PST 24
Finished	Feb 07 12:49:33 PM PST 24
Peak memory	229276 kb
Host	smart-e9e61291-7c48-49a1-888e-2d1ef8c85ec2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1009705031 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1009705031
Directory	/workspace/73.edn_err/latest

Test location	/workspace/coverage/default/73.edn_genbits.2575148117
Short name	T394
Test name
Test status
Simulation time	54680192 ps
CPU time	1.29 seconds
Started	Feb 07 12:49:34 PM PST 24
Finished	Feb 07 12:49:37 PM PST 24
Peak memory	215332 kb
Host	smart-1eaa145b-3f41-40d4-9a38-896f7d88dec3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2575148117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2575148117
Directory	/workspace/73.edn_genbits/latest

Test location	/workspace/coverage/default/74.edn_err.4095725723
Short name	T640
Test name
Test status
Simulation time	18492530 ps
CPU time	1.01 seconds
Started	Feb 07 12:49:31 PM PST 24
Finished	Feb 07 12:49:33 PM PST 24
Peak memory	216428 kb
Host	smart-e5683983-fd74-4973-8aa8-4e9fc149b05c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4095725723 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.4095725723
Directory	/workspace/74.edn_err/latest

Test location	/workspace/coverage/default/74.edn_genbits.1605686583
Short name	T884
Test name
Test status
Simulation time	319716759 ps
CPU time	1.11 seconds
Started	Feb 07 12:49:30 PM PST 24
Finished	Feb 07 12:49:32 PM PST 24
Peak memory	215416 kb
Host	smart-f39ead08-df5f-4a73-a18f-0cffaf6c1bdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1605686583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1605686583
Directory	/workspace/74.edn_genbits/latest

Test location	/workspace/coverage/default/75.edn_err.2127682809
Short name	T561
Test name
Test status
Simulation time	22040629 ps
CPU time	0.95 seconds
Started	Feb 07 12:49:40 PM PST 24
Finished	Feb 07 12:49:45 PM PST 24
Peak memory	216956 kb
Host	smart-7308f137-6fe6-499e-b63a-2ad64757e898
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2127682809 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2127682809
Directory	/workspace/75.edn_err/latest

Test location	/workspace/coverage/default/75.edn_genbits.54466207
Short name	T610
Test name
Test status
Simulation time	38533055 ps
CPU time	1.38 seconds
Started	Feb 07 12:49:28 PM PST 24
Finished	Feb 07 12:49:31 PM PST 24
Peak memory	215316 kb
Host	smart-e3c399fc-2522-4f42-9917-d16b190b5583
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54466207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.54466207
Directory	/workspace/75.edn_genbits/latest

Test location	/workspace/coverage/default/76.edn_err.2986691198
Short name	T485
Test name
Test status
Simulation time	34255584 ps
CPU time	1.05 seconds
Started	Feb 07 12:49:33 PM PST 24
Finished	Feb 07 12:49:36 PM PST 24
Peak memory	215768 kb
Host	smart-115f29c5-9448-40fd-9e1c-1571e59a54f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2986691198 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2986691198
Directory	/workspace/76.edn_err/latest

Test location	/workspace/coverage/default/76.edn_genbits.3380017157
Short name	T669
Test name
Test status
Simulation time	52452515 ps
CPU time	1.19 seconds
Started	Feb 07 12:49:43 PM PST 24
Finished	Feb 07 12:49:46 PM PST 24
Peak memory	215348 kb
Host	smart-6b518a4d-ba89-4a79-b512-5e16c74fc06e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3380017157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3380017157
Directory	/workspace/76.edn_genbits/latest

Test location	/workspace/coverage/default/77.edn_genbits.563192085
Short name	T472
Test name
Test status
Simulation time	57986272 ps
CPU time	1.3 seconds
Started	Feb 07 12:49:33 PM PST 24
Finished	Feb 07 12:49:35 PM PST 24
Peak memory	215432 kb
Host	smart-be716d2c-2a24-494b-b119-a1df89085658
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=563192085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.563192085
Directory	/workspace/77.edn_genbits/latest

Test location	/workspace/coverage/default/78.edn_err.3550250642
Short name	T945
Test name
Test status
Simulation time	21349805 ps
CPU time	0.98 seconds
Started	Feb 07 12:49:39 PM PST 24
Finished	Feb 07 12:49:42 PM PST 24
Peak memory	216868 kb
Host	smart-b0b00301-a407-4562-8e95-6688ec53f722
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550250642 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3550250642
Directory	/workspace/78.edn_err/latest

Test location	/workspace/coverage/default/78.edn_genbits.1878236163
Short name	T895
Test name
Test status
Simulation time	73388317 ps
CPU time	1.05 seconds
Started	Feb 07 12:49:36 PM PST 24
Finished	Feb 07 12:49:40 PM PST 24
Peak memory	215536 kb
Host	smart-529cce59-9df5-40d2-aaf1-017c00e73751
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1878236163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1878236163
Directory	/workspace/78.edn_genbits/latest

Test location	/workspace/coverage/default/79.edn_err.1042342641
Short name	T373
Test name
Test status
Simulation time	22431826 ps
CPU time	0.94 seconds
Started	Feb 07 12:49:38 PM PST 24
Finished	Feb 07 12:49:42 PM PST 24
Peak memory	222372 kb
Host	smart-6adc1e63-f0f8-42c5-b35b-8a931bda4008
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1042342641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1042342641
Directory	/workspace/79.edn_err/latest

Test location	/workspace/coverage/default/79.edn_genbits.3451227007
Short name	T424
Test name
Test status
Simulation time	44074375 ps
CPU time	1.69 seconds
Started	Feb 07 12:49:34 PM PST 24
Finished	Feb 07 12:49:38 PM PST 24
Peak memory	215480 kb
Host	smart-d757eb86-afac-4346-85cc-1c9df7ae3b39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3451227007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3451227007
Directory	/workspace/79.edn_genbits/latest

Test location	/workspace/coverage/default/8.edn_alert.3135803574
Short name	T864
Test name
Test status
Simulation time	21248096 ps
CPU time	1.05 seconds
Started	Feb 07 12:48:04 PM PST 24
Finished	Feb 07 12:48:06 PM PST 24
Peak memory	206112 kb
Host	smart-51798122-9793-4219-bf3e-3890a6df989d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3135803574 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3135803574
Directory	/workspace/8.edn_alert/latest

Test location	/workspace/coverage/default/8.edn_alert_test.1463788216
Short name	T784
Test name
Test status
Simulation time	46659070 ps
CPU time	1.36 seconds
Started	Feb 07 12:48:02 PM PST 24
Finished	Feb 07 12:48:04 PM PST 24
Peak memory	205900 kb
Host	smart-61fd2464-d36c-4b7c-9027-d1a440eec97e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463788216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1463788216
Directory	/workspace/8.edn_alert_test/latest

Test location	/workspace/coverage/default/8.edn_disable.2821015017
Short name	T935
Test name
Test status
Simulation time	17971718 ps
CPU time	0.88 seconds
Started	Feb 07 12:48:06 PM PST 24
Finished	Feb 07 12:48:08 PM PST 24
Peak memory	215048 kb
Host	smart-7f35cbe0-8516-4525-82a1-e41edd4e77ec
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821015017 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2821015017
Directory	/workspace/8.edn_disable/latest

Test location	/workspace/coverage/default/8.edn_disable_auto_req_mode.1504314321
Short name	T40
Test name
Test status
Simulation time	76056703 ps
CPU time	1.1 seconds
Started	Feb 07 12:48:03 PM PST 24
Finished	Feb 07 12:48:05 PM PST 24
Peak memory	215272 kb
Host	smart-e2a0738e-6119-4c06-8ab1-d0a83da74ae1
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504314321 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di sable_auto_req_mode.1504314321
Directory	/workspace/8.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/8.edn_err.889731756
Short name	T637
Test name
Test status
Simulation time	25026349 ps
CPU time	1.18 seconds
Started	Feb 07 12:48:04 PM PST 24
Finished	Feb 07 12:48:06 PM PST 24
Peak memory	215588 kb
Host	smart-63a98719-0794-4457-ab2c-22a3790f1962
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=889731756 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.889731756
Directory	/workspace/8.edn_err/latest

Test location	/workspace/coverage/default/8.edn_genbits.2170048953
Short name	T396
Test name
Test status
Simulation time	71836446 ps
CPU time	1.01 seconds
Started	Feb 07 12:48:05 PM PST 24
Finished	Feb 07 12:48:07 PM PST 24
Peak memory	215284 kb
Host	smart-2e5df735-ffe0-4b7b-b9ea-bf9331ee4322
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2170048953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2170048953
Directory	/workspace/8.edn_genbits/latest

Test location	/workspace/coverage/default/8.edn_intr.2758273841
Short name	T63
Test name
Test status
Simulation time	30694914 ps
CPU time	0.89 seconds
Started	Feb 07 12:48:21 PM PST 24
Finished	Feb 07 12:48:27 PM PST 24
Peak memory	214960 kb
Host	smart-6ebbf102-2804-4cfb-8035-1b79f9a06ad8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758273841 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2758273841
Directory	/workspace/8.edn_intr/latest

Test location	/workspace/coverage/default/8.edn_regwen.2671155757
Short name	T230
Test name
Test status
Simulation time	16974746 ps
CPU time	0.98 seconds
Started	Feb 07 12:48:03 PM PST 24
Finished	Feb 07 12:48:05 PM PST 24
Peak memory	206836 kb
Host	smart-89eddc18-adb9-4f8b-b7b4-75a75b9642d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2671155757 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2671155757
Directory	/workspace/8.edn_regwen/latest

Test location	/workspace/coverage/default/8.edn_smoke.414723638
Short name	T523
Test name
Test status
Simulation time	16784854 ps
CPU time	0.95 seconds
Started	Feb 07 12:48:07 PM PST 24
Finished	Feb 07 12:48:09 PM PST 24
Peak memory	214980 kb
Host	smart-93fde996-2a4e-42d6-8942-89456019e550
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=414723638 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.414723638
Directory	/workspace/8.edn_smoke/latest

Test location	/workspace/coverage/default/8.edn_stress_all.1357215325
Short name	T605
Test name
Test status
Simulation time	388415809 ps
CPU time	7.34 seconds
Started	Feb 07 12:48:02 PM PST 24
Finished	Feb 07 12:48:11 PM PST 24
Peak memory	218360 kb
Host	smart-26324d07-527c-4555-8290-5dcca87dd64c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357215325 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1357215325
Directory	/workspace/8.edn_stress_all/latest

Test location	/workspace/coverage/default/8.edn_stress_all_with_rand_reset.539976481
Short name	T436
Test name
Test status
Simulation time	40599316817 ps
CPU time	953.77 seconds
Started	Feb 07 12:48:04 PM PST 24
Finished	Feb 07 01:03:58 PM PST 24
Peak memory	217732 kb
Host	smart-335c4ea4-f5b6-44cc-a220-c6237dd750fa
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539976481 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.539976481
Directory	/workspace/8.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/80.edn_err.3682026667
Short name	T943
Test name
Test status
Simulation time	53489464 ps
CPU time	1.04 seconds
Started	Feb 07 12:49:39 PM PST 24
Finished	Feb 07 12:49:43 PM PST 24
Peak memory	229400 kb
Host	smart-20ff2035-85b9-402e-bfa2-e9841d80d745
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3682026667 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3682026667
Directory	/workspace/80.edn_err/latest

Test location	/workspace/coverage/default/80.edn_genbits.1044732798
Short name	T578
Test name
Test status
Simulation time	191624105 ps
CPU time	1.79 seconds
Started	Feb 07 12:49:32 PM PST 24
Finished	Feb 07 12:49:35 PM PST 24
Peak memory	216812 kb
Host	smart-90c2c12e-70fa-41d8-a164-9036d7df0090
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1044732798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1044732798
Directory	/workspace/80.edn_genbits/latest

Test location	/workspace/coverage/default/81.edn_err.3967263357
Short name	T620
Test name
Test status
Simulation time	25221116 ps
CPU time	1.18 seconds
Started	Feb 07 12:49:33 PM PST 24
Finished	Feb 07 12:49:36 PM PST 24
Peak memory	222496 kb
Host	smart-ad67ea8f-2c89-45af-87e0-01ba25a94c38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3967263357 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3967263357
Directory	/workspace/81.edn_err/latest

Test location	/workspace/coverage/default/81.edn_genbits.1921186750
Short name	T401
Test name
Test status
Simulation time	120468686 ps
CPU time	1.18 seconds
Started	Feb 07 12:49:36 PM PST 24
Finished	Feb 07 12:49:40 PM PST 24
Peak memory	215292 kb
Host	smart-d5f8f7eb-782e-4f16-8bb4-ed5f8f0ca989
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1921186750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1921186750
Directory	/workspace/81.edn_genbits/latest

Test location	/workspace/coverage/default/82.edn_err.1212563995
Short name	T758
Test name
Test status
Simulation time	20624120 ps
CPU time	1.18 seconds
Started	Feb 07 12:49:40 PM PST 24
Finished	Feb 07 12:49:45 PM PST 24
Peak memory	229232 kb
Host	smart-1aac9b84-3289-47be-8969-71cd2984be55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1212563995 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1212563995
Directory	/workspace/82.edn_err/latest

Test location	/workspace/coverage/default/82.edn_genbits.4244869564
Short name	T41
Test name
Test status
Simulation time	464399815 ps
CPU time	3.85 seconds
Started	Feb 07 12:49:34 PM PST 24
Finished	Feb 07 12:49:40 PM PST 24
Peak memory	215648 kb
Host	smart-ac191f9b-79a4-4e73-8eaf-983c71a15568
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4244869564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.4244869564
Directory	/workspace/82.edn_genbits/latest

Test location	/workspace/coverage/default/83.edn_err.603219212
Short name	T380
Test name
Test status
Simulation time	41771618 ps
CPU time	1.03 seconds
Started	Feb 07 12:49:31 PM PST 24
Finished	Feb 07 12:49:34 PM PST 24
Peak memory	217668 kb
Host	smart-f1a13140-c1b0-40ff-9e81-a936594b28d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=603219212 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.603219212
Directory	/workspace/83.edn_err/latest

Test location	/workspace/coverage/default/83.edn_genbits.3018628436
Short name	T726
Test name
Test status
Simulation time	73749134 ps
CPU time	1.42 seconds
Started	Feb 07 12:49:39 PM PST 24
Finished	Feb 07 12:49:43 PM PST 24
Peak memory	215376 kb
Host	smart-903c658b-53a3-4ece-93bb-1df6ac5ecb41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3018628436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3018628436
Directory	/workspace/83.edn_genbits/latest

Test location	/workspace/coverage/default/84.edn_err.4130526313
Short name	T936
Test name
Test status
Simulation time	127465918 ps
CPU time	1.16 seconds
Started	Feb 07 12:49:39 PM PST 24
Finished	Feb 07 12:49:43 PM PST 24
Peak memory	222584 kb
Host	smart-8ae9d321-5f64-40a5-b39a-1fb7138097b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4130526313 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.4130526313
Directory	/workspace/84.edn_err/latest

Test location	/workspace/coverage/default/84.edn_genbits.3390540666
Short name	T752
Test name
Test status
Simulation time	84799804 ps
CPU time	1.08 seconds
Started	Feb 07 12:49:39 PM PST 24
Finished	Feb 07 12:49:42 PM PST 24
Peak memory	215564 kb
Host	smart-0bc1857d-5dd9-4f41-aab5-e4e147dc6493
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3390540666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3390540666
Directory	/workspace/84.edn_genbits/latest

Test location	/workspace/coverage/default/85.edn_err.2698938762
Short name	T754
Test name
Test status
Simulation time	56460301 ps
CPU time	0.86 seconds
Started	Feb 07 12:49:34 PM PST 24
Finished	Feb 07 12:49:37 PM PST 24
Peak memory	215252 kb
Host	smart-04a463b1-2471-44de-91e7-ff5a79707327
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2698938762 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2698938762
Directory	/workspace/85.edn_err/latest

Test location	/workspace/coverage/default/86.edn_err.1897981867
Short name	T612
Test name
Test status
Simulation time	22603108 ps
CPU time	0.94 seconds
Started	Feb 07 12:49:39 PM PST 24
Finished	Feb 07 12:49:43 PM PST 24
Peak memory	216664 kb
Host	smart-34ba19c6-e150-445c-a342-dca09a5a3012
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1897981867 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1897981867
Directory	/workspace/86.edn_err/latest

Test location	/workspace/coverage/default/86.edn_genbits.2723256900
Short name	T465
Test name
Test status
Simulation time	32691873 ps
CPU time	1.05 seconds
Started	Feb 07 12:49:29 PM PST 24
Finished	Feb 07 12:49:32 PM PST 24
Peak memory	215444 kb
Host	smart-cdaaca6c-6fae-4ab0-8709-07c565c6bf1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2723256900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2723256900
Directory	/workspace/86.edn_genbits/latest

Test location	/workspace/coverage/default/87.edn_err.3363333001
Short name	T372
Test name
Test status
Simulation time	20980356 ps
CPU time	1.14 seconds
Started	Feb 07 12:49:36 PM PST 24
Finished	Feb 07 12:49:40 PM PST 24
Peak memory	215348 kb
Host	smart-93c7bea5-90f8-4acc-94dd-578b6f71a11b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363333001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3363333001
Directory	/workspace/87.edn_err/latest

Test location	/workspace/coverage/default/87.edn_genbits.2885841027
Short name	T576
Test name
Test status
Simulation time	118303519 ps
CPU time	1.06 seconds
Started	Feb 07 12:49:43 PM PST 24
Finished	Feb 07 12:49:46 PM PST 24
Peak memory	215336 kb
Host	smart-a19e4de9-3c65-406e-bffb-1532f86f563d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2885841027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2885841027
Directory	/workspace/87.edn_genbits/latest

Test location	/workspace/coverage/default/88.edn_err.2208937842
Short name	T847
Test name
Test status
Simulation time	18503239 ps
CPU time	1.09 seconds
Started	Feb 07 12:49:38 PM PST 24
Finished	Feb 07 12:49:42 PM PST 24
Peak memory	216628 kb
Host	smart-1be51440-5217-4047-828a-3bd905511757
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2208937842 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2208937842
Directory	/workspace/88.edn_err/latest

Test location	/workspace/coverage/default/88.edn_genbits.627685962
Short name	T694
Test name
Test status
Simulation time	86535835 ps
CPU time	1.16 seconds
Started	Feb 07 12:49:33 PM PST 24
Finished	Feb 07 12:49:36 PM PST 24
Peak memory	215616 kb
Host	smart-c5d9e688-01c6-43d4-b7d9-a25247f3d9b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=627685962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.627685962
Directory	/workspace/88.edn_genbits/latest

Test location	/workspace/coverage/default/89.edn_err.2112674726
Short name	T750
Test name
Test status
Simulation time	68108682 ps
CPU time	1.05 seconds
Started	Feb 07 12:49:36 PM PST 24
Finished	Feb 07 12:49:40 PM PST 24
Peak memory	218112 kb
Host	smart-4f1622a3-4ac5-4d4f-a7cc-47180e3e848d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2112674726 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2112674726
Directory	/workspace/89.edn_err/latest

Test location	/workspace/coverage/default/89.edn_genbits.3510889502
Short name	T351
Test name
Test status
Simulation time	45081760 ps
CPU time	1.5 seconds
Started	Feb 07 12:49:43 PM PST 24
Finished	Feb 07 12:49:46 PM PST 24
Peak memory	218188 kb
Host	smart-413e5efc-776b-487e-90a9-b0d9c6fa18d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3510889502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3510889502
Directory	/workspace/89.edn_genbits/latest

Test location	/workspace/coverage/default/9.edn_alert.4250300810
Short name	T234
Test name
Test status
Simulation time	32530218 ps
CPU time	1.04 seconds
Started	Feb 07 12:48:10 PM PST 24
Finished	Feb 07 12:48:12 PM PST 24
Peak memory	206000 kb
Host	smart-74d22ff5-b23d-4897-b68f-69664e649350
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4250300810 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.4250300810
Directory	/workspace/9.edn_alert/latest

Test location	/workspace/coverage/default/9.edn_alert_test.2482111003
Short name	T707
Test name
Test status
Simulation time	13521883 ps
CPU time	0.92 seconds
Started	Feb 07 12:48:04 PM PST 24
Finished	Feb 07 12:48:05 PM PST 24
Peak memory	205304 kb
Host	smart-05c25b3e-d546-4028-be58-85561e57a458
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482111003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2482111003
Directory	/workspace/9.edn_alert_test/latest

Test location	/workspace/coverage/default/9.edn_disable.2558193787
Short name	T508
Test name
Test status
Simulation time	16617727 ps
CPU time	0.91 seconds
Started	Feb 07 12:48:06 PM PST 24
Finished	Feb 07 12:48:08 PM PST 24
Peak memory	215216 kb
Host	smart-8bd2177d-9b2f-4d0e-8b75-c6a06743203f
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558193787 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2558193787
Directory	/workspace/9.edn_disable/latest

Test location	/workspace/coverage/default/9.edn_err.771466723
Short name	T503
Test name
Test status
Simulation time	21384450 ps
CPU time	0.91 seconds
Started	Feb 07 12:48:10 PM PST 24
Finished	Feb 07 12:48:12 PM PST 24
Peak memory	216532 kb
Host	smart-51bcec68-d5db-44bd-a7d7-0ebb28a4c6ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=771466723 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.771466723
Directory	/workspace/9.edn_err/latest

Test location	/workspace/coverage/default/9.edn_genbits.1818444949
Short name	T950
Test name
Test status
Simulation time	64840481 ps
CPU time	2.55 seconds
Started	Feb 07 12:48:08 PM PST 24
Finished	Feb 07 12:48:12 PM PST 24
Peak memory	216548 kb
Host	smart-299f5b32-5382-4bf4-9ad5-3e665a03589a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1818444949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1818444949
Directory	/workspace/9.edn_genbits/latest

Test location	/workspace/coverage/default/9.edn_intr.1697092025
Short name	T581
Test name
Test status
Simulation time	28284578 ps
CPU time	0.98 seconds
Started	Feb 07 12:48:08 PM PST 24
Finished	Feb 07 12:48:10 PM PST 24
Peak memory	214988 kb
Host	smart-51580108-6e73-4309-9cc0-7f7e3f99036b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1697092025 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1697092025
Directory	/workspace/9.edn_intr/latest

Test location	/workspace/coverage/default/9.edn_regwen.3522792835
Short name	T168
Test name
Test status
Simulation time	15902485 ps
CPU time	0.96 seconds
Started	Feb 07 12:48:05 PM PST 24
Finished	Feb 07 12:48:07 PM PST 24
Peak memory	206716 kb
Host	smart-0ae09ac6-5ecd-49ce-8424-ea957ab8b6f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3522792835 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3522792835
Directory	/workspace/9.edn_regwen/latest

Test location	/workspace/coverage/default/9.edn_smoke.1275201121
Short name	T800
Test name
Test status
Simulation time	192789815 ps
CPU time	0.92 seconds
Started	Feb 07 12:48:17 PM PST 24
Finished	Feb 07 12:48:19 PM PST 24
Peak memory	214476 kb
Host	smart-d01e06a1-c8a4-4b7d-840b-c9e0869281ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1275201121 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1275201121
Directory	/workspace/9.edn_smoke/latest

Test location	/workspace/coverage/default/9.edn_stress_all.2615804748
Short name	T81
Test name
Test status
Simulation time	364664742 ps
CPU time	6.7 seconds
Started	Feb 07 12:48:03 PM PST 24
Finished	Feb 07 12:48:10 PM PST 24
Peak memory	216552 kb
Host	smart-80d9f317-10a5-40d6-b4da-48bb196651d1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615804748 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2615804748
Directory	/workspace/9.edn_stress_all/latest

Test location	/workspace/coverage/default/9.edn_stress_all_with_rand_reset.1378587647
Short name	T506
Test name
Test status
Simulation time	147937501466 ps
CPU time	2702.52 seconds
Started	Feb 07 12:48:03 PM PST 24
Finished	Feb 07 01:33:07 PM PST 24
Peak memory	231240 kb
Host	smart-90004e81-433a-4523-b3b0-383840ac7382
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378587647 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.1378587647
Directory	/workspace/9.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/90.edn_err.883090814
Short name	T733
Test name
Test status
Simulation time	20441272 ps
CPU time	1.14 seconds
Started	Feb 07 12:49:38 PM PST 24
Finished	Feb 07 12:49:43 PM PST 24
Peak memory	215492 kb
Host	smart-8a8bef01-2f2d-4ec7-b062-5ab24457b619
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=883090814 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.883090814
Directory	/workspace/90.edn_err/latest

Test location	/workspace/coverage/default/90.edn_genbits.2572305264
Short name	T691
Test name
Test status
Simulation time	40489836 ps
CPU time	1.22 seconds
Started	Feb 07 12:49:36 PM PST 24
Finished	Feb 07 12:49:40 PM PST 24
Peak memory	218012 kb
Host	smart-a470175e-de4a-42ab-b295-a5a1751a841f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2572305264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2572305264
Directory	/workspace/90.edn_genbits/latest

Test location	/workspace/coverage/default/91.edn_err.2940222608
Short name	T649
Test name
Test status
Simulation time	19428337 ps
CPU time	1 seconds
Started	Feb 07 12:49:36 PM PST 24
Finished	Feb 07 12:49:40 PM PST 24
Peak memory	216772 kb
Host	smart-7a0ccb79-44be-45ee-9c40-c4342cbc782f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2940222608 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2940222608
Directory	/workspace/91.edn_err/latest

Test location	/workspace/coverage/default/91.edn_genbits.3257536328
Short name	T765
Test name
Test status
Simulation time	76137741 ps
CPU time	1.06 seconds
Started	Feb 07 12:49:43 PM PST 24
Finished	Feb 07 12:49:46 PM PST 24
Peak memory	215540 kb
Host	smart-899dba2d-51ef-495a-b345-c3d71aa78742
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3257536328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3257536328
Directory	/workspace/91.edn_genbits/latest

Test location	/workspace/coverage/default/92.edn_err.1092760430
Short name	T374
Test name
Test status
Simulation time	29525204 ps
CPU time	1.22 seconds
Started	Feb 07 12:49:32 PM PST 24
Finished	Feb 07 12:49:34 PM PST 24
Peak memory	217736 kb
Host	smart-25febb53-d1fa-4054-ab39-c1a74c640464
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1092760430 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1092760430
Directory	/workspace/92.edn_err/latest

Test location	/workspace/coverage/default/92.edn_genbits.2609814855
Short name	T913
Test name
Test status
Simulation time	256276126 ps
CPU time	3.35 seconds
Started	Feb 07 12:49:39 PM PST 24
Finished	Feb 07 12:49:45 PM PST 24
Peak memory	216784 kb
Host	smart-7864efd5-2a81-4f61-a825-42ca1e15d0ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2609814855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2609814855
Directory	/workspace/92.edn_genbits/latest

Test location	/workspace/coverage/default/93.edn_err.3874793047
Short name	T502
Test name
Test status
Simulation time	22390106 ps
CPU time	0.87 seconds
Started	Feb 07 12:49:36 PM PST 24
Finished	Feb 07 12:49:40 PM PST 24
Peak memory	216704 kb
Host	smart-ce1937e9-038b-4f54-a255-a2e13f589c1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3874793047 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3874793047
Directory	/workspace/93.edn_err/latest

Test location	/workspace/coverage/default/93.edn_genbits.310344576
Short name	T598
Test name
Test status
Simulation time	93522923 ps
CPU time	1.2 seconds
Started	Feb 07 12:49:42 PM PST 24
Finished	Feb 07 12:49:46 PM PST 24
Peak memory	215344 kb
Host	smart-a2ed8e8c-2e75-45f7-aacb-ad69000d22e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=310344576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.310344576
Directory	/workspace/93.edn_genbits/latest

Test location	/workspace/coverage/default/94.edn_err.1874341628
Short name	T5
Test name
Test status
Simulation time	36311953 ps
CPU time	1.08 seconds
Started	Feb 07 12:49:44 PM PST 24
Finished	Feb 07 12:49:47 PM PST 24
Peak memory	229312 kb
Host	smart-fe49d642-cc77-46dc-989f-4379ef3524a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1874341628 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1874341628
Directory	/workspace/94.edn_err/latest

Test location	/workspace/coverage/default/94.edn_genbits.1390545205
Short name	T929
Test name
Test status
Simulation time	41182825 ps
CPU time	1.15 seconds
Started	Feb 07 12:49:26 PM PST 24
Finished	Feb 07 12:49:28 PM PST 24
Peak memory	215624 kb
Host	smart-264111db-2095-4420-907b-0ae1f67dde22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1390545205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1390545205
Directory	/workspace/94.edn_genbits/latest

Test location	/workspace/coverage/default/95.edn_err.759657495
Short name	T769
Test name
Test status
Simulation time	28979412 ps
CPU time	1.15 seconds
Started	Feb 07 12:49:28 PM PST 24
Finished	Feb 07 12:49:30 PM PST 24
Peak memory	217988 kb
Host	smart-e3cba8d7-eaa3-4ec4-9cd6-2c7b4ffe06bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=759657495 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.759657495
Directory	/workspace/95.edn_err/latest

Test location	/workspace/coverage/default/95.edn_genbits.2397105375
Short name	T802
Test name
Test status
Simulation time	229503760 ps
CPU time	2.23 seconds
Started	Feb 07 12:49:26 PM PST 24
Finished	Feb 07 12:49:29 PM PST 24
Peak memory	215852 kb
Host	smart-d361f67a-f67e-4336-b10e-8be00a7c9edd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2397105375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2397105375
Directory	/workspace/95.edn_genbits/latest

Test location	/workspace/coverage/default/96.edn_err.1763935930
Short name	T678
Test name
Test status
Simulation time	23397274 ps
CPU time	0.94 seconds
Started	Feb 07 12:49:39 PM PST 24
Finished	Feb 07 12:49:42 PM PST 24
Peak memory	215192 kb
Host	smart-3c1210aa-4e5f-41d4-833c-f990e40bdfb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1763935930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1763935930
Directory	/workspace/96.edn_err/latest

Test location	/workspace/coverage/default/96.edn_genbits.70511380
Short name	T183
Test name
Test status
Simulation time	38302259 ps
CPU time	1.1 seconds
Started	Feb 07 12:49:26 PM PST 24
Finished	Feb 07 12:49:29 PM PST 24
Peak memory	215204 kb
Host	smart-4f151402-f0dd-4e96-b13a-195ae4465cf4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=70511380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.70511380
Directory	/workspace/96.edn_genbits/latest

Test location	/workspace/coverage/default/97.edn_err.499594200
Short name	T654
Test name
Test status
Simulation time	20752758 ps
CPU time	0.89 seconds
Started	Feb 07 12:49:40 PM PST 24
Finished	Feb 07 12:49:45 PM PST 24
Peak memory	216652 kb
Host	smart-54e07471-921b-4f7f-b689-b1af62afa6d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=499594200 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.499594200
Directory	/workspace/97.edn_err/latest

Test location	/workspace/coverage/default/97.edn_genbits.21808745
Short name	T706
Test name
Test status
Simulation time	62611217 ps
CPU time	2.04 seconds
Started	Feb 07 12:49:31 PM PST 24
Finished	Feb 07 12:49:35 PM PST 24
Peak memory	216680 kb
Host	smart-11db9604-4a2d-48fd-a05e-8009e9f81e92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21808745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.21808745
Directory	/workspace/97.edn_genbits/latest

Test location	/workspace/coverage/default/98.edn_err.310677011
Short name	T408
Test name
Test status
Simulation time	19363407 ps
CPU time	1.23 seconds
Started	Feb 07 12:49:26 PM PST 24
Finished	Feb 07 12:49:29 PM PST 24
Peak memory	222556 kb
Host	smart-3455eebb-9ee8-4cfd-89b8-1441b99c5ab0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=310677011 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.310677011
Directory	/workspace/98.edn_err/latest

Test location	/workspace/coverage/default/98.edn_genbits.3737809275
Short name	T941
Test name
Test status
Simulation time	32558981 ps
CPU time	1.26 seconds
Started	Feb 07 12:49:31 PM PST 24
Finished	Feb 07 12:49:34 PM PST 24
Peak memory	215632 kb
Host	smart-bfcc0bd0-c0b2-4e1c-8c9e-a432f06058b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3737809275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3737809275
Directory	/workspace/98.edn_genbits/latest

Test location	/workspace/coverage/default/99.edn_err.1449731928
Short name	T627
Test name
Test status
Simulation time	29831783 ps
CPU time	1.33 seconds
Started	Feb 07 12:49:37 PM PST 24
Finished	Feb 07 12:49:41 PM PST 24
Peak memory	222672 kb
Host	smart-2c8f9fac-14a9-408c-aa6b-29cd43eb72ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1449731928 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1449731928
Directory	/workspace/99.edn_err/latest

Test location	/workspace/coverage/default/99.edn_genbits.1818111022
Short name	T714
Test name
Test status
Simulation time	330907586 ps
CPU time	3.45 seconds
Started	Feb 07 12:49:33 PM PST 24
Finished	Feb 07 12:49:38 PM PST 24
Peak memory	215812 kb
Host	smart-f778ccf8-f5c7-47b9-a9a5-ec82603b0c02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1818111022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1818111022
Directory	/workspace/99.edn_genbits/latest