Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.94	93.94	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	93.94	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.94	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	2	19	90.48

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	2	19	90.48	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	136	1			T2	1		T19	1		T25	1
auto_req_mode	137	1			T13	1		T9	1		T56	1
sw_mode	2738	1			T4	6		T35	5		T155	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

296

1

T2

1

T13

1

T25

1

single

92

1

T19

1

T21

1

T178

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1195	1			T35	5		T21	1		T9	1
auto[2]	192	1			T263	1		T264	1		T265	1
auto[3]	92	1			T266	1		T267	5		T268	1
auto[4]	221	1			T269	1		T270	1		T271	1
auto[5]	54	1			T208	1		T193	40		T272	1
auto[6]	211	1			T178	1		T197	1		T257	1
auto[7]	1046	1			T2	1		T19	1		T4	6

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	2	19	90.48	2

Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	NUMBER	STATUS
[auto[2]]	[boot_req_mode]	0	1	1
[auto[6]]	[auto_req_mode]	0	1	1

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	85	1			T21	1		T145	1		T179	1
auto[1]	auto_req_mode	73	1			T9	1		T56	1		T132	1
auto[1]	sw_mode	1037	1			T35	5		T155	1		T22	43
auto[2]	auto_req_mode	3	1			T264	1		T265	1		T273	1
auto[2]	sw_mode	189	1			T263	1		T198	28		T274	72
auto[3]	boot_req_mode	6	1			T275	1		T276	1		T277	1
auto[3]	auto_req_mode	6	1			T278	1		T279	1		T280	1
auto[3]	sw_mode	80	1			T266	1		T267	5		T268	1
auto[4]	boot_req_mode	3	1			T270	1		T281	1		T282	1
auto[4]	auto_req_mode	4	1			T271	1		T283	1		T284	1
auto[4]	sw_mode	214	1			T269	1		T285	9		T286	39
auto[5]	boot_req_mode	4	1			T272	1		T287	1		T288	1
auto[5]	auto_req_mode	3	1			T208	1		T289	1		T290	1
auto[5]	sw_mode	47	1			T193	40		T291	1		T292	1
auto[6]	boot_req_mode	4	1			T197	1		T257	1		T293	1
auto[6]	sw_mode	207	1			T178	1		T212	6		T294	1
auto[7]	boot_req_mode	34	1			T2	1		T19	1		T25	1
auto[7]	auto_req_mode	48	1			T13	1		T131	1		T32	1
auto[7]	sw_mode	964	1			T4	6		T30	1		T31	1