Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	718377	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6025450

1

T1

12

T2

30

T3

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1765549	1			T1	6		T2	363		T3	5
values[0x0]	2299407	1			T1	8		T2	16		T3	8
values[0x1]	2678871	1			T1	7		T2	12		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	346926	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6396901

1

T1

13

T2

153

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26472	1			T25	1		T6	1		T31	1
valid_sources[0x01]	25492	1			T2	2		T4	6		T5	8
valid_sources[0x02]	26865	1			T2	4		T19	2		T35	1
valid_sources[0x03]	25375	1			T2	4		T4	3		T25	6
valid_sources[0x04]	26208	1			T4	2		T25	2		T35	1
valid_sources[0x05]	26061	1			T2	2		T8	2		T6	1
valid_sources[0x06]	25938	1			T2	1		T19	2		T35	2
valid_sources[0x07]	27412	1			T3	3		T4	1		T22	251
valid_sources[0x08]	27266	1			T2	3		T35	2		T31	1
valid_sources[0x09]	26514	1			T2	2		T4	1		T13	1
valid_sources[0x0a]	27377	1			T4	4		T31	3		T178	1
valid_sources[0x0b]	26062	1			T25	8		T35	1		T178	4
valid_sources[0x0c]	25626	1			T4	6		T25	4		T35	2
valid_sources[0x0d]	25548	1			T19	2		T4	3		T25	1
valid_sources[0x0e]	27748	1			T2	2		T13	1		T6	2
valid_sources[0x0f]	26148	1			T2	2		T35	2		T178	1
valid_sources[0x10]	26306	1			T2	3		T4	2		T8	2
valid_sources[0x11]	25677	1			T4	1		T25	1		T35	2
valid_sources[0x12]	26712	1			T5	2		T6	1		T22	215
valid_sources[0x13]	26652	1			T2	4		T19	1		T4	7
valid_sources[0x14]	27257	1			T2	2		T4	1		T13	2
valid_sources[0x15]	25502	1			T2	3		T4	5		T5	4
valid_sources[0x16]	27642	1			T4	1		T13	2		T25	1
valid_sources[0x17]	27472	1			T2	3		T4	4		T35	2
valid_sources[0x18]	27207	1			T4	1		T25	4		T178	2
valid_sources[0x19]	26378	1			T19	1		T4	2		T13	2
valid_sources[0x1a]	26841	1			T2	2		T4	1		T35	1
valid_sources[0x1b]	25234	1			T1	3		T2	3		T19	1
valid_sources[0x1c]	25002	1			T19	1		T4	3		T35	1
valid_sources[0x1d]	25507	1			T2	3		T4	1		T13	2
valid_sources[0x1e]	27572	1			T2	5		T19	2		T4	1
valid_sources[0x1f]	24043	1			T2	1		T13	1		T25	1
valid_sources[0x20]	27106	1			T4	1		T13	1		T6	1
valid_sources[0x21]	25036	1			T2	7		T19	1		T4	5
valid_sources[0x22]	27416	1			T2	1		T4	1		T178	1
valid_sources[0x23]	26515	1			T2	1		T19	3		T4	2
valid_sources[0x24]	25788	1			T2	4		T4	2		T25	3
valid_sources[0x25]	27566	1			T2	4		T4	1		T35	1
valid_sources[0x26]	26946	1			T2	1		T4	1		T20	1
valid_sources[0x27]	26383	1			T4	1		T25	3		T35	2
valid_sources[0x28]	26710	1			T4	1		T155	5		T178	1
valid_sources[0x29]	24565	1			T2	3		T19	1		T25	7
valid_sources[0x2a]	26883	1			T2	3		T25	7		T178	6
valid_sources[0x2b]	27161	1			T2	2		T4	1		T13	2
valid_sources[0x2c]	26036	1			T2	2		T4	3		T155	2
valid_sources[0x2d]	27355	1			T3	4		T19	2		T4	5
valid_sources[0x2e]	24999	1			T2	1		T4	9		T8	2
valid_sources[0x2f]	25779	1			T2	2		T25	8		T8	1
valid_sources[0x30]	24994	1			T2	1		T25	1		T31	2
valid_sources[0x31]	26124	1			T2	6		T4	5		T25	6
valid_sources[0x32]	26948	1			T2	1		T25	2		T8	1
valid_sources[0x33]	26330	1			T31	1		T178	2		T22	259
valid_sources[0x34]	27815	1			T2	4		T13	1		T35	2
valid_sources[0x35]	25259	1			T2	2		T19	3		T4	2
valid_sources[0x36]	26305	1			T19	2		T4	2		T35	1
valid_sources[0x37]	26286	1			T19	1		T4	1		T35	1
valid_sources[0x38]	25402	1			T2	2		T19	1		T25	3
valid_sources[0x39]	28586	1			T4	6		T31	2		T22	183
valid_sources[0x3a]	28679	1			T2	2		T8	1		T6	2
valid_sources[0x3b]	25272	1			T2	2		T19	2		T13	1
valid_sources[0x3c]	25312	1			T19	3		T4	3		T5	8
valid_sources[0x3d]	25916	1			T2	4		T4	5		T13	4
valid_sources[0x3e]	26584	1			T5	8		T178	3		T22	239
valid_sources[0x3f]	26408	1			T2	1		T13	1		T35	4
valid_sources[0x40]	27735	1			T2	4		T3	1		T8	1
valid_sources[0x41]	24905	1			T2	1		T19	1		T4	4
valid_sources[0x42]	25829	1			T2	6		T3	4		T4	2
valid_sources[0x43]	26185	1			T2	3		T19	2		T13	4
valid_sources[0x44]	26331	1			T4	8		T25	1		T31	1
valid_sources[0x45]	25254	1			T2	1		T13	1		T35	1
valid_sources[0x46]	25979	1			T2	1		T4	8		T31	2
valid_sources[0x47]	25941	1			T2	2		T19	1		T4	7
valid_sources[0x48]	25863	1			T2	3		T4	1		T13	1
valid_sources[0x49]	26743	1			T4	1		T13	2		T35	3
valid_sources[0x4a]	27074	1			T2	1		T19	2		T13	1
valid_sources[0x4b]	24856	1			T4	2		T13	1		T178	2
valid_sources[0x4c]	25268	1			T2	2		T19	1		T4	3
valid_sources[0x4d]	24859	1			T2	1		T4	3		T13	1
valid_sources[0x4e]	25619	1			T19	1		T4	2		T145	1
valid_sources[0x4f]	26939	1			T2	2		T35	1		T20	2
valid_sources[0x50]	25845	1			T2	1		T3	1		T19	4
valid_sources[0x51]	25826	1			T2	1		T19	1		T4	1
valid_sources[0x52]	26551	1			T2	2		T19	2		T35	2
valid_sources[0x53]	26947	1			T8	9		T35	1		T155	3
valid_sources[0x54]	26320	1			T2	1		T19	1		T8	1
valid_sources[0x55]	27255	1			T2	1		T4	5		T13	1
valid_sources[0x56]	25859	1			T2	4		T13	1		T25	3
valid_sources[0x57]	25002	1			T2	1		T19	1		T4	3
valid_sources[0x58]	26138	1			T2	1		T19	5		T4	1
valid_sources[0x59]	26715	1			T19	1		T13	1		T25	3
valid_sources[0x5a]	28689	1			T19	3		T8	2		T20	1
valid_sources[0x5b]	25466	1			T2	3		T4	2		T35	2
valid_sources[0x5c]	26446	1			T2	1		T5	3		T35	2
valid_sources[0x5d]	27158	1			T2	6		T4	3		T8	2
valid_sources[0x5e]	26789	1			T4	1		T5	5		T8	1
valid_sources[0x5f]	25473	1			T2	1		T4	2		T5	7
valid_sources[0x60]	26803	1			T1	4		T2	3		T4	3
valid_sources[0x61]	27069	1			T2	3		T19	1		T13	1
valid_sources[0x62]	25758	1			T19	1		T8	1		T35	1
valid_sources[0x63]	27146	1			T2	1		T19	1		T4	9
valid_sources[0x64]	28339	1			T2	1		T25	4		T6	1
valid_sources[0x65]	25338	1			T2	2		T3	1		T19	4
valid_sources[0x66]	24963	1			T2	1		T5	2		T35	1
valid_sources[0x67]	27073	1			T25	6		T178	1		T22	253
valid_sources[0x68]	26979	1			T2	1		T19	1		T4	2
valid_sources[0x69]	26013	1			T2	1		T4	6		T35	1
valid_sources[0x6a]	27541	1			T2	1		T25	7		T8	2
valid_sources[0x6b]	24606	1			T2	2		T4	6		T13	1
valid_sources[0x6c]	27057	1			T2	1		T19	1		T4	2
valid_sources[0x6d]	26256	1			T2	3		T4	6		T13	1
valid_sources[0x6e]	26308	1			T25	1		T35	1		T178	1
valid_sources[0x6f]	25599	1			T2	2		T4	4		T5	3
valid_sources[0x70]	26081	1			T2	2		T4	5		T13	2
valid_sources[0x71]	28238	1			T2	2		T19	1		T25	5
valid_sources[0x72]	25472	1			T2	3		T19	1		T4	2
valid_sources[0x73]	26138	1			T8	1		T31	1		T178	1
valid_sources[0x74]	26080	1			T2	4		T19	1		T4	7
valid_sources[0x75]	27082	1			T2	1		T19	4		T8	1
valid_sources[0x76]	26384	1			T2	3		T4	2		T25	2
valid_sources[0x77]	26784	1			T2	2		T19	1		T4	4
valid_sources[0x78]	26250	1			T4	3		T25	6		T178	1
valid_sources[0x79]	25509	1			T19	2		T4	2		T13	1
valid_sources[0x7a]	24250	1			T2	1		T19	1		T4	3
valid_sources[0x7b]	29067	1			T2	1		T4	1		T25	6
valid_sources[0x7c]	26325	1			T4	1		T8	3		T35	2
valid_sources[0x7d]	28424	1			T2	1		T19	1		T4	6
valid_sources[0x7e]	27611	1			T4	1		T25	1		T35	1
valid_sources[0x7f]	25351	1			T2	1		T4	1		T8	1
valid_sources[0x80]	26771	1			T2	2		T4	2		T8	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1516493

1

T1

3

T2

6

T3

3

values[0x0]

all_enables

biggest_size

2255353

1

T1

7

T2

13

T3

7

values[0x1]

all_enables

biggest_size

2253604

1

T1

2

T2

11

T3

2