Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
67.19	67.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	67.19	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
67.19	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	21	31	59.62

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	21	31	59.62	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2493	1			T4	3		T13	12		T35	4
non_zero_bins[1]	1779	1			T13	1		T25	1		T35	1
zero	8049	1			T1	3		T2	4		T3	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	488	1			T35	1		T30	1		T178	1
uni	3395	1			T2	1		T19	1		T4	6
gen	3781	1			T1	1		T2	1		T3	2
res	767	1			T4	1		T13	2		T9	2
ins	3890	1			T1	2		T2	2		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8355

1

T1

1

T2

2

T3

3

mubi_true

3966

1

T1

2

T2

2

T3

1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

50

1

T8

1

T14

1

T15

1

pass

12271

1

T1

3

T2

4

T3

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	21	31	59.62	21
Automatically Generated Cross Bins	52	21	31	59.62	21
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	115	1			T22	2		T141	1		T23	3
upd	non_zero_bins[0]	pass	mubi_true	101	1			T30	1		T137	1		T23	2
upd	non_zero_bins[1]	pass	mubi_false	87	1			T22	2		T23	1		T139	1
upd	non_zero_bins[1]	pass	mubi_true	81	1			T35	1		T178	1		T22	2
upd	zero	pass	mubi_false	44	1			T23	1		T139	2		T216	1
upd	zero	pass	mubi_true	60	1			T22	1		T179	1		T24	1
uni	zero	fail	mubi_false	13	1			T14	1		T116	1		T117	1
uni	zero	pass	mubi_false	2461	1			T2	1		T19	1		T4	2
uni	zero	pass	mubi_true	921	1			T4	4		T35	2		T22	16
gen	non_zero_bins[0]	pass	mubi_false	460	1			T4	1		T9	3		T22	6
gen	non_zero_bins[0]	pass	mubi_true	513	1			T13	9		T35	2		T22	5
gen	non_zero_bins[1]	pass	mubi_false	322	1			T13	1		T9	1		T22	5
gen	non_zero_bins[1]	pass	mubi_true	287	1			T22	2		T179	1		T132	2
gen	zero	fail	mubi_false	22	1			T8	1		T60	1		T146	1
gen	zero	pass	mubi_false	1714	1			T2	1		T3	1		T19	1
gen	zero	pass	mubi_true	463	1			T1	1		T3	1		T25	1
res	non_zero_bins[0]	pass	mubi_false	189	1			T13	2		T22	1		T56	2
res	non_zero_bins[0]	pass	mubi_true	143	1			T4	1		T22	2		T142	1
res	non_zero_bins[1]	pass	mubi_false	163	1			T22	2		T131	2		T26	1
res	non_zero_bins[1]	pass	mubi_true	108	1			T9	2		T133	2		T138	2
res	zero	fail	mubi_false	9	1			T61	1		T184	1		T180	1
res	zero	pass	mubi_false	89	1			T132	2		T141	3		T23	6
res	zero	pass	mubi_true	66	1			T22	1		T197	1		T10	2
ins	non_zero_bins[0]	pass	mubi_false	520	1			T4	1		T22	3		T28	1
ins	non_zero_bins[0]	pass	mubi_true	452	1			T13	1		T35	2		T30	1
ins	non_zero_bins[1]	pass	mubi_false	356	1			T25	1		T178	1		T22	5
ins	non_zero_bins[1]	pass	mubi_true	375	1			T9	1		T31	1		T22	7
ins	zero	fail	mubi_false	4	1			T15	1		T253	1		T254	1
ins	zero	fail	mubi_true	2	1			T102	1		T103	1		-	-
ins	zero	pass	mubi_false	1787	1			T1	1		T3	2		T19	1
ins	zero	pass	mubi_true	394	1			T1	1		T2	2		T19	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded