Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	235155378	10792490	0	0
boot_gen_cmd_rd_A	235155378	45906	0	0
boot_ins_cmd_rd_A	235155378	52430	0	0
ctrl_rd_A	235155378	47293	0	0
err_code_test_rd_A	235155378	52695	0	0
intr_enable_rd_A	235155378	51803	0	0
max_num_reqs_between_reseeds_rd_A	235155378	47468	0	0
regwen_rd_A	235155378	54916	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235155378	10792490	0	0
T22	166705	92119	0	0
T23	0	555319	0	0
T24	0	49137	0	0
T28	4138	0	0	0
T33	3071	0	0	0
T34	1371	0	0	0
T56	5507	0	0	0
T89	1033	0	0	0
T131	1658	0	0	0
T139	0	471490	0	0
T140	0	93836	0	0
T143	2369	0	0	0
T179	1755	0	0	0
T192	0	207052	0	0
T193	0	202755	0	0
T194	0	62786	0	0
T195	0	59730	0	0
T196	0	72444	0	0
T197	1313	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235155378	45906	0	0
T24	142662	1550	0	0
T88	810	0	0	0
T134	1992	0	0	0
T191	3001	0	0	0
T196	0	2121	0	0
T198	0	4362	0	0
T199	0	7655	0	0
T200	0	1683	0	0
T201	0	14348	0	0
T202	0	3092	0	0
T203	0	6312	0	0
T204	0	4298	0	0
T205	0	11	0	0
T206	2385	0	0	0
T207	3708	0	0	0
T208	1575	0	0	0
T209	5950	0	0	0
T210	2045	0	0	0
T211	1070	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235155378	52430	0	0
T24	142662	1610	0	0
T88	810	0	0	0
T134	1992	0	0	0
T191	3001	0	0	0
T196	0	2445	0	0
T198	0	5166	0	0
T199	0	9084	0	0
T200	0	1894	0	0
T201	0	16281	0	0
T202	0	3526	0	0
T203	0	7164	0	0
T204	0	4725	0	0
T205	0	12	0	0
T206	2385	0	0	0
T207	3708	0	0	0
T208	1575	0	0	0
T209	5950	0	0	0
T210	2045	0	0	0
T211	1070	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235155378	47293	0	0
T22	166705	0	0	0
T24	0	1445	0	0
T28	4138	0	0	0
T33	3071	0	0	0
T34	1371	0	0	0
T36	2236	8	0	0
T38	0	1	0	0
T40	0	5	0	0
T56	5507	0	0	0
T74	0	3	0	0
T127	0	2	0	0
T131	1658	0	0	0
T138	0	8	0	0
T143	2369	0	0	0
T159	0	3	0	0
T179	1755	0	0	0
T196	0	2306	0	0
T197	1313	0	0	0
T212	0	2	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235155378	52695	0	0
T24	142662	1653	0	0
T88	810	0	0	0
T134	1992	0	0	0
T191	3001	0	0	0
T196	0	2474	0	0
T198	0	5154	0	0
T199	0	9001	0	0
T200	0	1825	0	0
T201	0	16450	0	0
T202	0	3600	0	0
T203	0	7292	0	0
T204	0	4830	0	0
T206	2385	0	0	0
T207	3708	0	0	0
T208	1575	0	0	0
T209	5950	0	0	0
T210	2045	0	0	0
T211	1070	0	0	0
T213	0	20	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235155378	51803	0	0
T6	886	0	0	0
T9	4649	0	0	0
T20	1952	0	0	0
T21	902	0	0	0
T24	0	1661	0	0
T30	1510	0	0	0
T31	3796	0	0	0
T35	9534	11	0	0
T142	0	102	0	0
T145	564	0	0	0
T155	1799	0	0	0
T178	3883	0	0	0
T196	0	2221	0	0
T198	0	4960	0	0
T212	0	74	0	0
T214	0	20	0	0
T215	0	40	0	0
T216	0	17	0	0
T217	0	69	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235155378	47468	0	0
T24	142662	1387	0	0
T88	810	0	0	0
T134	1992	0	0	0
T191	3001	0	0	0
T196	0	2208	0	0
T198	0	4416	0	0
T199	0	8105	0	0
T200	0	1594	0	0
T201	0	14545	0	0
T202	0	3329	0	0
T203	0	6455	0	0
T204	0	4142	0	0
T206	2385	0	0	0
T207	3708	0	0	0
T208	1575	0	0	0
T209	5950	0	0	0
T210	2045	0	0	0
T211	1070	0	0	0
T218	0	6	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235155378	54916	0	0
T24	142662	1701	0	0
T88	810	0	0	0
T134	1992	0	0	0
T191	3001	0	0	0
T196	0	2520	0	0
T198	0	5156	0	0
T199	0	9005	0	0
T200	0	1891	0	0
T201	0	16952	0	0
T202	0	3659	0	0
T203	0	7653	0	0
T204	0	4846	0	0
T206	2385	0	0	0
T207	3708	0	0	0
T208	1575	0	0	0
T209	5950	0	0	0
T210	2045	0	0	0
T211	1070	0	0	0
T218	0	7	0	0