Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.58 98.27 93.56 96.84 79.77 96.87 96.58 93.15


Total test records in report: 972
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T786 /workspace/coverage/default/129.edn_genbits.1393372175 Feb 21 12:54:47 PM PST 24 Feb 21 12:54:50 PM PST 24 64903811 ps
T787 /workspace/coverage/default/46.edn_stress_all.4074275978 Feb 21 12:54:17 PM PST 24 Feb 21 12:54:21 PM PST 24 242143783 ps
T788 /workspace/coverage/default/280.edn_genbits.1490709497 Feb 21 12:55:00 PM PST 24 Feb 21 12:55:02 PM PST 24 220802412 ps
T789 /workspace/coverage/default/43.edn_genbits.2076604741 Feb 21 12:54:10 PM PST 24 Feb 21 12:54:12 PM PST 24 32286346 ps
T790 /workspace/coverage/default/3.edn_disable_auto_req_mode.2328895039 Feb 21 12:52:30 PM PST 24 Feb 21 12:52:32 PM PST 24 202573105 ps
T791 /workspace/coverage/default/21.edn_alert_test.3977226352 Feb 21 12:53:20 PM PST 24 Feb 21 12:53:22 PM PST 24 61078586 ps
T792 /workspace/coverage/default/22.edn_disable_auto_req_mode.3123148215 Feb 21 12:53:21 PM PST 24 Feb 21 12:53:23 PM PST 24 49156415 ps
T793 /workspace/coverage/default/46.edn_alert.3739211181 Feb 21 12:54:19 PM PST 24 Feb 21 12:54:20 PM PST 24 50534787 ps
T794 /workspace/coverage/default/62.edn_genbits.3894764126 Feb 21 12:54:29 PM PST 24 Feb 21 12:54:31 PM PST 24 91822762 ps
T795 /workspace/coverage/default/94.edn_err.756113919 Feb 21 12:54:46 PM PST 24 Feb 21 12:54:47 PM PST 24 66904692 ps
T796 /workspace/coverage/default/0.edn_smoke.4171660797 Feb 21 12:52:17 PM PST 24 Feb 21 12:52:18 PM PST 24 24640700 ps
T797 /workspace/coverage/default/38.edn_intr.1487244412 Feb 21 12:54:00 PM PST 24 Feb 21 12:54:01 PM PST 24 48676817 ps
T798 /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3207635458 Feb 21 12:52:45 PM PST 24 Feb 21 12:59:07 PM PST 24 29224899686 ps
T799 /workspace/coverage/default/219.edn_genbits.1467291495 Feb 21 12:55:01 PM PST 24 Feb 21 12:55:03 PM PST 24 52540463 ps
T800 /workspace/coverage/default/36.edn_disable.2058133525 Feb 21 12:53:40 PM PST 24 Feb 21 12:53:41 PM PST 24 12581158 ps
T801 /workspace/coverage/default/58.edn_err.1172885887 Feb 21 12:54:16 PM PST 24 Feb 21 12:54:18 PM PST 24 28447890 ps
T802 /workspace/coverage/default/85.edn_genbits.912419531 Feb 21 12:54:34 PM PST 24 Feb 21 12:54:37 PM PST 24 485597188 ps
T803 /workspace/coverage/default/30.edn_alert.3567589044 Feb 21 12:53:39 PM PST 24 Feb 21 12:53:41 PM PST 24 26938755 ps
T804 /workspace/coverage/default/4.edn_err.1136216211 Feb 21 12:52:33 PM PST 24 Feb 21 12:52:34 PM PST 24 33423693 ps
T805 /workspace/coverage/default/86.edn_genbits.215664872 Feb 21 12:54:37 PM PST 24 Feb 21 12:54:40 PM PST 24 28995835 ps
T806 /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1145342778 Feb 21 12:52:51 PM PST 24 Feb 21 12:58:36 PM PST 24 51142747915 ps
T807 /workspace/coverage/default/22.edn_smoke.4283211864 Feb 21 12:53:20 PM PST 24 Feb 21 12:53:22 PM PST 24 36172753 ps
T808 /workspace/coverage/default/2.edn_genbits.1776136519 Feb 21 12:52:14 PM PST 24 Feb 21 12:52:16 PM PST 24 126039927 ps
T809 /workspace/coverage/default/0.edn_alert.91097305 Feb 21 12:52:17 PM PST 24 Feb 21 12:52:19 PM PST 24 139511151 ps
T810 /workspace/coverage/default/74.edn_genbits.3112703416 Feb 21 12:54:34 PM PST 24 Feb 21 12:54:38 PM PST 24 243113212 ps
T811 /workspace/coverage/default/21.edn_disable.594590984 Feb 21 12:53:20 PM PST 24 Feb 21 12:53:22 PM PST 24 16585590 ps
T812 /workspace/coverage/default/35.edn_smoke.599055781 Feb 21 12:53:48 PM PST 24 Feb 21 12:53:49 PM PST 24 42603562 ps
T813 /workspace/coverage/default/181.edn_genbits.1143010353 Feb 21 12:54:49 PM PST 24 Feb 21 12:54:51 PM PST 24 81122047 ps
T814 /workspace/coverage/default/37.edn_alert.3178222500 Feb 21 12:53:47 PM PST 24 Feb 21 12:53:48 PM PST 24 46258385 ps
T815 /workspace/coverage/default/36.edn_alert_test.3141190507 Feb 21 12:53:49 PM PST 24 Feb 21 12:53:50 PM PST 24 18281101 ps
T816 /workspace/coverage/default/138.edn_genbits.3959198278 Feb 21 12:54:44 PM PST 24 Feb 21 12:54:46 PM PST 24 52036607 ps
T817 /workspace/coverage/default/46.edn_alert_test.577145759 Feb 21 12:54:10 PM PST 24 Feb 21 12:54:12 PM PST 24 43875713 ps
T818 /workspace/coverage/default/46.edn_err.4087214491 Feb 21 12:54:15 PM PST 24 Feb 21 12:54:16 PM PST 24 26722660 ps
T819 /workspace/coverage/default/27.edn_alert_test.1464342804 Feb 21 12:53:44 PM PST 24 Feb 21 12:53:46 PM PST 24 45048262 ps
T820 /workspace/coverage/default/19.edn_err.3348396749 Feb 21 12:53:04 PM PST 24 Feb 21 12:53:06 PM PST 24 47374945 ps
T821 /workspace/coverage/default/28.edn_disable.122966348 Feb 21 12:53:39 PM PST 24 Feb 21 12:53:41 PM PST 24 12896524 ps
T822 /workspace/coverage/default/15.edn_smoke.3537587813 Feb 21 12:52:52 PM PST 24 Feb 21 12:52:53 PM PST 24 16442580 ps
T823 /workspace/coverage/default/45.edn_disable.1621450495 Feb 21 12:54:10 PM PST 24 Feb 21 12:54:11 PM PST 24 14212576 ps
T824 /workspace/coverage/default/71.edn_err.1240445684 Feb 21 12:54:31 PM PST 24 Feb 21 12:54:32 PM PST 24 28025925 ps
T825 /workspace/coverage/default/238.edn_genbits.1946767430 Feb 21 12:55:08 PM PST 24 Feb 21 12:55:09 PM PST 24 60008286 ps
T146 /workspace/coverage/default/50.edn_err.3864483422 Feb 21 12:54:15 PM PST 24 Feb 21 12:54:16 PM PST 24 19527693 ps
T826 /workspace/coverage/default/32.edn_disable.2447315268 Feb 21 12:53:40 PM PST 24 Feb 21 12:53:41 PM PST 24 38950545 ps
T827 /workspace/coverage/default/43.edn_stress_all.1955736072 Feb 21 12:53:55 PM PST 24 Feb 21 12:53:57 PM PST 24 533492665 ps
T828 /workspace/coverage/default/25.edn_alert.3244901608 Feb 21 12:53:32 PM PST 24 Feb 21 12:53:34 PM PST 24 27696122 ps
T829 /workspace/coverage/default/35.edn_intr.965413099 Feb 21 12:53:45 PM PST 24 Feb 21 12:53:47 PM PST 24 22654544 ps
T830 /workspace/coverage/default/10.edn_alert_test.2808196686 Feb 21 12:52:54 PM PST 24 Feb 21 12:52:55 PM PST 24 39706249 ps
T831 /workspace/coverage/default/290.edn_genbits.1178482228 Feb 21 12:55:04 PM PST 24 Feb 21 12:55:07 PM PST 24 75428678 ps
T832 /workspace/coverage/default/5.edn_intr.2086913983 Feb 21 12:52:28 PM PST 24 Feb 21 12:52:30 PM PST 24 20824464 ps
T833 /workspace/coverage/default/31.edn_smoke.2184826873 Feb 21 12:53:41 PM PST 24 Feb 21 12:53:42 PM PST 24 138493021 ps
T834 /workspace/coverage/default/26.edn_err.2337040307 Feb 21 12:53:37 PM PST 24 Feb 21 12:53:38 PM PST 24 28191262 ps
T835 /workspace/coverage/default/32.edn_alert_test.128397187 Feb 21 12:53:41 PM PST 24 Feb 21 12:53:43 PM PST 24 108969657 ps
T836 /workspace/coverage/default/17.edn_disable.3072922296 Feb 21 12:53:01 PM PST 24 Feb 21 12:53:03 PM PST 24 11596122 ps
T837 /workspace/coverage/default/26.edn_alert_test.1056364200 Feb 21 12:53:44 PM PST 24 Feb 21 12:53:46 PM PST 24 37914701 ps
T838 /workspace/coverage/default/3.edn_smoke.153235054 Feb 21 12:52:34 PM PST 24 Feb 21 12:52:35 PM PST 24 15236921 ps
T839 /workspace/coverage/default/11.edn_disable_auto_req_mode.1021379026 Feb 21 12:52:50 PM PST 24 Feb 21 12:52:52 PM PST 24 113304025 ps
T840 /workspace/coverage/default/42.edn_alert_test.2426437432 Feb 21 12:53:59 PM PST 24 Feb 21 12:54:01 PM PST 24 15830335 ps
T841 /workspace/coverage/default/96.edn_err.583060580 Feb 21 12:54:54 PM PST 24 Feb 21 12:54:56 PM PST 24 33644960 ps
T248 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.249881010 Feb 21 12:28:54 PM PST 24 Feb 21 12:28:58 PM PST 24 164570083 ps
T249 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3352273528 Feb 21 12:28:54 PM PST 24 Feb 21 12:28:59 PM PST 24 152993255 ps
T842 /workspace/coverage/cover_reg_top/18.edn_tl_errors.4013282315 Feb 21 12:29:05 PM PST 24 Feb 21 12:29:09 PM PST 24 44183994 ps
T250 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1529528939 Feb 21 12:29:16 PM PST 24 Feb 21 12:29:19 PM PST 24 368342829 ps
T843 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1234647609 Feb 21 12:29:17 PM PST 24 Feb 21 12:29:19 PM PST 24 28798102 ps
T844 /workspace/coverage/cover_reg_top/34.edn_intr_test.3059582395 Feb 21 12:29:09 PM PST 24 Feb 21 12:29:10 PM PST 24 25484960 ps
T845 /workspace/coverage/cover_reg_top/11.edn_intr_test.3779375246 Feb 21 12:28:59 PM PST 24 Feb 21 12:29:02 PM PST 24 238331733 ps
T846 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.588338683 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:56 PM PST 24 53359351 ps
T847 /workspace/coverage/cover_reg_top/44.edn_intr_test.3775004499 Feb 21 12:29:04 PM PST 24 Feb 21 12:29:16 PM PST 24 11765917 ps
T848 /workspace/coverage/cover_reg_top/37.edn_intr_test.1853024375 Feb 21 12:29:17 PM PST 24 Feb 21 12:29:18 PM PST 24 41697540 ps
T849 /workspace/coverage/cover_reg_top/35.edn_intr_test.2941286326 Feb 21 12:29:13 PM PST 24 Feb 21 12:29:14 PM PST 24 37310479 ps
T850 /workspace/coverage/cover_reg_top/33.edn_intr_test.1711551446 Feb 21 12:29:09 PM PST 24 Feb 21 12:29:10 PM PST 24 14760351 ps
T232 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2096321816 Feb 21 12:29:04 PM PST 24 Feb 21 12:29:06 PM PST 24 51617199 ps
T851 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3178044021 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:56 PM PST 24 77108231 ps
T852 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.500067085 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:57 PM PST 24 111535180 ps
T853 /workspace/coverage/cover_reg_top/4.edn_intr_test.2966820522 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:55 PM PST 24 29234148 ps
T212 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.4248493772 Feb 21 12:28:59 PM PST 24 Feb 21 12:29:04 PM PST 24 56754663 ps
T854 /workspace/coverage/cover_reg_top/46.edn_intr_test.148750364 Feb 21 12:29:09 PM PST 24 Feb 21 12:29:10 PM PST 24 73234156 ps
T855 /workspace/coverage/cover_reg_top/38.edn_intr_test.2414745314 Feb 21 12:29:09 PM PST 24 Feb 21 12:29:10 PM PST 24 14947984 ps
T255 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.309146204 Feb 21 12:28:43 PM PST 24 Feb 21 12:28:45 PM PST 24 73928407 ps
T856 /workspace/coverage/cover_reg_top/8.edn_tl_errors.813270484 Feb 21 12:28:46 PM PST 24 Feb 21 12:28:48 PM PST 24 199443127 ps
T857 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3873422349 Feb 21 12:28:59 PM PST 24 Feb 21 12:29:06 PM PST 24 164981907 ps
T858 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2374636135 Feb 21 12:29:05 PM PST 24 Feb 21 12:29:07 PM PST 24 126588459 ps
T258 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2675215249 Feb 21 12:29:09 PM PST 24 Feb 21 12:29:11 PM PST 24 123614065 ps
T256 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2682145129 Feb 21 12:29:11 PM PST 24 Feb 21 12:29:13 PM PST 24 136610879 ps
T859 /workspace/coverage/cover_reg_top/40.edn_intr_test.765093988 Feb 21 12:29:17 PM PST 24 Feb 21 12:29:19 PM PST 24 15506033 ps
T213 /workspace/coverage/cover_reg_top/15.edn_csr_rw.3220630163 Feb 21 12:29:07 PM PST 24 Feb 21 12:29:08 PM PST 24 18263025 ps
T860 /workspace/coverage/cover_reg_top/17.edn_intr_test.4130011513 Feb 21 12:29:04 PM PST 24 Feb 21 12:29:05 PM PST 24 122513263 ps
T861 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3960346158 Feb 21 12:29:15 PM PST 24 Feb 21 12:29:17 PM PST 24 67152931 ps
T862 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1795789155 Feb 21 12:28:46 PM PST 24 Feb 21 12:28:48 PM PST 24 105852628 ps
T259 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.4115655446 Feb 21 12:28:59 PM PST 24 Feb 21 12:29:04 PM PST 24 208233508 ps
T214 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1393256197 Feb 21 12:28:48 PM PST 24 Feb 21 12:28:49 PM PST 24 15594254 ps
T215 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.830017944 Feb 21 12:28:52 PM PST 24 Feb 21 12:28:53 PM PST 24 52215789 ps
T863 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2058174476 Feb 21 12:28:54 PM PST 24 Feb 21 12:28:59 PM PST 24 94771865 ps
T864 /workspace/coverage/cover_reg_top/24.edn_intr_test.2508884033 Feb 21 12:29:33 PM PST 24 Feb 21 12:29:34 PM PST 24 32071074 ps
T233 /workspace/coverage/cover_reg_top/16.edn_csr_rw.923064094 Feb 21 12:29:14 PM PST 24 Feb 21 12:29:16 PM PST 24 41695663 ps
T865 /workspace/coverage/cover_reg_top/10.edn_intr_test.2418653208 Feb 21 12:28:54 PM PST 24 Feb 21 12:28:57 PM PST 24 40859634 ps
T234 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2468768120 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:56 PM PST 24 22285166 ps
T247 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.4018869488 Feb 21 12:28:52 PM PST 24 Feb 21 12:28:55 PM PST 24 511498416 ps
T866 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3280899655 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:58 PM PST 24 58923305 ps
T867 /workspace/coverage/cover_reg_top/0.edn_intr_test.205898680 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:56 PM PST 24 22365991 ps
T868 /workspace/coverage/cover_reg_top/18.edn_intr_test.561799180 Feb 21 12:29:19 PM PST 24 Feb 21 12:29:21 PM PST 24 27396752 ps
T869 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.179459839 Feb 21 12:29:16 PM PST 24 Feb 21 12:29:19 PM PST 24 88489116 ps
T870 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2436565608 Feb 21 12:28:59 PM PST 24 Feb 21 12:29:04 PM PST 24 271627893 ps
T871 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1726093243 Feb 21 12:29:07 PM PST 24 Feb 21 12:29:09 PM PST 24 328568595 ps
T872 /workspace/coverage/cover_reg_top/32.edn_intr_test.2579965347 Feb 21 12:29:09 PM PST 24 Feb 21 12:29:10 PM PST 24 70659665 ps
T235 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1809324776 Feb 21 12:28:54 PM PST 24 Feb 21 12:28:58 PM PST 24 37141783 ps
T873 /workspace/coverage/cover_reg_top/39.edn_intr_test.1930955411 Feb 21 12:29:17 PM PST 24 Feb 21 12:29:19 PM PST 24 14302398 ps
T874 /workspace/coverage/cover_reg_top/6.edn_intr_test.3802387457 Feb 21 12:28:52 PM PST 24 Feb 21 12:28:53 PM PST 24 45730605 ps
T875 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.160964769 Feb 21 12:29:07 PM PST 24 Feb 21 12:29:10 PM PST 24 124112933 ps
T216 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1294298502 Feb 21 12:28:49 PM PST 24 Feb 21 12:28:50 PM PST 24 16831058 ps
T236 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2966936095 Feb 21 12:28:59 PM PST 24 Feb 21 12:29:02 PM PST 24 676156134 ps
T217 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3064182132 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:57 PM PST 24 51613106 ps
T876 /workspace/coverage/cover_reg_top/42.edn_intr_test.1201391300 Feb 21 12:29:16 PM PST 24 Feb 21 12:29:18 PM PST 24 21187433 ps
T877 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2782841124 Feb 21 12:29:00 PM PST 24 Feb 21 12:29:05 PM PST 24 249842297 ps
T878 /workspace/coverage/cover_reg_top/26.edn_intr_test.3365272490 Feb 21 12:29:17 PM PST 24 Feb 21 12:29:19 PM PST 24 36163395 ps
T218 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1263651412 Feb 21 12:29:00 PM PST 24 Feb 21 12:29:04 PM PST 24 88455249 ps
T879 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3328552472 Feb 21 12:29:03 PM PST 24 Feb 21 12:29:05 PM PST 24 33990796 ps
T880 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2716366927 Feb 21 12:28:52 PM PST 24 Feb 21 12:28:54 PM PST 24 357066621 ps
T881 /workspace/coverage/cover_reg_top/2.edn_tl_errors.810810557 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:59 PM PST 24 57571462 ps
T882 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.284164425 Feb 21 12:29:10 PM PST 24 Feb 21 12:29:12 PM PST 24 26784109 ps
T883 /workspace/coverage/cover_reg_top/15.edn_tl_errors.3766182195 Feb 21 12:29:30 PM PST 24 Feb 21 12:29:33 PM PST 24 209048307 ps
T884 /workspace/coverage/cover_reg_top/12.edn_csr_rw.208200859 Feb 21 12:29:01 PM PST 24 Feb 21 12:29:04 PM PST 24 12826316 ps
T885 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.978746865 Feb 21 12:28:48 PM PST 24 Feb 21 12:28:52 PM PST 24 175747566 ps
T219 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1632089751 Feb 21 12:29:11 PM PST 24 Feb 21 12:29:12 PM PST 24 82993781 ps
T220 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1565350490 Feb 21 12:29:11 PM PST 24 Feb 21 12:29:12 PM PST 24 41191431 ps
T886 /workspace/coverage/cover_reg_top/13.edn_intr_test.1239743661 Feb 21 12:28:57 PM PST 24 Feb 21 12:28:59 PM PST 24 42498351 ps
T887 /workspace/coverage/cover_reg_top/3.edn_intr_test.1329210983 Feb 21 12:28:46 PM PST 24 Feb 21 12:28:48 PM PST 24 58283365 ps
T888 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2497900308 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:58 PM PST 24 300879796 ps
T889 /workspace/coverage/cover_reg_top/19.edn_intr_test.4203264948 Feb 21 12:29:17 PM PST 24 Feb 21 12:29:19 PM PST 24 32036398 ps
T890 /workspace/coverage/cover_reg_top/29.edn_intr_test.1834720343 Feb 21 12:29:17 PM PST 24 Feb 21 12:29:19 PM PST 24 39081534 ps
T891 /workspace/coverage/cover_reg_top/22.edn_intr_test.3042574859 Feb 21 12:29:30 PM PST 24 Feb 21 12:29:31 PM PST 24 12524156 ps
T221 /workspace/coverage/cover_reg_top/11.edn_csr_rw.4259039181 Feb 21 12:29:01 PM PST 24 Feb 21 12:29:04 PM PST 24 29069931 ps
T892 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2195335349 Feb 21 12:29:08 PM PST 24 Feb 21 12:29:10 PM PST 24 39343332 ps
T893 /workspace/coverage/cover_reg_top/43.edn_intr_test.1106138950 Feb 21 12:29:09 PM PST 24 Feb 21 12:29:10 PM PST 24 47156600 ps
T894 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3608871736 Feb 21 12:29:07 PM PST 24 Feb 21 12:29:09 PM PST 24 100497319 ps
T895 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1130424327 Feb 21 12:29:23 PM PST 24 Feb 21 12:29:25 PM PST 24 58661970 ps
T896 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1645154729 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:57 PM PST 24 95719836 ps
T897 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1964139671 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:57 PM PST 24 75954901 ps
T898 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1885896400 Feb 21 12:28:59 PM PST 24 Feb 21 12:29:03 PM PST 24 53469399 ps
T899 /workspace/coverage/cover_reg_top/5.edn_intr_test.3466032705 Feb 21 12:28:55 PM PST 24 Feb 21 12:28:57 PM PST 24 16410904 ps
T900 /workspace/coverage/cover_reg_top/10.edn_tl_errors.867521325 Feb 21 12:29:03 PM PST 24 Feb 21 12:29:08 PM PST 24 102364529 ps
T901 /workspace/coverage/cover_reg_top/20.edn_intr_test.4148755086 Feb 21 12:29:27 PM PST 24 Feb 21 12:29:28 PM PST 24 22246748 ps
T902 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2917057539 Feb 21 12:28:48 PM PST 24 Feb 21 12:28:50 PM PST 24 17112063 ps
T903 /workspace/coverage/cover_reg_top/7.edn_csr_rw.535855620 Feb 21 12:28:46 PM PST 24 Feb 21 12:28:47 PM PST 24 30175176 ps
T222 /workspace/coverage/cover_reg_top/5.edn_csr_rw.3425671244 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:56 PM PST 24 38749685 ps
T904 /workspace/coverage/cover_reg_top/14.edn_intr_test.2449528456 Feb 21 12:29:06 PM PST 24 Feb 21 12:29:07 PM PST 24 39948703 ps
T905 /workspace/coverage/cover_reg_top/9.edn_intr_test.932669118 Feb 21 12:28:46 PM PST 24 Feb 21 12:28:48 PM PST 24 36987078 ps
T223 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3201182899 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:55 PM PST 24 172049733 ps
T906 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1572864701 Feb 21 12:29:04 PM PST 24 Feb 21 12:29:07 PM PST 24 954163018 ps
T907 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1697613056 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:56 PM PST 24 31701114 ps
T908 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.370925323 Feb 21 12:28:41 PM PST 24 Feb 21 12:28:44 PM PST 24 91374329 ps
T909 /workspace/coverage/cover_reg_top/25.edn_intr_test.455574876 Feb 21 12:29:09 PM PST 24 Feb 21 12:29:10 PM PST 24 42328311 ps
T224 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.705373084 Feb 21 12:29:00 PM PST 24 Feb 21 12:29:04 PM PST 24 25028160 ps
T257 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1135430056 Feb 21 12:28:59 PM PST 24 Feb 21 12:29:05 PM PST 24 201668130 ps
T910 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3495296641 Feb 21 12:28:46 PM PST 24 Feb 21 12:28:48 PM PST 24 112889354 ps
T911 /workspace/coverage/cover_reg_top/1.edn_intr_test.3708022629 Feb 21 12:28:36 PM PST 24 Feb 21 12:28:38 PM PST 24 47024705 ps
T912 /workspace/coverage/cover_reg_top/16.edn_intr_test.3775204644 Feb 21 12:29:18 PM PST 24 Feb 21 12:29:21 PM PST 24 38761967 ps
T913 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1533366528 Feb 21 12:28:36 PM PST 24 Feb 21 12:28:39 PM PST 24 96331251 ps
T225 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2388595061 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:56 PM PST 24 36491791 ps
T914 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3199046426 Feb 21 12:28:59 PM PST 24 Feb 21 12:29:04 PM PST 24 41881034 ps
T915 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2037157893 Feb 21 12:29:00 PM PST 24 Feb 21 12:29:04 PM PST 24 31483216 ps
T916 /workspace/coverage/cover_reg_top/28.edn_intr_test.1945138711 Feb 21 12:29:27 PM PST 24 Feb 21 12:29:28 PM PST 24 29495013 ps
T917 /workspace/coverage/cover_reg_top/19.edn_tl_errors.2695807716 Feb 21 12:29:41 PM PST 24 Feb 21 12:29:44 PM PST 24 124534167 ps
T918 /workspace/coverage/cover_reg_top/27.edn_intr_test.1195624606 Feb 21 12:29:17 PM PST 24 Feb 21 12:29:19 PM PST 24 25432634 ps
T919 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2347869601 Feb 21 12:29:28 PM PST 24 Feb 21 12:29:29 PM PST 24 42716431 ps
T920 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2505958343 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:56 PM PST 24 105016256 ps
T921 /workspace/coverage/cover_reg_top/45.edn_intr_test.483616039 Feb 21 12:29:24 PM PST 24 Feb 21 12:29:26 PM PST 24 28195798 ps
T922 /workspace/coverage/cover_reg_top/41.edn_intr_test.3966053788 Feb 21 12:29:09 PM PST 24 Feb 21 12:29:10 PM PST 24 27183557 ps
T923 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3708864528 Feb 21 12:28:48 PM PST 24 Feb 21 12:28:50 PM PST 24 28659183 ps
T924 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3021649582 Feb 21 12:28:56 PM PST 24 Feb 21 12:28:58 PM PST 24 156183647 ps
T925 /workspace/coverage/cover_reg_top/15.edn_intr_test.68382523 Feb 21 12:29:10 PM PST 24 Feb 21 12:29:11 PM PST 24 17404468 ps
T926 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2421445505 Feb 21 12:29:05 PM PST 24 Feb 21 12:29:06 PM PST 24 28012874 ps
T927 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1525623400 Feb 21 12:29:13 PM PST 24 Feb 21 12:29:16 PM PST 24 78521510 ps
T928 /workspace/coverage/cover_reg_top/17.edn_csr_rw.3200338335 Feb 21 12:29:31 PM PST 24 Feb 21 12:29:32 PM PST 24 14357841 ps
T929 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2284982063 Feb 21 12:28:47 PM PST 24 Feb 21 12:28:49 PM PST 24 34507747 ps
T930 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3318868745 Feb 21 12:29:17 PM PST 24 Feb 21 12:29:19 PM PST 24 197817417 ps
T931 /workspace/coverage/cover_reg_top/3.edn_csr_rw.3725098820 Feb 21 12:28:59 PM PST 24 Feb 21 12:29:04 PM PST 24 16479853 ps
T932 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.932076241 Feb 21 12:29:05 PM PST 24 Feb 21 12:29:07 PM PST 24 73077716 ps
T933 /workspace/coverage/cover_reg_top/49.edn_intr_test.3941934152 Feb 21 12:29:09 PM PST 24 Feb 21 12:29:10 PM PST 24 13052957 ps
T934 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1748714685 Feb 21 12:29:30 PM PST 24 Feb 21 12:29:32 PM PST 24 19874837 ps
T226 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1515709155 Feb 21 12:28:52 PM PST 24 Feb 21 12:28:53 PM PST 24 37586434 ps
T935 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1892600894 Feb 21 12:28:53 PM PST 24 Feb 21 12:29:02 PM PST 24 315315678 ps
T936 /workspace/coverage/cover_reg_top/31.edn_intr_test.177277304 Feb 21 12:29:31 PM PST 24 Feb 21 12:29:32 PM PST 24 40966437 ps
T937 /workspace/coverage/cover_reg_top/7.edn_intr_test.1927378451 Feb 21 12:28:48 PM PST 24 Feb 21 12:28:50 PM PST 24 46358739 ps
T938 /workspace/coverage/cover_reg_top/6.edn_csr_rw.881226123 Feb 21 12:28:59 PM PST 24 Feb 21 12:29:02 PM PST 24 39636525 ps
T939 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3440318017 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:58 PM PST 24 142966306 ps
T940 /workspace/coverage/cover_reg_top/48.edn_intr_test.1334980728 Feb 21 12:29:09 PM PST 24 Feb 21 12:29:10 PM PST 24 133859952 ps
T941 /workspace/coverage/cover_reg_top/47.edn_intr_test.3568388078 Feb 21 12:29:04 PM PST 24 Feb 21 12:29:06 PM PST 24 19271493 ps
T942 /workspace/coverage/cover_reg_top/36.edn_intr_test.2540638508 Feb 21 12:29:15 PM PST 24 Feb 21 12:29:16 PM PST 24 39743000 ps
T943 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3767304608 Feb 21 12:28:53 PM PST 24 Feb 21 12:29:00 PM PST 24 1887567297 ps
T944 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3643366955 Feb 21 12:29:28 PM PST 24 Feb 21 12:29:31 PM PST 24 68969958 ps
T945 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2769122061 Feb 21 12:29:04 PM PST 24 Feb 21 12:29:06 PM PST 24 142448875 ps
T227 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2272270457 Feb 21 12:29:00 PM PST 24 Feb 21 12:29:04 PM PST 24 21141030 ps
T946 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2402308801 Feb 21 12:28:56 PM PST 24 Feb 21 12:29:01 PM PST 24 98266830 ps
T947 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1192235674 Feb 21 12:29:08 PM PST 24 Feb 21 12:29:10 PM PST 24 37252493 ps
T948 /workspace/coverage/cover_reg_top/8.edn_intr_test.610539814 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:55 PM PST 24 22129595 ps
T949 /workspace/coverage/cover_reg_top/12.edn_intr_test.1591270459 Feb 21 12:29:16 PM PST 24 Feb 21 12:29:17 PM PST 24 172059111 ps
T950 /workspace/coverage/cover_reg_top/23.edn_intr_test.722504202 Feb 21 12:29:09 PM PST 24 Feb 21 12:29:10 PM PST 24 32622728 ps
T951 /workspace/coverage/cover_reg_top/30.edn_intr_test.3296968932 Feb 21 12:29:14 PM PST 24 Feb 21 12:29:15 PM PST 24 13095786 ps
T952 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1622469568 Feb 21 12:28:57 PM PST 24 Feb 21 12:29:00 PM PST 24 31093784 ps
T953 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2395725165 Feb 21 12:29:12 PM PST 24 Feb 21 12:29:14 PM PST 24 164416634 ps
T954 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.218221923 Feb 21 12:28:54 PM PST 24 Feb 21 12:29:00 PM PST 24 59953631 ps
T955 /workspace/coverage/cover_reg_top/21.edn_intr_test.506898394 Feb 21 12:29:17 PM PST 24 Feb 21 12:29:19 PM PST 24 18464964 ps
T956 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1616580518 Feb 21 12:29:10 PM PST 24 Feb 21 12:29:12 PM PST 24 62870185 ps
T957 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1927282084 Feb 21 12:29:08 PM PST 24 Feb 21 12:29:09 PM PST 24 76924813 ps
T958 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3395541869 Feb 21 12:28:59 PM PST 24 Feb 21 12:29:03 PM PST 24 143211255 ps
T959 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4179809185 Feb 21 12:29:17 PM PST 24 Feb 21 12:29:19 PM PST 24 142104141 ps
T960 /workspace/coverage/cover_reg_top/10.edn_csr_rw.61979135 Feb 21 12:28:54 PM PST 24 Feb 21 12:28:57 PM PST 24 12112440 ps
T961 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3166067275 Feb 21 12:28:56 PM PST 24 Feb 21 12:28:58 PM PST 24 27198437 ps
T962 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2313457857 Feb 21 12:29:05 PM PST 24 Feb 21 12:29:06 PM PST 24 23111269 ps
T963 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3216223348 Feb 21 12:29:04 PM PST 24 Feb 21 12:29:06 PM PST 24 162859420 ps
T964 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2279478441 Feb 21 12:29:00 PM PST 24 Feb 21 12:29:05 PM PST 24 76032612 ps
T965 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1973838931 Feb 21 12:28:53 PM PST 24 Feb 21 12:28:56 PM PST 24 40034774 ps
T228 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2523552013 Feb 21 12:28:55 PM PST 24 Feb 21 12:28:58 PM PST 24 33366314 ps
T229 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1413707784 Feb 21 12:29:00 PM PST 24 Feb 21 12:29:04 PM PST 24 93946268 ps
T966 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2226050320 Feb 21 12:28:59 PM PST 24 Feb 21 12:29:05 PM PST 24 51940485 ps
T967 /workspace/coverage/cover_reg_top/12.edn_tl_errors.2402765657 Feb 21 12:29:10 PM PST 24 Feb 21 12:29:13 PM PST 24 72226506 ps
T968 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1419723632 Feb 21 12:29:17 PM PST 24 Feb 21 12:29:19 PM PST 24 42024249 ps
T969 /workspace/coverage/cover_reg_top/2.edn_intr_test.4273504311 Feb 21 12:29:00 PM PST 24 Feb 21 12:29:04 PM PST 24 49427661 ps
T970 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2752334709 Feb 21 12:29:30 PM PST 24 Feb 21 12:29:32 PM PST 24 117949526 ps
T230 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3481095365 Feb 21 12:29:20 PM PST 24 Feb 21 12:29:22 PM PST 24 15458006 ps
T971 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1830337190 Feb 21 12:29:05 PM PST 24 Feb 21 12:29:06 PM PST 24 67264803 ps
T972 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3673637849 Feb 21 12:28:54 PM PST 24 Feb 21 12:28:57 PM PST 24 27023811 ps
T231 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.649062582 Feb 21 12:28:56 PM PST 24 Feb 21 12:29:01 PM PST 24 349724466 ps

Test location /workspace/coverage/default/71.edn_genbits.4182650511
Short name T3
Test name
Test status
Simulation time 134318149 ps
CPU time 1.69 seconds
Started Feb 21 12:54:34 PM PST 24
Finished Feb 21 12:54:37 PM PST 24
Peak memory 217452 kb
Host smart-98345064-55f6-4e5b-9fff-ac63a101c751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182650511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.4182650511
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.677784498
Short name T5
Test name
Test status
Simulation time 50231666227 ps
CPU time 440.85 seconds
Started Feb 21 12:52:39 PM PST 24
Finished Feb 21 01:00:01 PM PST 24
Peak memory 216524 kb
Host smart-9174e563-5fbf-47ce-8f7c-c25e7cbf7b44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677784498 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.677784498
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.edn_sec_cm.4156291534
Short name T17
Test name
Test status
Simulation time 1229980714 ps
CPU time 6.49 seconds
Started Feb 21 12:52:30 PM PST 24
Finished Feb 21 12:52:37 PM PST 24
Peak memory 235712 kb
Host smart-ce0c4c73-f901-449a-85f3-281c93739b0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156291534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.4156291534
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/33.edn_alert.3261381137
Short name T18
Test name
Test status
Simulation time 30508645 ps
CPU time 1.18 seconds
Started Feb 21 12:53:39 PM PST 24
Finished Feb 21 12:53:41 PM PST 24
Peak memory 215140 kb
Host smart-a779096b-293e-47a4-97b4-88b50db37e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261381137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3261381137
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/221.edn_genbits.2396430589
Short name T13
Test name
Test status
Simulation time 39904506 ps
CPU time 1.49 seconds
Started Feb 21 12:54:58 PM PST 24
Finished Feb 21 12:55:01 PM PST 24
Peak memory 218116 kb
Host smart-cbc49fa0-bd87-408b-b85e-91275e47ab9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396430589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2396430589
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1088421767
Short name T25
Test name
Test status
Simulation time 57491868 ps
CPU time 1.28 seconds
Started Feb 21 12:55:03 PM PST 24
Finished Feb 21 12:55:07 PM PST 24
Peak memory 217072 kb
Host smart-ba84ed26-d2b7-4354-a4c5-f621df122367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088421767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1088421767
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_sec_cm.4217772229
Short name T22
Test name
Test status
Simulation time 212040482 ps
CPU time 3.73 seconds
Started Feb 21 12:52:36 PM PST 24
Finished Feb 21 12:52:40 PM PST 24
Peak memory 234968 kb
Host smart-5fc58fea-4dc1-45f4-87fa-e0612c6f2045
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217772229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.4217772229
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/40.edn_disable.37664818
Short name T103
Test name
Test status
Simulation time 14140589 ps
CPU time 0.83 seconds
Started Feb 21 12:53:57 PM PST 24
Finished Feb 21 12:53:58 PM PST 24
Peak memory 215112 kb
Host smart-adfddf0f-9114-4df2-ab97-a3910884c2ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37664818 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.37664818
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3301286043
Short name T130
Test name
Test status
Simulation time 87043604847 ps
CPU time 1114.7 seconds
Started Feb 21 12:52:56 PM PST 24
Finished Feb 21 01:11:31 PM PST 24
Peak memory 222920 kb
Host smart-51cf6e49-8bd3-49dd-b598-fcc78912b349
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301286043 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3301286043
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3156080961
Short name T74
Test name
Test status
Simulation time 192497451 ps
CPU time 1.22 seconds
Started Feb 21 12:54:10 PM PST 24
Finished Feb 21 12:54:12 PM PST 24
Peak memory 215764 kb
Host smart-26bf10b9-3ebf-4841-b746-c3034b4ed59f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156080961 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3156080961
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_alert.906829359
Short name T19
Test name
Test status
Simulation time 25141185 ps
CPU time 1.2 seconds
Started Feb 21 12:52:52 PM PST 24
Finished Feb 21 12:52:53 PM PST 24
Peak memory 215132 kb
Host smart-c5d3deac-cddc-4113-91ee-0c0204aa61f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906829359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.906829359
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/3.edn_regwen.3067627807
Short name T116
Test name
Test status
Simulation time 21388475 ps
CPU time 0.89 seconds
Started Feb 21 12:52:34 PM PST 24
Finished Feb 21 12:52:35 PM PST 24
Peak memory 206528 kb
Host smart-dd6fa073-2cb9-461e-8a7b-d4c1317963be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067627807 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3067627807
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/41.edn_alert.3952193726
Short name T113
Test name
Test status
Simulation time 80037875 ps
CPU time 1.12 seconds
Started Feb 21 12:53:55 PM PST 24
Finished Feb 21 12:53:56 PM PST 24
Peak memory 215096 kb
Host smart-52a0d0ad-b771-4d59-b34a-435754147f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952193726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3952193726
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/1.edn_intr.1214484569
Short name T126
Test name
Test status
Simulation time 20325799 ps
CPU time 1.04 seconds
Started Feb 21 12:52:25 PM PST 24
Finished Feb 21 12:52:26 PM PST 24
Peak memory 215236 kb
Host smart-ac95ff2b-9e17-4c48-bf7f-0ec83d842b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214484569 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1214484569
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2266967997
Short name T179
Test name
Test status
Simulation time 36942394518 ps
CPU time 607.1 seconds
Started Feb 21 12:53:53 PM PST 24
Finished Feb 21 01:04:01 PM PST 24
Peak memory 222944 kb
Host smart-bdb6e970-e7d3-44be-b26d-43bc0b5cd4b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266967997 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2266967997
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.4259039181
Short name T221
Test name
Test status
Simulation time 29069931 ps
CPU time 0.89 seconds
Started Feb 21 12:29:01 PM PST 24
Finished Feb 21 12:29:04 PM PST 24
Peak memory 205644 kb
Host smart-4f0e32d8-803e-4bab-a70f-800ad70f28d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259039181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.4259039181
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.4115655446
Short name T259
Test name
Test status
Simulation time 208233508 ps
CPU time 2.9 seconds
Started Feb 21 12:28:59 PM PST 24
Finished Feb 21 12:29:04 PM PST 24
Peak memory 205688 kb
Host smart-28de3813-a837-4def-bfeb-f337d90e0305
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115655446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.4115655446
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1104599975
Short name T76
Test name
Test status
Simulation time 27984955 ps
CPU time 0.96 seconds
Started Feb 21 12:53:34 PM PST 24
Finished Feb 21 12:53:35 PM PST 24
Peak memory 215036 kb
Host smart-37b66793-d86a-470d-87ba-c2f4b6770211
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104599975 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1104599975
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_disable.3480406498
Short name T165
Test name
Test status
Simulation time 21719027 ps
CPU time 0.84 seconds
Started Feb 21 12:53:41 PM PST 24
Finished Feb 21 12:53:43 PM PST 24
Peak memory 215256 kb
Host smart-5db1ac82-992f-4b09-a3ce-0a4f79e659b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480406498 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3480406498
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1164481184
Short name T569
Test name
Test status
Simulation time 52066889 ps
CPU time 1.21 seconds
Started Feb 21 12:52:57 PM PST 24
Finished Feb 21 12:52:59 PM PST 24
Peak memory 215848 kb
Host smart-324a5dcd-9997-476d-a2db-c8e02417255f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164481184 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1164481184
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_disable.1138231247
Short name T154
Test name
Test status
Simulation time 80156206 ps
CPU time 0.83 seconds
Started Feb 21 12:54:32 PM PST 24
Finished Feb 21 12:54:33 PM PST 24
Peak memory 215144 kb
Host smart-870cd98d-ddcb-4c43-801d-6e674d3c2072
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138231247 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1138231247
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable.1981813910
Short name T108
Test name
Test status
Simulation time 65522135 ps
CPU time 0.83 seconds
Started Feb 21 12:52:40 PM PST 24
Finished Feb 21 12:52:42 PM PST 24
Peak memory 215044 kb
Host smart-8d19fdc4-2e9d-4568-811f-508b26899f9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981813910 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1981813910
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/10.edn_intr.2351245245
Short name T122
Test name
Test status
Simulation time 91159522 ps
CPU time 0.79 seconds
Started Feb 21 12:52:51 PM PST 24
Finished Feb 21 12:52:53 PM PST 24
Peak memory 215076 kb
Host smart-d1afd81d-e0d5-478e-88ab-5a73f89ecb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351245245 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2351245245
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/27.edn_alert.3400596968
Short name T91
Test name
Test status
Simulation time 103577903 ps
CPU time 1.11 seconds
Started Feb 21 12:53:39 PM PST 24
Finished Feb 21 12:53:41 PM PST 24
Peak memory 215112 kb
Host smart-d8577da9-22ee-4f79-bcee-cbb79f13ede4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400596968 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3400596968
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.1915004429
Short name T35
Test name
Test status
Simulation time 38615300 ps
CPU time 0.91 seconds
Started Feb 21 12:54:23 PM PST 24
Finished Feb 21 12:54:25 PM PST 24
Peak memory 230432 kb
Host smart-2b06269e-13b0-4127-bb1e-cf7875708d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915004429 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1915004429
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/291.edn_genbits.2920663664
Short name T41
Test name
Test status
Simulation time 88305417 ps
CPU time 1.58 seconds
Started Feb 21 12:55:04 PM PST 24
Finished Feb 21 12:55:08 PM PST 24
Peak memory 216316 kb
Host smart-25a3e832-c1d8-42f9-84de-4a0b0dce031b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920663664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2920663664
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3583569492
Short name T287
Test name
Test status
Simulation time 37651596 ps
CPU time 1.35 seconds
Started Feb 21 12:55:04 PM PST 24
Finished Feb 21 12:55:07 PM PST 24
Peak memory 216188 kb
Host smart-c87e0cce-c036-4dcf-92ed-f0f0453d1c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583569492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3583569492
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_alert.2012304495
Short name T133
Test name
Test status
Simulation time 361697985 ps
CPU time 1.41 seconds
Started Feb 21 12:53:44 PM PST 24
Finished Feb 21 12:53:45 PM PST 24
Peak memory 215120 kb
Host smart-15841eb8-0799-43a7-8910-378892db4d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012304495 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2012304495
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/25.edn_disable.19277632
Short name T651
Test name
Test status
Simulation time 34460610 ps
CPU time 0.79 seconds
Started Feb 21 12:53:40 PM PST 24
Finished Feb 21 12:53:41 PM PST 24
Peak memory 214820 kb
Host smart-4de52df1-8b81-4996-94f0-0556d8593dfe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19277632 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.19277632
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/211.edn_genbits.2048640825
Short name T26
Test name
Test status
Simulation time 234687265 ps
CPU time 3.15 seconds
Started Feb 21 12:55:01 PM PST 24
Finished Feb 21 12:55:07 PM PST 24
Peak memory 218080 kb
Host smart-8d9e683f-1708-4ff0-b4d6-3ecff76ff351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048640825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2048640825
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2837019407
Short name T707
Test name
Test status
Simulation time 85631498 ps
CPU time 1.07 seconds
Started Feb 21 12:52:20 PM PST 24
Finished Feb 21 12:52:22 PM PST 24
Peak memory 215868 kb
Host smart-4c74e0b1-d826-4716-8d19-0aa5218aa181
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837019407 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2837019407
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.256875667
Short name T63
Test name
Test status
Simulation time 62148298 ps
CPU time 0.96 seconds
Started Feb 21 12:53:09 PM PST 24
Finished Feb 21 12:53:10 PM PST 24
Peak memory 215764 kb
Host smart-23b6f008-8ea5-42ec-8470-7af3a82b18e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256875667 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.256875667
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3815501925
Short name T80
Test name
Test status
Simulation time 33291130 ps
CPU time 1.23 seconds
Started Feb 21 12:52:31 PM PST 24
Finished Feb 21 12:52:33 PM PST 24
Peak memory 215936 kb
Host smart-2817fbef-60e9-45f9-bb1c-f53b98726528
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815501925 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3815501925
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_disable.1471110019
Short name T158
Test name
Test status
Simulation time 16623068 ps
CPU time 0.8 seconds
Started Feb 21 12:53:37 PM PST 24
Finished Feb 21 12:53:38 PM PST 24
Peak memory 215140 kb
Host smart-1fe7b26d-90f4-4183-aeba-fc8b6bf00548
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471110019 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1471110019
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/0.edn_regwen.4246509805
Short name T270
Test name
Test status
Simulation time 35340326 ps
CPU time 0.93 seconds
Started Feb 21 12:52:24 PM PST 24
Finished Feb 21 12:52:25 PM PST 24
Peak memory 206512 kb
Host smart-2cab139b-8113-416b-a5cb-ca636fbaa49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246509805 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.4246509805
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2286254078
Short name T129
Test name
Test status
Simulation time 1155632326340 ps
CPU time 5057.01 seconds
Started Feb 21 12:53:43 PM PST 24
Finished Feb 21 02:18:01 PM PST 24
Peak memory 243712 kb
Host smart-d9508712-f07b-4bbf-9493-2b96ac95d4f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286254078 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2286254078
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.edn_alert_test.4157023693
Short name T361
Test name
Test status
Simulation time 13297489 ps
CPU time 0.86 seconds
Started Feb 21 12:52:52 PM PST 24
Finished Feb 21 12:52:54 PM PST 24
Peak memory 205876 kb
Host smart-2bc0bea9-a294-408b-a652-eab0cc19eede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157023693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.4157023693
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/55.edn_genbits.1551853751
Short name T428
Test name
Test status
Simulation time 112560328 ps
CPU time 1.19 seconds
Started Feb 21 12:54:16 PM PST 24
Finished Feb 21 12:54:18 PM PST 24
Peak memory 218584 kb
Host smart-c1b13963-9c19-42f4-9701-ea00ae13ba71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551853751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1551853751
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3910258570
Short name T237
Test name
Test status
Simulation time 75731457 ps
CPU time 1.27 seconds
Started Feb 21 12:53:24 PM PST 24
Finished Feb 21 12:53:26 PM PST 24
Peak memory 215132 kb
Host smart-639dd29d-8110-475a-bb63-aded5206cbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910258570 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3910258570
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/0.edn_stress_all.1680968448
Short name T203
Test name
Test status
Simulation time 527570389 ps
CPU time 5.05 seconds
Started Feb 21 12:52:19 PM PST 24
Finished Feb 21 12:52:24 PM PST 24
Peak memory 215860 kb
Host smart-95d1458c-3642-46cc-be3f-693ebfd800c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680968448 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1680968448
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/162.edn_genbits.2511865982
Short name T283
Test name
Test status
Simulation time 37372793 ps
CPU time 1.35 seconds
Started Feb 21 12:54:52 PM PST 24
Finished Feb 21 12:54:54 PM PST 24
Peak memory 217280 kb
Host smart-d19bf2cd-7c44-4dcb-8c33-3f01251d79b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511865982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2511865982
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_regwen.2855964153
Short name T266
Test name
Test status
Simulation time 27617849 ps
CPU time 0.93 seconds
Started Feb 21 12:52:41 PM PST 24
Finished Feb 21 12:52:42 PM PST 24
Peak memory 206784 kb
Host smart-60436edb-6203-42bb-a9c4-399bb2d4f346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855964153 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2855964153
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/15.edn_intr.2463817318
Short name T121
Test name
Test status
Simulation time 24925540 ps
CPU time 0.91 seconds
Started Feb 21 12:52:52 PM PST 24
Finished Feb 21 12:52:54 PM PST 24
Peak memory 215212 kb
Host smart-75495275-6f0d-44d0-a43f-0e058ce3393b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463817318 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2463817318
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/4.edn_alert.2311087567
Short name T268
Test name
Test status
Simulation time 70169202 ps
CPU time 1.15 seconds
Started Feb 21 12:52:27 PM PST 24
Finished Feb 21 12:52:29 PM PST 24
Peak memory 215120 kb
Host smart-c621cc16-075d-4c12-a8ac-5a1b775bc51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311087567 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2311087567
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3352273528
Short name T249
Test name
Test status
Simulation time 152993255 ps
CPU time 2.29 seconds
Started Feb 21 12:28:54 PM PST 24
Finished Feb 21 12:28:59 PM PST 24
Peak memory 206032 kb
Host smart-f6f36a1e-e6ec-41b0-b97a-f39459dc8954
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352273528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3352273528
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2015879223
Short name T639
Test name
Test status
Simulation time 54195493507 ps
CPU time 1408.75 seconds
Started Feb 21 12:52:14 PM PST 24
Finished Feb 21 01:15:44 PM PST 24
Peak memory 222800 kb
Host smart-6a44683f-2b1e-4fef-a49c-a59f17ba9883
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015879223 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2015879223
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_genbits.390155811
Short name T52
Test name
Test status
Simulation time 46374597 ps
CPU time 1.28 seconds
Started Feb 21 12:52:23 PM PST 24
Finished Feb 21 12:52:24 PM PST 24
Peak memory 218124 kb
Host smart-bf7806a6-24a3-4994-bc72-d65d8b3b1f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390155811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.390155811
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.1283900337
Short name T262
Test name
Test status
Simulation time 25167292 ps
CPU time 0.9 seconds
Started Feb 21 12:52:15 PM PST 24
Finished Feb 21 12:52:16 PM PST 24
Peak memory 206532 kb
Host smart-6a3baea9-1830-4340-a88d-ef1a816a5a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283900337 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1283900337
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/100.edn_genbits.2723484756
Short name T296
Test name
Test status
Simulation time 53899731 ps
CPU time 1.12 seconds
Started Feb 21 12:54:53 PM PST 24
Finished Feb 21 12:54:54 PM PST 24
Peak memory 217592 kb
Host smart-a186005e-b460-44a1-ba6e-eed82c4cd1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723484756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2723484756
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.2126611129
Short name T285
Test name
Test status
Simulation time 164393665 ps
CPU time 1.31 seconds
Started Feb 21 12:54:45 PM PST 24
Finished Feb 21 12:54:47 PM PST 24
Peak memory 217712 kb
Host smart-2f2ad5e8-1abc-418c-a8be-bed47ed0bd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126611129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2126611129
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.1828776908
Short name T298
Test name
Test status
Simulation time 53684744 ps
CPU time 2.16 seconds
Started Feb 21 12:54:48 PM PST 24
Finished Feb 21 12:54:51 PM PST 24
Peak memory 218596 kb
Host smart-d020d7f6-ff2a-4cd0-a801-539627265561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828776908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1828776908
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.3195823037
Short name T299
Test name
Test status
Simulation time 66191884 ps
CPU time 1.75 seconds
Started Feb 21 12:54:48 PM PST 24
Finished Feb 21 12:54:51 PM PST 24
Peak memory 217360 kb
Host smart-2574c0e6-c674-4a54-9323-86a9d6348a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195823037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3195823037
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.3771333515
Short name T279
Test name
Test status
Simulation time 81786511 ps
CPU time 1.41 seconds
Started Feb 21 12:54:41 PM PST 24
Finished Feb 21 12:54:43 PM PST 24
Peak memory 217520 kb
Host smart-44bf8020-8bd7-4fcd-9def-efe85a2ae438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771333515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3771333515
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.2170377965
Short name T289
Test name
Test status
Simulation time 172984145 ps
CPU time 0.98 seconds
Started Feb 21 12:54:42 PM PST 24
Finished Feb 21 12:54:43 PM PST 24
Peak memory 215960 kb
Host smart-9888a8de-084a-4d42-8c5a-066aa8122cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170377965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2170377965
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/130.edn_genbits.1070200154
Short name T168
Test name
Test status
Simulation time 52440041 ps
CPU time 1.11 seconds
Started Feb 21 12:54:42 PM PST 24
Finished Feb 21 12:54:44 PM PST 24
Peak memory 215928 kb
Host smart-5ce450dc-1b29-4442-991a-9974b1da7765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070200154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1070200154
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.2109637936
Short name T261
Test name
Test status
Simulation time 110622149 ps
CPU time 1.38 seconds
Started Feb 21 12:54:52 PM PST 24
Finished Feb 21 12:54:54 PM PST 24
Peak memory 217696 kb
Host smart-4f9c024a-481d-4403-a993-5b50b5fb2ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109637936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2109637936
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2369586218
Short name T119
Test name
Test status
Simulation time 22109815 ps
CPU time 1.05 seconds
Started Feb 21 12:52:54 PM PST 24
Finished Feb 21 12:52:55 PM PST 24
Peak memory 215248 kb
Host smart-73d740ff-490e-4061-82d2-e8e91b6bf442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369586218 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2369586218
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/13.edn_disable.2038041523
Short name T171
Test name
Test status
Simulation time 18324425 ps
CPU time 0.9 seconds
Started Feb 21 12:53:00 PM PST 24
Finished Feb 21 12:53:02 PM PST 24
Peak memory 215148 kb
Host smart-630dc487-9966-486c-97b0-b9b6ae176286
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038041523 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2038041523
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.641083204
Short name T36
Test name
Test status
Simulation time 21120423 ps
CPU time 1.21 seconds
Started Feb 21 12:53:35 PM PST 24
Finished Feb 21 12:53:37 PM PST 24
Peak memory 229180 kb
Host smart-dc1405ec-6f6b-4ea5-a431-32ab3fd7812d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641083204 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.641083204
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/251.edn_genbits.4135692758
Short name T423
Test name
Test status
Simulation time 107435262 ps
CPU time 1.53 seconds
Started Feb 21 12:55:12 PM PST 24
Finished Feb 21 12:55:14 PM PST 24
Peak memory 216192 kb
Host smart-52841c0f-d29b-42f6-991a-61af070d7df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135692758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.4135692758
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_genbits.2038244239
Short name T333
Test name
Test status
Simulation time 75997524 ps
CPU time 1.62 seconds
Started Feb 21 12:54:40 PM PST 24
Finished Feb 21 12:54:43 PM PST 24
Peak memory 218844 kb
Host smart-d43b2dd3-6876-4324-a58a-8d5c66929617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038244239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2038244239
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1413707784
Short name T229
Test name
Test status
Simulation time 93946268 ps
CPU time 1.17 seconds
Started Feb 21 12:29:00 PM PST 24
Finished Feb 21 12:29:04 PM PST 24
Peak memory 205700 kb
Host smart-8b3b37b5-cd3e-418c-8acb-c8daf58a2da5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413707784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1413707784
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1892600894
Short name T935
Test name
Test status
Simulation time 315315678 ps
CPU time 6.41 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:29:02 PM PST 24
Peak memory 205748 kb
Host smart-a7bcfcc0-a7fe-49d0-b5c7-b8809d03193e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892600894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1892600894
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1294298502
Short name T216
Test name
Test status
Simulation time 16831058 ps
CPU time 0.9 seconds
Started Feb 21 12:28:49 PM PST 24
Finished Feb 21 12:28:50 PM PST 24
Peak memory 205680 kb
Host smart-8a6fec26-1213-45db-bc20-c379bd079ef3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294298502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1294298502
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1645154729
Short name T896
Test name
Test status
Simulation time 95719836 ps
CPU time 1.32 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:57 PM PST 24
Peak memory 216020 kb
Host smart-2de1a262-2a84-4b31-92b8-c92266dd43bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645154729 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1645154729
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2284982063
Short name T929
Test name
Test status
Simulation time 34507747 ps
CPU time 0.91 seconds
Started Feb 21 12:28:47 PM PST 24
Finished Feb 21 12:28:49 PM PST 24
Peak memory 206076 kb
Host smart-2d5a3a5f-5820-45a5-ae24-ba2833f7ee60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284982063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2284982063
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.205898680
Short name T867
Test name
Test status
Simulation time 22365991 ps
CPU time 0.83 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:56 PM PST 24
Peak memory 205612 kb
Host smart-3ef45808-214f-4261-82ca-19ecdb8ee302
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205898680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.205898680
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1697613056
Short name T907
Test name
Test status
Simulation time 31701114 ps
CPU time 1.35 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:56 PM PST 24
Peak memory 205656 kb
Host smart-6fcafa64-5410-46bc-a7e2-b17c24721403
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697613056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1697613056
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3873422349
Short name T857
Test name
Test status
Simulation time 164981907 ps
CPU time 3.21 seconds
Started Feb 21 12:28:59 PM PST 24
Finished Feb 21 12:29:06 PM PST 24
Peak memory 213976 kb
Host smart-aed22892-ea21-4d53-b889-9daa91bd18b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873422349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3873422349
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.309146204
Short name T255
Test name
Test status
Simulation time 73928407 ps
CPU time 1.47 seconds
Started Feb 21 12:28:43 PM PST 24
Finished Feb 21 12:28:45 PM PST 24
Peak memory 205752 kb
Host smart-3701c1c9-56de-402f-a522-2dfbaa874fe1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309146204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.309146204
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.284164425
Short name T882
Test name
Test status
Simulation time 26784109 ps
CPU time 1.12 seconds
Started Feb 21 12:29:10 PM PST 24
Finished Feb 21 12:29:12 PM PST 24
Peak memory 205668 kb
Host smart-4190eee9-ed4c-4e8e-8189-b1ad3602e867
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284164425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.284164425
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.4018869488
Short name T247
Test name
Test status
Simulation time 511498416 ps
CPU time 2.06 seconds
Started Feb 21 12:28:52 PM PST 24
Finished Feb 21 12:28:55 PM PST 24
Peak memory 205664 kb
Host smart-8489b4aa-8b8b-4083-903a-d11ebf62e7fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018869488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.4018869488
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1973838931
Short name T965
Test name
Test status
Simulation time 40034774 ps
CPU time 0.8 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:56 PM PST 24
Peak memory 205604 kb
Host smart-6f1e7553-75d4-46d0-b54f-d21cdb556460
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973838931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1973838931
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.500067085
Short name T852
Test name
Test status
Simulation time 111535180 ps
CPU time 1.96 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:57 PM PST 24
Peak memory 213976 kb
Host smart-7374b518-0496-446d-a516-a6afb135f29f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500067085 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.500067085
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3201182899
Short name T223
Test name
Test status
Simulation time 172049733 ps
CPU time 0.92 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:55 PM PST 24
Peak memory 205672 kb
Host smart-bce07e67-4439-4c0b-a94e-0c5238596f66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201182899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3201182899
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3708022629
Short name T911
Test name
Test status
Simulation time 47024705 ps
CPU time 0.89 seconds
Started Feb 21 12:28:36 PM PST 24
Finished Feb 21 12:28:38 PM PST 24
Peak memory 204880 kb
Host smart-1789b968-de48-4ba7-b0cd-1644e2d52641
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708022629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3708022629
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2505958343
Short name T920
Test name
Test status
Simulation time 105016256 ps
CPU time 1.14 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:56 PM PST 24
Peak memory 205804 kb
Host smart-e8f48f8c-8aac-4ee8-b635-2faf3d3ed876
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505958343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2505958343
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3440318017
Short name T939
Test name
Test status
Simulation time 142966306 ps
CPU time 2.73 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:58 PM PST 24
Peak memory 213956 kb
Host smart-d17958c9-9d56-45b7-92d1-956de9ca94f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440318017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3440318017
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1533366528
Short name T913
Test name
Test status
Simulation time 96331251 ps
CPU time 2.5 seconds
Started Feb 21 12:28:36 PM PST 24
Finished Feb 21 12:28:39 PM PST 24
Peak memory 204908 kb
Host smart-5c7c5104-5d47-4f56-97e0-a6e3a57ad818
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533366528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1533366528
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3673637849
Short name T972
Test name
Test status
Simulation time 27023811 ps
CPU time 1.51 seconds
Started Feb 21 12:28:54 PM PST 24
Finished Feb 21 12:28:57 PM PST 24
Peak memory 214000 kb
Host smart-ab67ce89-d846-46f8-a7b6-085ecccd4dc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673637849 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3673637849
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.61979135
Short name T960
Test name
Test status
Simulation time 12112440 ps
CPU time 0.85 seconds
Started Feb 21 12:28:54 PM PST 24
Finished Feb 21 12:28:57 PM PST 24
Peak memory 206036 kb
Host smart-f1d5780b-8d58-4bf9-9c46-34ce49139014
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61979135 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.61979135
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2418653208
Short name T865
Test name
Test status
Simulation time 40859634 ps
CPU time 0.83 seconds
Started Feb 21 12:28:54 PM PST 24
Finished Feb 21 12:28:57 PM PST 24
Peak memory 205600 kb
Host smart-ca25f671-f0a1-4f56-8cca-0bbb42cb064e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418653208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2418653208
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.4248493772
Short name T212
Test name
Test status
Simulation time 56754663 ps
CPU time 1.25 seconds
Started Feb 21 12:28:59 PM PST 24
Finished Feb 21 12:29:04 PM PST 24
Peak memory 205680 kb
Host smart-4f3fefc4-9477-4832-bbfa-f78595277501
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248493772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.4248493772
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.867521325
Short name T900
Test name
Test status
Simulation time 102364529 ps
CPU time 4.07 seconds
Started Feb 21 12:29:03 PM PST 24
Finished Feb 21 12:29:08 PM PST 24
Peak memory 214040 kb
Host smart-8727877d-02a1-40ec-bf87-b07e934094d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867521325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.867521325
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3021649582
Short name T924
Test name
Test status
Simulation time 156183647 ps
CPU time 1.44 seconds
Started Feb 21 12:28:56 PM PST 24
Finished Feb 21 12:28:58 PM PST 24
Peak memory 205756 kb
Host smart-af6a1601-40a5-4994-af58-f524a5c1c64f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021649582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3021649582
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2769122061
Short name T945
Test name
Test status
Simulation time 142448875 ps
CPU time 1.45 seconds
Started Feb 21 12:29:04 PM PST 24
Finished Feb 21 12:29:06 PM PST 24
Peak memory 214004 kb
Host smart-cffbb18d-2e7f-4720-9864-52801f1f0981
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769122061 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2769122061
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.3779375246
Short name T845
Test name
Test status
Simulation time 238331733 ps
CPU time 0.87 seconds
Started Feb 21 12:28:59 PM PST 24
Finished Feb 21 12:29:02 PM PST 24
Peak memory 205652 kb
Host smart-13c472b7-64e7-4b90-8bfd-6f68ff56a22a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779375246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3779375246
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3318868745
Short name T930
Test name
Test status
Simulation time 197817417 ps
CPU time 1.14 seconds
Started Feb 21 12:29:17 PM PST 24
Finished Feb 21 12:29:19 PM PST 24
Peak memory 205416 kb
Host smart-4a73f0ba-7603-4f69-aa20-e76f88fda78a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318868745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3318868745
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2436565608
Short name T870
Test name
Test status
Simulation time 271627893 ps
CPU time 3.97 seconds
Started Feb 21 12:28:59 PM PST 24
Finished Feb 21 12:29:04 PM PST 24
Peak memory 214028 kb
Host smart-c9c699e5-4b40-48e5-b562-4b7aa37ec02b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436565608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2436565608
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1572864701
Short name T906
Test name
Test status
Simulation time 954163018 ps
CPU time 2.43 seconds
Started Feb 21 12:29:04 PM PST 24
Finished Feb 21 12:29:07 PM PST 24
Peak memory 205552 kb
Host smart-ceca8a36-db3c-4f59-9437-cbbc0267ccc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572864701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1572864701
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3960346158
Short name T861
Test name
Test status
Simulation time 67152931 ps
CPU time 1.51 seconds
Started Feb 21 12:29:15 PM PST 24
Finished Feb 21 12:29:17 PM PST 24
Peak memory 214020 kb
Host smart-4362d873-01f5-40e9-9c98-0add3bfaabe1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960346158 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3960346158
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.208200859
Short name T884
Test name
Test status
Simulation time 12826316 ps
CPU time 0.89 seconds
Started Feb 21 12:29:01 PM PST 24
Finished Feb 21 12:29:04 PM PST 24
Peak memory 205612 kb
Host smart-1e420578-c01e-4e37-b8d7-a2ca9b9a152a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208200859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.208200859
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1591270459
Short name T949
Test name
Test status
Simulation time 172059111 ps
CPU time 0.83 seconds
Started Feb 21 12:29:16 PM PST 24
Finished Feb 21 12:29:17 PM PST 24
Peak memory 205616 kb
Host smart-757c26ec-419d-455f-b667-35363f6d6468
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591270459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1591270459
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2395725165
Short name T953
Test name
Test status
Simulation time 164416634 ps
CPU time 1.58 seconds
Started Feb 21 12:29:12 PM PST 24
Finished Feb 21 12:29:14 PM PST 24
Peak memory 206072 kb
Host smart-3e8b4e2b-31cd-45de-8dc7-e105eecb6a4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395725165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2395725165
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2402765657
Short name T967
Test name
Test status
Simulation time 72226506 ps
CPU time 2.63 seconds
Started Feb 21 12:29:10 PM PST 24
Finished Feb 21 12:29:13 PM PST 24
Peak memory 214008 kb
Host smart-031b1712-41f6-462c-a135-8ed00d4003aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402765657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2402765657
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.160964769
Short name T875
Test name
Test status
Simulation time 124112933 ps
CPU time 1.96 seconds
Started Feb 21 12:29:07 PM PST 24
Finished Feb 21 12:29:10 PM PST 24
Peak memory 205736 kb
Host smart-ce57c477-66cb-4b68-b0e1-483d66859b41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160964769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.160964769
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2374636135
Short name T858
Test name
Test status
Simulation time 126588459 ps
CPU time 1.43 seconds
Started Feb 21 12:29:05 PM PST 24
Finished Feb 21 12:29:07 PM PST 24
Peak memory 214016 kb
Host smart-9d3be950-0dd5-40e2-96ce-f49196776333
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374636135 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2374636135
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1632089751
Short name T219
Test name
Test status
Simulation time 82993781 ps
CPU time 0.86 seconds
Started Feb 21 12:29:11 PM PST 24
Finished Feb 21 12:29:12 PM PST 24
Peak memory 205676 kb
Host smart-bb4cfe71-3b0d-493a-8ec6-7ab9afe3a57c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632089751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1632089751
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1239743661
Short name T886
Test name
Test status
Simulation time 42498351 ps
CPU time 0.81 seconds
Started Feb 21 12:28:57 PM PST 24
Finished Feb 21 12:28:59 PM PST 24
Peak memory 205624 kb
Host smart-51b0faab-f2d4-46cd-b17f-2dd1b7078a74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239743661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1239743661
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2096321816
Short name T232
Test name
Test status
Simulation time 51617199 ps
CPU time 1.47 seconds
Started Feb 21 12:29:04 PM PST 24
Finished Feb 21 12:29:06 PM PST 24
Peak memory 205688 kb
Host smart-d86b217a-474f-423b-95b9-27317687ba3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096321816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2096321816
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2195335349
Short name T892
Test name
Test status
Simulation time 39343332 ps
CPU time 2.6 seconds
Started Feb 21 12:29:08 PM PST 24
Finished Feb 21 12:29:10 PM PST 24
Peak memory 213916 kb
Host smart-5630f825-8379-4386-a8a4-6bb5533f85a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195335349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2195335349
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2682145129
Short name T256
Test name
Test status
Simulation time 136610879 ps
CPU time 1.72 seconds
Started Feb 21 12:29:11 PM PST 24
Finished Feb 21 12:29:13 PM PST 24
Peak memory 206076 kb
Host smart-538794ba-2e24-48eb-b8e3-87011494f5d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682145129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2682145129
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1616580518
Short name T956
Test name
Test status
Simulation time 62870185 ps
CPU time 1.55 seconds
Started Feb 21 12:29:10 PM PST 24
Finished Feb 21 12:29:12 PM PST 24
Peak memory 214004 kb
Host smart-9ba46fac-c39d-4395-ba52-9825f8499838
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616580518 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1616580518
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3481095365
Short name T230
Test name
Test status
Simulation time 15458006 ps
CPU time 0.85 seconds
Started Feb 21 12:29:20 PM PST 24
Finished Feb 21 12:29:22 PM PST 24
Peak memory 205668 kb
Host smart-14f0115f-a0c9-4f81-812e-2e7b1597e9d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481095365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3481095365
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2449528456
Short name T904
Test name
Test status
Simulation time 39948703 ps
CPU time 0.81 seconds
Started Feb 21 12:29:06 PM PST 24
Finished Feb 21 12:29:07 PM PST 24
Peak memory 205544 kb
Host smart-bd4f4aee-fece-4d36-958d-85bf11cdace0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449528456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2449528456
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.932076241
Short name T932
Test name
Test status
Simulation time 73077716 ps
CPU time 1.46 seconds
Started Feb 21 12:29:05 PM PST 24
Finished Feb 21 12:29:07 PM PST 24
Peak memory 205704 kb
Host smart-b79396c7-8c8d-481a-8d0e-83bcceb171dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932076241 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.932076241
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1748714685
Short name T934
Test name
Test status
Simulation time 19874837 ps
CPU time 1.42 seconds
Started Feb 21 12:29:30 PM PST 24
Finished Feb 21 12:29:32 PM PST 24
Peak memory 214256 kb
Host smart-0ca05abe-def0-4ab0-a4d1-9ceb15f31459
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748714685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1748714685
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1529528939
Short name T250
Test name
Test status
Simulation time 368342829 ps
CPU time 2.4 seconds
Started Feb 21 12:29:16 PM PST 24
Finished Feb 21 12:29:19 PM PST 24
Peak memory 205676 kb
Host smart-f444f9ed-a9b5-40fb-a499-86b7822aac6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529528939 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1529528939
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3608871736
Short name T894
Test name
Test status
Simulation time 100497319 ps
CPU time 1.46 seconds
Started Feb 21 12:29:07 PM PST 24
Finished Feb 21 12:29:09 PM PST 24
Peak memory 213920 kb
Host smart-d1e6c4e2-54be-42ce-918b-e379c65ad0a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608871736 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3608871736
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.3220630163
Short name T213
Test name
Test status
Simulation time 18263025 ps
CPU time 0.86 seconds
Started Feb 21 12:29:07 PM PST 24
Finished Feb 21 12:29:08 PM PST 24
Peak memory 205636 kb
Host smart-1a76322f-06a7-469a-a027-e9348ee64b23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220630163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3220630163
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.68382523
Short name T925
Test name
Test status
Simulation time 17404468 ps
CPU time 0.86 seconds
Started Feb 21 12:29:10 PM PST 24
Finished Feb 21 12:29:11 PM PST 24
Peak memory 205700 kb
Host smart-be728db0-23ef-4398-a88a-9d126a3404e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68382523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.68382523
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2421445505
Short name T926
Test name
Test status
Simulation time 28012874 ps
CPU time 1.11 seconds
Started Feb 21 12:29:05 PM PST 24
Finished Feb 21 12:29:06 PM PST 24
Peak memory 205740 kb
Host smart-eb71d807-b139-4690-b866-8c655dd41b44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421445505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2421445505
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3766182195
Short name T883
Test name
Test status
Simulation time 209048307 ps
CPU time 3.24 seconds
Started Feb 21 12:29:30 PM PST 24
Finished Feb 21 12:29:33 PM PST 24
Peak memory 214288 kb
Host smart-2fe5fc10-40ff-44f0-903a-0aed61d850f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766182195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3766182195
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2675215249
Short name T258
Test name
Test status
Simulation time 123614065 ps
CPU time 1.92 seconds
Started Feb 21 12:29:09 PM PST 24
Finished Feb 21 12:29:11 PM PST 24
Peak memory 205672 kb
Host smart-72365679-ea43-443d-a325-856b28b04e7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675215249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2675215249
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1130424327
Short name T895
Test name
Test status
Simulation time 58661970 ps
CPU time 1.34 seconds
Started Feb 21 12:29:23 PM PST 24
Finished Feb 21 12:29:25 PM PST 24
Peak memory 214020 kb
Host smart-a0b91fcc-1f0c-49af-9473-9fefc28fbcd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130424327 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1130424327
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.923064094
Short name T233
Test name
Test status
Simulation time 41695663 ps
CPU time 0.89 seconds
Started Feb 21 12:29:14 PM PST 24
Finished Feb 21 12:29:16 PM PST 24
Peak memory 205672 kb
Host smart-be51d536-0c4b-44bb-93e7-f52ec415b91a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923064094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.923064094
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3775204644
Short name T912
Test name
Test status
Simulation time 38761967 ps
CPU time 0.77 seconds
Started Feb 21 12:29:18 PM PST 24
Finished Feb 21 12:29:21 PM PST 24
Peak memory 205536 kb
Host smart-54ebf3d2-4933-48c2-a5d3-60c93b32add2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775204644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3775204644
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2313457857
Short name T962
Test name
Test status
Simulation time 23111269 ps
CPU time 1.17 seconds
Started Feb 21 12:29:05 PM PST 24
Finished Feb 21 12:29:06 PM PST 24
Peak memory 205716 kb
Host smart-60232909-86fd-4463-8636-fa79bcd78798
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313457857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2313457857
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3395541869
Short name T958
Test name
Test status
Simulation time 143211255 ps
CPU time 1.77 seconds
Started Feb 21 12:28:59 PM PST 24
Finished Feb 21 12:29:03 PM PST 24
Peak memory 214064 kb
Host smart-1374f168-ba2f-4d96-960e-ed1484be6147
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395541869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3395541869
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.179459839
Short name T869
Test name
Test status
Simulation time 88489116 ps
CPU time 2.2 seconds
Started Feb 21 12:29:16 PM PST 24
Finished Feb 21 12:29:19 PM PST 24
Peak memory 205716 kb
Host smart-bb67c7d9-33e4-48dc-a91d-957becd4b6cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179459839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.179459839
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3216223348
Short name T963
Test name
Test status
Simulation time 162859420 ps
CPU time 1.32 seconds
Started Feb 21 12:29:04 PM PST 24
Finished Feb 21 12:29:06 PM PST 24
Peak memory 213936 kb
Host smart-70ad3436-77a8-40ac-b004-ce07443f6e4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216223348 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3216223348
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3200338335
Short name T928
Test name
Test status
Simulation time 14357841 ps
CPU time 0.87 seconds
Started Feb 21 12:29:31 PM PST 24
Finished Feb 21 12:29:32 PM PST 24
Peak memory 205680 kb
Host smart-0d061604-fb63-4f8f-97fd-ba79f734a466
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200338335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3200338335
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.4130011513
Short name T860
Test name
Test status
Simulation time 122513263 ps
CPU time 0.82 seconds
Started Feb 21 12:29:04 PM PST 24
Finished Feb 21 12:29:05 PM PST 24
Peak memory 205556 kb
Host smart-951508b1-60ef-4525-8047-1e0c209e0e80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130011513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.4130011513
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1927282084
Short name T957
Test name
Test status
Simulation time 76924813 ps
CPU time 1.32 seconds
Started Feb 21 12:29:08 PM PST 24
Finished Feb 21 12:29:09 PM PST 24
Peak memory 205708 kb
Host smart-60442737-b0ba-4239-9eb3-77321143dd94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927282084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1927282084
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3199046426
Short name T914
Test name
Test status
Simulation time 41881034 ps
CPU time 1.74 seconds
Started Feb 21 12:28:59 PM PST 24
Finished Feb 21 12:29:04 PM PST 24
Peak memory 214004 kb
Host smart-ac0c7369-59fa-484a-b476-8e1acece5aa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199046426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3199046426
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1525623400
Short name T927
Test name
Test status
Simulation time 78521510 ps
CPU time 2.22 seconds
Started Feb 21 12:29:13 PM PST 24
Finished Feb 21 12:29:16 PM PST 24
Peak memory 205696 kb
Host smart-12f4ed0d-d6e3-4742-950a-442eba82d172
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525623400 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1525623400
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1419723632
Short name T968
Test name
Test status
Simulation time 42024249 ps
CPU time 1.12 seconds
Started Feb 21 12:29:17 PM PST 24
Finished Feb 21 12:29:19 PM PST 24
Peak memory 213976 kb
Host smart-3c255594-3da8-4838-a25a-2e299099416f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419723632 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1419723632
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1622469568
Short name T952
Test name
Test status
Simulation time 31093784 ps
CPU time 0.85 seconds
Started Feb 21 12:28:57 PM PST 24
Finished Feb 21 12:29:00 PM PST 24
Peak memory 205672 kb
Host smart-d9b4f721-8770-4209-ab36-24f173ea4477
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622469568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1622469568
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.561799180
Short name T868
Test name
Test status
Simulation time 27396752 ps
CPU time 0.84 seconds
Started Feb 21 12:29:19 PM PST 24
Finished Feb 21 12:29:21 PM PST 24
Peak memory 205548 kb
Host smart-cadd439b-c542-41fe-b59f-3347e84f32eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561799180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.561799180
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3643366955
Short name T944
Test name
Test status
Simulation time 68969958 ps
CPU time 1.1 seconds
Started Feb 21 12:29:28 PM PST 24
Finished Feb 21 12:29:31 PM PST 24
Peak memory 205760 kb
Host smart-1605281c-9b48-4ea0-9d80-32ce51fad724
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643366955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3643366955
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.4013282315
Short name T842
Test name
Test status
Simulation time 44183994 ps
CPU time 2.97 seconds
Started Feb 21 12:29:05 PM PST 24
Finished Feb 21 12:29:09 PM PST 24
Peak memory 214088 kb
Host smart-80243f76-db56-440b-952d-1496c0c69c29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013282315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.4013282315
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4179809185
Short name T959
Test name
Test status
Simulation time 142104141 ps
CPU time 1.73 seconds
Started Feb 21 12:29:17 PM PST 24
Finished Feb 21 12:29:19 PM PST 24
Peak memory 205692 kb
Host smart-47c6972e-2052-41dc-907f-ce597d2d7554
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179809185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.4179809185
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1234647609
Short name T843
Test name
Test status
Simulation time 28798102 ps
CPU time 1.32 seconds
Started Feb 21 12:29:17 PM PST 24
Finished Feb 21 12:29:19 PM PST 24
Peak memory 213720 kb
Host smart-8214086e-9d5e-470f-b6fe-8699ea9d974d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234647609 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1234647609
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2347869601
Short name T919
Test name
Test status
Simulation time 42716431 ps
CPU time 0.83 seconds
Started Feb 21 12:29:28 PM PST 24
Finished Feb 21 12:29:29 PM PST 24
Peak memory 205612 kb
Host smart-5899ceb0-bc15-4995-969a-7473739aa644
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347869601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2347869601
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.4203264948
Short name T889
Test name
Test status
Simulation time 32036398 ps
CPU time 0.83 seconds
Started Feb 21 12:29:17 PM PST 24
Finished Feb 21 12:29:19 PM PST 24
Peak memory 205504 kb
Host smart-96b6606a-3535-44da-8538-804eb407ec08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203264948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.4203264948
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2752334709
Short name T970
Test name
Test status
Simulation time 117949526 ps
CPU time 1.04 seconds
Started Feb 21 12:29:30 PM PST 24
Finished Feb 21 12:29:32 PM PST 24
Peak memory 205660 kb
Host smart-48f38fbd-5533-465d-9f97-08f46a2a1e80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752334709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.2752334709
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2695807716
Short name T917
Test name
Test status
Simulation time 124534167 ps
CPU time 2.55 seconds
Started Feb 21 12:29:41 PM PST 24
Finished Feb 21 12:29:44 PM PST 24
Peak memory 217160 kb
Host smart-9896acac-ca04-44b9-9c7b-e0206b5f385b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695807716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2695807716
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1726093243
Short name T871
Test name
Test status
Simulation time 328568595 ps
CPU time 1.59 seconds
Started Feb 21 12:29:07 PM PST 24
Finished Feb 21 12:29:09 PM PST 24
Peak memory 205732 kb
Host smart-5d929de1-dcc2-4993-9a96-fc66d0236214
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726093243 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1726093243
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2523552013
Short name T228
Test name
Test status
Simulation time 33366314 ps
CPU time 1.23 seconds
Started Feb 21 12:28:55 PM PST 24
Finished Feb 21 12:28:58 PM PST 24
Peak memory 205764 kb
Host smart-6cba0d5b-e74a-4080-8622-7003fdc68b85
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523552013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2523552013
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2279478441
Short name T964
Test name
Test status
Simulation time 76032612 ps
CPU time 2.02 seconds
Started Feb 21 12:29:00 PM PST 24
Finished Feb 21 12:29:05 PM PST 24
Peak memory 205780 kb
Host smart-b6924786-3e9f-4cb6-b225-3d06d8aa5896
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279478441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2279478441
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1393256197
Short name T214
Test name
Test status
Simulation time 15594254 ps
CPU time 0.93 seconds
Started Feb 21 12:28:48 PM PST 24
Finished Feb 21 12:28:49 PM PST 24
Peak memory 205700 kb
Host smart-53ff67c9-03a7-458a-a701-28fcf68485d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393256197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1393256197
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3178044021
Short name T851
Test name
Test status
Simulation time 77108231 ps
CPU time 1.23 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:56 PM PST 24
Peak memory 213980 kb
Host smart-8ff06987-c2fb-4ee1-a318-b94023c2ada8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178044021 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3178044021
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2388595061
Short name T225
Test name
Test status
Simulation time 36491791 ps
CPU time 0.84 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:56 PM PST 24
Peak memory 205648 kb
Host smart-dac93530-a9d4-4717-a76c-17e40c46396d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388595061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2388595061
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.4273504311
Short name T969
Test name
Test status
Simulation time 49427661 ps
CPU time 0.85 seconds
Started Feb 21 12:29:00 PM PST 24
Finished Feb 21 12:29:04 PM PST 24
Peak memory 205636 kb
Host smart-2bb88ed5-a7ba-49b9-9803-296d7bc9dde6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273504311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.4273504311
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3064182132
Short name T217
Test name
Test status
Simulation time 51613106 ps
CPU time 1.17 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:57 PM PST 24
Peak memory 205732 kb
Host smart-d1b7314c-07ae-48f8-a9d3-702ef0e39185
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064182132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3064182132
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.810810557
Short name T881
Test name
Test status
Simulation time 57571462 ps
CPU time 2.86 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:59 PM PST 24
Peak memory 214044 kb
Host smart-54345100-20f7-4102-8c7e-c1fc261d2c8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810810557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.810810557
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.370925323
Short name T908
Test name
Test status
Simulation time 91374329 ps
CPU time 1.47 seconds
Started Feb 21 12:28:41 PM PST 24
Finished Feb 21 12:28:44 PM PST 24
Peak memory 204996 kb
Host smart-977e8130-92d1-418a-9703-086786d4b2f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370925323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.370925323
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.4148755086
Short name T901
Test name
Test status
Simulation time 22246748 ps
CPU time 0.86 seconds
Started Feb 21 12:29:27 PM PST 24
Finished Feb 21 12:29:28 PM PST 24
Peak memory 205608 kb
Host smart-49742046-c9a4-4e9c-a84c-c9030e1fbdc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148755086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.4148755086
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.506898394
Short name T955
Test name
Test status
Simulation time 18464964 ps
CPU time 0.81 seconds
Started Feb 21 12:29:17 PM PST 24
Finished Feb 21 12:29:19 PM PST 24
Peak memory 205600 kb
Host smart-cd16d03b-3cb1-4d62-9b22-1a01bb99ea69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506898394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.506898394
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3042574859
Short name T891
Test name
Test status
Simulation time 12524156 ps
CPU time 0.85 seconds
Started Feb 21 12:29:30 PM PST 24
Finished Feb 21 12:29:31 PM PST 24
Peak memory 205636 kb
Host smart-f3c5b18c-9a83-47fb-b3ec-5632250b48fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042574859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3042574859
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.722504202
Short name T950
Test name
Test status
Simulation time 32622728 ps
CPU time 0.82 seconds
Started Feb 21 12:29:09 PM PST 24
Finished Feb 21 12:29:10 PM PST 24
Peak memory 205604 kb
Host smart-b39d403d-d758-4d0b-ac8c-8f93bb0c82da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722504202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.722504202
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2508884033
Short name T864
Test name
Test status
Simulation time 32071074 ps
CPU time 0.82 seconds
Started Feb 21 12:29:33 PM PST 24
Finished Feb 21 12:29:34 PM PST 24
Peak memory 205560 kb
Host smart-833d3149-995c-4b60-b405-68db9d6e8487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508884033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2508884033
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.455574876
Short name T909
Test name
Test status
Simulation time 42328311 ps
CPU time 0.81 seconds
Started Feb 21 12:29:09 PM PST 24
Finished Feb 21 12:29:10 PM PST 24
Peak memory 205616 kb
Host smart-80b8109b-8b62-4410-9dd1-132b64ee616d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455574876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.455574876
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3365272490
Short name T878
Test name
Test status
Simulation time 36163395 ps
CPU time 0.81 seconds
Started Feb 21 12:29:17 PM PST 24
Finished Feb 21 12:29:19 PM PST 24
Peak memory 205576 kb
Host smart-d7bc435a-dec0-4fa9-a7b5-c1ba1060b9e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365272490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3365272490
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1195624606
Short name T918
Test name
Test status
Simulation time 25432634 ps
CPU time 0.86 seconds
Started Feb 21 12:29:17 PM PST 24
Finished Feb 21 12:29:19 PM PST 24
Peak memory 205568 kb
Host smart-cb917479-66c7-4ae4-80fe-0b26e0d683c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195624606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1195624606
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1945138711
Short name T916
Test name
Test status
Simulation time 29495013 ps
CPU time 0.87 seconds
Started Feb 21 12:29:27 PM PST 24
Finished Feb 21 12:29:28 PM PST 24
Peak memory 205612 kb
Host smart-3d528b1f-4997-4859-925e-941d125043af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945138711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1945138711
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1834720343
Short name T890
Test name
Test status
Simulation time 39081534 ps
CPU time 0.84 seconds
Started Feb 21 12:29:17 PM PST 24
Finished Feb 21 12:29:19 PM PST 24
Peak memory 205572 kb
Host smart-a7b4fe63-8cc1-4e2f-9765-c4adaaf184b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834720343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1834720343
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2272270457
Short name T227
Test name
Test status
Simulation time 21141030 ps
CPU time 1.23 seconds
Started Feb 21 12:29:00 PM PST 24
Finished Feb 21 12:29:04 PM PST 24
Peak memory 205716 kb
Host smart-864a733a-d4fe-405e-bdfa-809f580d727b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272270457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2272270457
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.218221923
Short name T954
Test name
Test status
Simulation time 59953631 ps
CPU time 3.37 seconds
Started Feb 21 12:28:54 PM PST 24
Finished Feb 21 12:29:00 PM PST 24
Peak memory 206088 kb
Host smart-430be76f-fb32-4a9d-9a1b-44d725eb88d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218221923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.218221923
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.705373084
Short name T224
Test name
Test status
Simulation time 25028160 ps
CPU time 0.84 seconds
Started Feb 21 12:29:00 PM PST 24
Finished Feb 21 12:29:04 PM PST 24
Peak memory 205680 kb
Host smart-b3a0a52d-6cc8-4967-85c0-3e7ed3b6ad87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705373084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.705373084
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2716366927
Short name T880
Test name
Test status
Simulation time 357066621 ps
CPU time 1.69 seconds
Started Feb 21 12:28:52 PM PST 24
Finished Feb 21 12:28:54 PM PST 24
Peak memory 214020 kb
Host smart-46cf0f6f-895d-43c8-b138-e88d35c49ddc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716366927 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2716366927
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3725098820
Short name T931
Test name
Test status
Simulation time 16479853 ps
CPU time 0.91 seconds
Started Feb 21 12:28:59 PM PST 24
Finished Feb 21 12:29:04 PM PST 24
Peak memory 205668 kb
Host smart-601adcae-a20f-4bb7-8a0d-bff87dd87664
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725098820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3725098820
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1329210983
Short name T887
Test name
Test status
Simulation time 58283365 ps
CPU time 0.84 seconds
Started Feb 21 12:28:46 PM PST 24
Finished Feb 21 12:28:48 PM PST 24
Peak memory 205656 kb
Host smart-061de43f-bab2-447f-a714-89df668d3628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329210983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1329210983
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3495296641
Short name T910
Test name
Test status
Simulation time 112889354 ps
CPU time 1.34 seconds
Started Feb 21 12:28:46 PM PST 24
Finished Feb 21 12:28:48 PM PST 24
Peak memory 205756 kb
Host smart-c25daa2c-9c1a-4287-b300-8bae59060bbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495296641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3495296641
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3280899655
Short name T866
Test name
Test status
Simulation time 58923305 ps
CPU time 2.22 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:58 PM PST 24
Peak memory 213952 kb
Host smart-243ce255-d882-4a64-9d2f-cf4218d76811
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280899655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3280899655
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3296968932
Short name T951
Test name
Test status
Simulation time 13095786 ps
CPU time 0.9 seconds
Started Feb 21 12:29:14 PM PST 24
Finished Feb 21 12:29:15 PM PST 24
Peak memory 205628 kb
Host smart-d2acc84a-f11f-49a5-aee4-d53f2c871bfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296968932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3296968932
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.177277304
Short name T936
Test name
Test status
Simulation time 40966437 ps
CPU time 0.83 seconds
Started Feb 21 12:29:31 PM PST 24
Finished Feb 21 12:29:32 PM PST 24
Peak memory 205576 kb
Host smart-d3da9be9-0c14-4a62-bcee-e73574327fbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177277304 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.177277304
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2579965347
Short name T872
Test name
Test status
Simulation time 70659665 ps
CPU time 0.86 seconds
Started Feb 21 12:29:09 PM PST 24
Finished Feb 21 12:29:10 PM PST 24
Peak memory 205636 kb
Host smart-198b38be-24ec-4b1b-9691-c42c43cc2c7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579965347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2579965347
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1711551446
Short name T850
Test name
Test status
Simulation time 14760351 ps
CPU time 1 seconds
Started Feb 21 12:29:09 PM PST 24
Finished Feb 21 12:29:10 PM PST 24
Peak memory 206016 kb
Host smart-bbbdbe05-d8ab-4fac-9b05-539219bc7abf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711551446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1711551446
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3059582395
Short name T844
Test name
Test status
Simulation time 25484960 ps
CPU time 0.84 seconds
Started Feb 21 12:29:09 PM PST 24
Finished Feb 21 12:29:10 PM PST 24
Peak memory 205636 kb
Host smart-1b4d1b95-a297-4d0a-96de-a95bc2d699fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059582395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3059582395
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2941286326
Short name T849
Test name
Test status
Simulation time 37310479 ps
CPU time 0.89 seconds
Started Feb 21 12:29:13 PM PST 24
Finished Feb 21 12:29:14 PM PST 24
Peak memory 206016 kb
Host smart-95aa4afb-a195-43f2-bbcd-85214c034579
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941286326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2941286326
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2540638508
Short name T942
Test name
Test status
Simulation time 39743000 ps
CPU time 0.83 seconds
Started Feb 21 12:29:15 PM PST 24
Finished Feb 21 12:29:16 PM PST 24
Peak memory 205556 kb
Host smart-00b019c4-ce13-437c-8ab0-8b704c54dea4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540638508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2540638508
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1853024375
Short name T848
Test name
Test status
Simulation time 41697540 ps
CPU time 0.78 seconds
Started Feb 21 12:29:17 PM PST 24
Finished Feb 21 12:29:18 PM PST 24
Peak memory 205504 kb
Host smart-9f4f5bc9-5fa6-4224-b049-76294eac12e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853024375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1853024375
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2414745314
Short name T855
Test name
Test status
Simulation time 14947984 ps
CPU time 0.88 seconds
Started Feb 21 12:29:09 PM PST 24
Finished Feb 21 12:29:10 PM PST 24
Peak memory 205616 kb
Host smart-9c971f7e-de17-438c-b413-8e21e76ed176
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414745314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2414745314
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1930955411
Short name T873
Test name
Test status
Simulation time 14302398 ps
CPU time 0.92 seconds
Started Feb 21 12:29:17 PM PST 24
Finished Feb 21 12:29:19 PM PST 24
Peak memory 205648 kb
Host smart-0155418c-8676-4224-a8dd-789982ea33fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930955411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1930955411
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1263651412
Short name T218
Test name
Test status
Simulation time 88455249 ps
CPU time 1.16 seconds
Started Feb 21 12:29:00 PM PST 24
Finished Feb 21 12:29:04 PM PST 24
Peak memory 205696 kb
Host smart-66e39770-88bd-4abd-880f-3d090adcf1be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263651412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1263651412
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.649062582
Short name T231
Test name
Test status
Simulation time 349724466 ps
CPU time 3.07 seconds
Started Feb 21 12:28:56 PM PST 24
Finished Feb 21 12:29:01 PM PST 24
Peak memory 205704 kb
Host smart-bc300774-9b19-4a8c-aeb5-e0cb2452e2ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649062582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.649062582
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1565350490
Short name T220
Test name
Test status
Simulation time 41191431 ps
CPU time 0.86 seconds
Started Feb 21 12:29:11 PM PST 24
Finished Feb 21 12:29:12 PM PST 24
Peak memory 205676 kb
Host smart-e2a7386a-10db-4d1e-b267-0959955e5f22
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565350490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1565350490
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3166067275
Short name T961
Test name
Test status
Simulation time 27198437 ps
CPU time 1.3 seconds
Started Feb 21 12:28:56 PM PST 24
Finished Feb 21 12:28:58 PM PST 24
Peak memory 213992 kb
Host smart-1b27e4a3-1447-44ac-a288-f8f818f3c54b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166067275 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3166067275
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2037157893
Short name T915
Test name
Test status
Simulation time 31483216 ps
CPU time 0.9 seconds
Started Feb 21 12:29:00 PM PST 24
Finished Feb 21 12:29:04 PM PST 24
Peak memory 205672 kb
Host smart-aada87e6-b159-43e2-8c21-2844f30ec2e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037157893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2037157893
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2966820522
Short name T853
Test name
Test status
Simulation time 29234148 ps
CPU time 0.94 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:55 PM PST 24
Peak memory 205664 kb
Host smart-b77a4f71-c6b6-4a16-ad42-b1735cad69d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966820522 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2966820522
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2917057539
Short name T902
Test name
Test status
Simulation time 17112063 ps
CPU time 1.21 seconds
Started Feb 21 12:28:48 PM PST 24
Finished Feb 21 12:28:50 PM PST 24
Peak memory 205672 kb
Host smart-9cd978da-9c8d-4980-a79b-5b15a45d5940
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917057539 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2917057539
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3767304608
Short name T943
Test name
Test status
Simulation time 1887567297 ps
CPU time 3.79 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:29:00 PM PST 24
Peak memory 214004 kb
Host smart-7f5886aa-e47f-42a0-a3e7-31673b99c823
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767304608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3767304608
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.978746865
Short name T885
Test name
Test status
Simulation time 175747566 ps
CPU time 3.12 seconds
Started Feb 21 12:28:48 PM PST 24
Finished Feb 21 12:28:52 PM PST 24
Peak memory 205600 kb
Host smart-395d475f-b92f-4344-97ee-d0414a485732
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978746865 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.978746865
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.765093988
Short name T859
Test name
Test status
Simulation time 15506033 ps
CPU time 1 seconds
Started Feb 21 12:29:17 PM PST 24
Finished Feb 21 12:29:19 PM PST 24
Peak memory 205648 kb
Host smart-63e76f03-6f6d-4f5e-9897-fd56bab996a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765093988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.765093988
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3966053788
Short name T922
Test name
Test status
Simulation time 27183557 ps
CPU time 0.76 seconds
Started Feb 21 12:29:09 PM PST 24
Finished Feb 21 12:29:10 PM PST 24
Peak memory 205564 kb
Host smart-9f14960c-c8d6-48a8-bf5d-f0a7ababede0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966053788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3966053788
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1201391300
Short name T876
Test name
Test status
Simulation time 21187433 ps
CPU time 0.81 seconds
Started Feb 21 12:29:16 PM PST 24
Finished Feb 21 12:29:18 PM PST 24
Peak memory 205556 kb
Host smart-235cea1e-be04-4515-92f4-305c56f2b0f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201391300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1201391300
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1106138950
Short name T893
Test name
Test status
Simulation time 47156600 ps
CPU time 0.83 seconds
Started Feb 21 12:29:09 PM PST 24
Finished Feb 21 12:29:10 PM PST 24
Peak memory 205636 kb
Host smart-1b896802-051f-4ef8-8ec0-52194a9463c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106138950 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1106138950
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3775004499
Short name T847
Test name
Test status
Simulation time 11765917 ps
CPU time 0.83 seconds
Started Feb 21 12:29:04 PM PST 24
Finished Feb 21 12:29:16 PM PST 24
Peak memory 205676 kb
Host smart-e61bfc5d-6a22-48f8-a929-b228ef85fdf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775004499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3775004499
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.483616039
Short name T921
Test name
Test status
Simulation time 28195798 ps
CPU time 0.85 seconds
Started Feb 21 12:29:24 PM PST 24
Finished Feb 21 12:29:26 PM PST 24
Peak memory 205648 kb
Host smart-0c26679d-4335-491b-904c-3249f1508422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483616039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.483616039
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.148750364
Short name T854
Test name
Test status
Simulation time 73234156 ps
CPU time 0.85 seconds
Started Feb 21 12:29:09 PM PST 24
Finished Feb 21 12:29:10 PM PST 24
Peak memory 205648 kb
Host smart-90f15eff-e70e-444b-9a1e-397511a3494b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148750364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.148750364
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3568388078
Short name T941
Test name
Test status
Simulation time 19271493 ps
CPU time 0.86 seconds
Started Feb 21 12:29:04 PM PST 24
Finished Feb 21 12:29:06 PM PST 24
Peak memory 205568 kb
Host smart-d53c77a7-5f5a-454a-b19b-b0da61668ccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568388078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3568388078
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1334980728
Short name T940
Test name
Test status
Simulation time 133859952 ps
CPU time 0.89 seconds
Started Feb 21 12:29:09 PM PST 24
Finished Feb 21 12:29:10 PM PST 24
Peak memory 205636 kb
Host smart-b1987d9e-9bd7-4e65-823e-9958de2d3aa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334980728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1334980728
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3941934152
Short name T933
Test name
Test status
Simulation time 13052957 ps
CPU time 0.8 seconds
Started Feb 21 12:29:09 PM PST 24
Finished Feb 21 12:29:10 PM PST 24
Peak memory 205616 kb
Host smart-7be443a3-e4f3-40b9-a4a8-501652ee4bcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941934152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3941934152
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1885896400
Short name T898
Test name
Test status
Simulation time 53469399 ps
CPU time 1.43 seconds
Started Feb 21 12:28:59 PM PST 24
Finished Feb 21 12:29:03 PM PST 24
Peak memory 222132 kb
Host smart-356e871a-0f18-46d6-976a-5411117590bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885896400 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1885896400
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3425671244
Short name T222
Test name
Test status
Simulation time 38749685 ps
CPU time 0.88 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:56 PM PST 24
Peak memory 205676 kb
Host smart-18b0ff71-9b7c-4c62-a128-bea2c0cc470b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425671244 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3425671244
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3466032705
Short name T899
Test name
Test status
Simulation time 16410904 ps
CPU time 0.92 seconds
Started Feb 21 12:28:55 PM PST 24
Finished Feb 21 12:28:57 PM PST 24
Peak memory 205620 kb
Host smart-2ade75fc-dd1f-43e3-94a0-7e4a96a20298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466032705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3466032705
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3708864528
Short name T923
Test name
Test status
Simulation time 28659183 ps
CPU time 1.25 seconds
Started Feb 21 12:28:48 PM PST 24
Finished Feb 21 12:28:50 PM PST 24
Peak memory 205708 kb
Host smart-96f3877c-1aa8-4a77-a4a9-82155e4f85d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708864528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3708864528
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2402308801
Short name T946
Test name
Test status
Simulation time 98266830 ps
CPU time 3.54 seconds
Started Feb 21 12:28:56 PM PST 24
Finished Feb 21 12:29:01 PM PST 24
Peak memory 214036 kb
Host smart-a3b2bdc9-24a1-49cb-8a4b-b26e81c92649
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402308801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2402308801
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1964139671
Short name T897
Test name
Test status
Simulation time 75954901 ps
CPU time 1.18 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:57 PM PST 24
Peak memory 213948 kb
Host smart-df5cdf57-68a7-43e0-8bc8-4f31c07ec576
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964139671 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1964139671
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.881226123
Short name T938
Test name
Test status
Simulation time 39636525 ps
CPU time 0.86 seconds
Started Feb 21 12:28:59 PM PST 24
Finished Feb 21 12:29:02 PM PST 24
Peak memory 205608 kb
Host smart-7e4a56ad-3f43-41f9-8fd8-9e664f7d5055
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881226123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.881226123
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3802387457
Short name T874
Test name
Test status
Simulation time 45730605 ps
CPU time 0.79 seconds
Started Feb 21 12:28:52 PM PST 24
Finished Feb 21 12:28:53 PM PST 24
Peak memory 205584 kb
Host smart-58d47396-f6aa-46da-92f8-67c7e34e7b25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802387457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3802387457
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1809324776
Short name T235
Test name
Test status
Simulation time 37141783 ps
CPU time 1.12 seconds
Started Feb 21 12:28:54 PM PST 24
Finished Feb 21 12:28:58 PM PST 24
Peak memory 205700 kb
Host smart-6fa1c940-97d6-485b-adae-0f5114ca3054
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809324776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1809324776
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2782841124
Short name T877
Test name
Test status
Simulation time 249842297 ps
CPU time 2.59 seconds
Started Feb 21 12:29:00 PM PST 24
Finished Feb 21 12:29:05 PM PST 24
Peak memory 213948 kb
Host smart-d0e3addd-1f4a-40f0-bc8c-d8ee21c54681
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782841124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2782841124
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.588338683
Short name T846
Test name
Test status
Simulation time 53359351 ps
CPU time 1.69 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:56 PM PST 24
Peak memory 205700 kb
Host smart-024c9b1d-5424-45c2-9f68-20ef7f9ae729
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588338683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.588338683
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1192235674
Short name T947
Test name
Test status
Simulation time 37252493 ps
CPU time 1.43 seconds
Started Feb 21 12:29:08 PM PST 24
Finished Feb 21 12:29:10 PM PST 24
Peak memory 214016 kb
Host smart-32d55acd-18a6-4b38-b74d-ba3fe47a7cb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192235674 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1192235674
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.535855620
Short name T903
Test name
Test status
Simulation time 30175176 ps
CPU time 0.79 seconds
Started Feb 21 12:28:46 PM PST 24
Finished Feb 21 12:28:47 PM PST 24
Peak memory 205624 kb
Host smart-10682648-919c-4cfb-b091-bcede9b49261
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535855620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.535855620
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1927378451
Short name T937
Test name
Test status
Simulation time 46358739 ps
CPU time 0.92 seconds
Started Feb 21 12:28:48 PM PST 24
Finished Feb 21 12:28:50 PM PST 24
Peak memory 205600 kb
Host smart-323eb5da-f009-48b2-a6b7-be53c130046b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927378451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1927378451
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2966936095
Short name T236
Test name
Test status
Simulation time 676156134 ps
CPU time 1.59 seconds
Started Feb 21 12:28:59 PM PST 24
Finished Feb 21 12:29:02 PM PST 24
Peak memory 205764 kb
Host smart-59e1c48c-506b-412b-823d-2fbee6767615
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966936095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2966936095
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2226050320
Short name T966
Test name
Test status
Simulation time 51940485 ps
CPU time 2 seconds
Started Feb 21 12:28:59 PM PST 24
Finished Feb 21 12:29:05 PM PST 24
Peak memory 213940 kb
Host smart-1422d62f-306a-4bac-a4ea-cc36cf63fddc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226050320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2226050320
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2497900308
Short name T888
Test name
Test status
Simulation time 300879796 ps
CPU time 2.25 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:58 PM PST 24
Peak memory 205652 kb
Host smart-f1ded3c1-f2e1-417b-97cc-a7044656ec1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497900308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2497900308
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1795789155
Short name T862
Test name
Test status
Simulation time 105852628 ps
CPU time 1.37 seconds
Started Feb 21 12:28:46 PM PST 24
Finished Feb 21 12:28:48 PM PST 24
Peak memory 213368 kb
Host smart-e7eeb8d8-2d7b-4c52-9f02-3ffc3eb83056
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795789155 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1795789155
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1515709155
Short name T226
Test name
Test status
Simulation time 37586434 ps
CPU time 0.86 seconds
Started Feb 21 12:28:52 PM PST 24
Finished Feb 21 12:28:53 PM PST 24
Peak memory 205588 kb
Host smart-da697072-bdaf-45a8-a71f-f796f52edeaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515709155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1515709155
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.610539814
Short name T948
Test name
Test status
Simulation time 22129595 ps
CPU time 0.86 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:55 PM PST 24
Peak memory 205616 kb
Host smart-5bc08f02-7186-4791-b7d9-e3b96afad12f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610539814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.610539814
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.830017944
Short name T215
Test name
Test status
Simulation time 52215789 ps
CPU time 1.15 seconds
Started Feb 21 12:28:52 PM PST 24
Finished Feb 21 12:28:53 PM PST 24
Peak memory 205696 kb
Host smart-3b095e78-259b-43e4-891b-5cc55733839c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830017944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_out
standing.830017944
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.813270484
Short name T856
Test name
Test status
Simulation time 199443127 ps
CPU time 1.93 seconds
Started Feb 21 12:28:46 PM PST 24
Finished Feb 21 12:28:48 PM PST 24
Peak memory 213940 kb
Host smart-23c2664e-06e2-474c-977c-d18345eb47c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813270484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.813270484
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1135430056
Short name T257
Test name
Test status
Simulation time 201668130 ps
CPU time 2.34 seconds
Started Feb 21 12:28:59 PM PST 24
Finished Feb 21 12:29:05 PM PST 24
Peak memory 205760 kb
Host smart-11d5cd83-ae10-4276-9edd-eb00929fe539
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135430056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1135430056
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3328552472
Short name T879
Test name
Test status
Simulation time 33990796 ps
CPU time 1.65 seconds
Started Feb 21 12:29:03 PM PST 24
Finished Feb 21 12:29:05 PM PST 24
Peak memory 213956 kb
Host smart-ec03f196-691b-43b9-b709-cd93bdacb8f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328552472 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3328552472
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2468768120
Short name T234
Test name
Test status
Simulation time 22285166 ps
CPU time 0.89 seconds
Started Feb 21 12:28:53 PM PST 24
Finished Feb 21 12:28:56 PM PST 24
Peak memory 205736 kb
Host smart-1bec40c9-8e4e-431f-a45e-0d2c6f2f5cb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468768120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2468768120
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.932669118
Short name T905
Test name
Test status
Simulation time 36987078 ps
CPU time 1.04 seconds
Started Feb 21 12:28:46 PM PST 24
Finished Feb 21 12:28:48 PM PST 24
Peak memory 204920 kb
Host smart-d108fbde-318a-42d8-9df7-43d3da1143ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932669118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.932669118
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1830337190
Short name T971
Test name
Test status
Simulation time 67264803 ps
CPU time 1.24 seconds
Started Feb 21 12:29:05 PM PST 24
Finished Feb 21 12:29:06 PM PST 24
Peak memory 205764 kb
Host smart-d8e4c378-4af2-45a3-a906-a9d47f6806b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830337190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1830337190
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2058174476
Short name T863
Test name
Test status
Simulation time 94771865 ps
CPU time 2.81 seconds
Started Feb 21 12:28:54 PM PST 24
Finished Feb 21 12:28:59 PM PST 24
Peak memory 213940 kb
Host smart-5ee42f23-169e-497e-9239-6bcc40f028af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058174476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2058174476
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.249881010
Short name T248
Test name
Test status
Simulation time 164570083 ps
CPU time 1.49 seconds
Started Feb 21 12:28:54 PM PST 24
Finished Feb 21 12:28:58 PM PST 24
Peak memory 205780 kb
Host smart-176121fb-9d2a-4539-883b-6425972945fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249881010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.249881010
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.91097305
Short name T809
Test name
Test status
Simulation time 139511151 ps
CPU time 1.32 seconds
Started Feb 21 12:52:17 PM PST 24
Finished Feb 21 12:52:19 PM PST 24
Peak memory 215112 kb
Host smart-0e3f3bc5-728f-4905-88a2-b80df18adc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91097305 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.91097305
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.4137854649
Short name T519
Test name
Test status
Simulation time 28108063 ps
CPU time 0.85 seconds
Started Feb 21 12:52:12 PM PST 24
Finished Feb 21 12:52:13 PM PST 24
Peak memory 206212 kb
Host smart-db69a497-01f2-4658-a57d-d2af8f379036
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137854649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.4137854649
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.1622400536
Short name T508
Test name
Test status
Simulation time 18998511 ps
CPU time 0.85 seconds
Started Feb 21 12:52:24 PM PST 24
Finished Feb 21 12:52:25 PM PST 24
Peak memory 214960 kb
Host smart-a66665a8-1a8c-41d1-b3cb-ce3ecba8f73d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622400536 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1622400536
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.499383552
Short name T77
Test name
Test status
Simulation time 49729781 ps
CPU time 1.05 seconds
Started Feb 21 12:52:26 PM PST 24
Finished Feb 21 12:52:28 PM PST 24
Peak memory 216052 kb
Host smart-4685ca18-dd6f-4cbb-91e3-0014783ec8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499383552 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.499383552
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1693716228
Short name T419
Test name
Test status
Simulation time 74992970 ps
CPU time 1.11 seconds
Started Feb 21 12:52:13 PM PST 24
Finished Feb 21 12:52:14 PM PST 24
Peak memory 216264 kb
Host smart-d10458ec-88b6-49bd-89dd-87b4f4cc20dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693716228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1693716228
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.3817733156
Short name T609
Test name
Test status
Simulation time 28180636 ps
CPU time 1.04 seconds
Started Feb 21 12:52:21 PM PST 24
Finished Feb 21 12:52:22 PM PST 24
Peak memory 232088 kb
Host smart-24f69e0b-fd1e-4c33-9e49-2b77f5d6df34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817733156 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3817733156
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2578575398
Short name T45
Test name
Test status
Simulation time 531024991 ps
CPU time 5.69 seconds
Started Feb 21 12:52:14 PM PST 24
Finished Feb 21 12:52:20 PM PST 24
Peak memory 235976 kb
Host smart-3a5408c7-921b-4c1b-bfae-55920e86e9e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578575398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2578575398
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.4171660797
Short name T796
Test name
Test status
Simulation time 24640700 ps
CPU time 0.95 seconds
Started Feb 21 12:52:17 PM PST 24
Finished Feb 21 12:52:18 PM PST 24
Peak memory 214964 kb
Host smart-5a85bdca-820e-4c30-bdd7-1eb669a4dead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171660797 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.4171660797
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_alert.68796845
Short name T20
Test name
Test status
Simulation time 303570121 ps
CPU time 1.28 seconds
Started Feb 21 12:52:26 PM PST 24
Finished Feb 21 12:52:28 PM PST 24
Peak memory 215068 kb
Host smart-76ea632d-eb4a-498b-a158-074e161e2b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68796845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.68796845
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.602004816
Short name T576
Test name
Test status
Simulation time 11134522 ps
CPU time 0.8 seconds
Started Feb 21 12:52:17 PM PST 24
Finished Feb 21 12:52:18 PM PST 24
Peak memory 205132 kb
Host smart-e2078442-f28a-4858-a42c-059982d7df8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602004816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.602004816
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.2745304995
Short name T99
Test name
Test status
Simulation time 21973645 ps
CPU time 0.89 seconds
Started Feb 21 12:52:23 PM PST 24
Finished Feb 21 12:52:24 PM PST 24
Peak memory 215272 kb
Host smart-f8212b2c-0caf-48db-8353-b56969f6f117
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745304995 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2745304995
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.3638596475
Short name T591
Test name
Test status
Simulation time 99331689 ps
CPU time 1.09 seconds
Started Feb 21 12:52:21 PM PST 24
Finished Feb 21 12:52:22 PM PST 24
Peak memory 217264 kb
Host smart-e3662281-3a85-4102-a9b2-dc903d0ef90b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638596475 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.3638596475
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.893991512
Short name T339
Test name
Test status
Simulation time 29770239 ps
CPU time 0.93 seconds
Started Feb 21 12:52:14 PM PST 24
Finished Feb 21 12:52:15 PM PST 24
Peak memory 217240 kb
Host smart-c33f61b0-109e-41b3-b131-f59b570daf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893991512 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.893991512
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1894254898
Short name T21
Test name
Test status
Simulation time 551789572 ps
CPU time 6.16 seconds
Started Feb 21 12:52:14 PM PST 24
Finished Feb 21 12:52:20 PM PST 24
Peak memory 235028 kb
Host smart-eddc6d11-29ec-4eaf-b4b6-334e8f29a121
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894254898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1894254898
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.3350336643
Short name T387
Test name
Test status
Simulation time 24059764 ps
CPU time 0.98 seconds
Started Feb 21 12:52:16 PM PST 24
Finished Feb 21 12:52:17 PM PST 24
Peak memory 214632 kb
Host smart-ed0a568f-4612-4f1f-9bcd-86d69b821420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350336643 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3350336643
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1578622845
Short name T614
Test name
Test status
Simulation time 196926944 ps
CPU time 1.51 seconds
Started Feb 21 12:52:14 PM PST 24
Finished Feb 21 12:52:15 PM PST 24
Peak memory 214544 kb
Host smart-8ea1669c-84a6-43e8-80f1-9dd17419a6a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578622845 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1578622845
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1865116269
Short name T379
Test name
Test status
Simulation time 53879902573 ps
CPU time 731.32 seconds
Started Feb 21 12:52:18 PM PST 24
Finished Feb 21 01:04:29 PM PST 24
Peak memory 217376 kb
Host smart-74f31f9f-0fc1-422a-8776-7680d98377d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865116269 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1865116269
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.519700038
Short name T136
Test name
Test status
Simulation time 24048820 ps
CPU time 1.16 seconds
Started Feb 21 12:52:51 PM PST 24
Finished Feb 21 12:52:53 PM PST 24
Peak memory 215132 kb
Host smart-68114fa5-8269-435a-aa65-481250e7b3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519700038 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.519700038
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2808196686
Short name T830
Test name
Test status
Simulation time 39706249 ps
CPU time 0.88 seconds
Started Feb 21 12:52:54 PM PST 24
Finished Feb 21 12:52:55 PM PST 24
Peak memory 206320 kb
Host smart-b8cf4a2f-1b15-428e-8d91-3ab70e37c9b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808196686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2808196686
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.237668762
Short name T539
Test name
Test status
Simulation time 20521616 ps
CPU time 0.82 seconds
Started Feb 21 12:52:50 PM PST 24
Finished Feb 21 12:52:51 PM PST 24
Peak memory 214824 kb
Host smart-c36383cc-4e52-4707-add3-f6d668bd5892
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237668762 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.237668762
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.1846126471
Short name T81
Test name
Test status
Simulation time 44439855 ps
CPU time 0.95 seconds
Started Feb 21 12:52:57 PM PST 24
Finished Feb 21 12:52:59 PM PST 24
Peak memory 222364 kb
Host smart-321e4cef-545a-451a-81e4-6bda9bde190f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846126471 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1846126471
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1255749807
Short name T628
Test name
Test status
Simulation time 21486153 ps
CPU time 1.13 seconds
Started Feb 21 12:52:42 PM PST 24
Finished Feb 21 12:52:43 PM PST 24
Peak memory 217368 kb
Host smart-055a3279-6d6d-49b3-9ffc-038c80c0b2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255749807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1255749807
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_smoke.822890093
Short name T392
Test name
Test status
Simulation time 20714625 ps
CPU time 0.95 seconds
Started Feb 21 12:52:41 PM PST 24
Finished Feb 21 12:52:43 PM PST 24
Peak memory 214740 kb
Host smart-63aecff3-1468-414e-b24d-9edbda81014c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822890093 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.822890093
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.398338701
Short name T633
Test name
Test status
Simulation time 926491674 ps
CPU time 5.06 seconds
Started Feb 21 12:52:52 PM PST 24
Finished Feb 21 12:52:57 PM PST 24
Peak memory 215856 kb
Host smart-b56e927f-739d-429f-819e-e3677d10e184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398338701 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.398338701
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1145342778
Short name T806
Test name
Test status
Simulation time 51142747915 ps
CPU time 343.74 seconds
Started Feb 21 12:52:51 PM PST 24
Finished Feb 21 12:58:36 PM PST 24
Peak memory 218100 kb
Host smart-b9f97798-cf4f-4e85-b8b2-309b993d29ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145342778 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1145342778
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.edn_genbits.1031939625
Short name T663
Test name
Test status
Simulation time 70298124 ps
CPU time 2.2 seconds
Started Feb 21 12:54:48 PM PST 24
Finished Feb 21 12:54:51 PM PST 24
Peak memory 218272 kb
Host smart-66c97b02-3819-4e31-bcad-10dd3ead18a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031939625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1031939625
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.464876722
Short name T415
Test name
Test status
Simulation time 55099155 ps
CPU time 1.19 seconds
Started Feb 21 12:54:49 PM PST 24
Finished Feb 21 12:54:51 PM PST 24
Peak memory 216800 kb
Host smart-c19b89e1-aef3-4235-b029-ddef09e3817a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464876722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.464876722
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3027166840
Short name T767
Test name
Test status
Simulation time 71716695 ps
CPU time 1.02 seconds
Started Feb 21 12:54:48 PM PST 24
Finished Feb 21 12:54:50 PM PST 24
Peak memory 216132 kb
Host smart-04473391-03c4-42b9-afa8-f718890a07a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027166840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3027166840
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.57255294
Short name T300
Test name
Test status
Simulation time 180149717 ps
CPU time 1.11 seconds
Started Feb 21 12:54:48 PM PST 24
Finished Feb 21 12:54:50 PM PST 24
Peak memory 217652 kb
Host smart-f0f61131-e646-4d7e-b2ba-ab1c3c3466ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57255294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.57255294
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1775632690
Short name T690
Test name
Test status
Simulation time 56210769 ps
CPU time 1.27 seconds
Started Feb 21 12:54:47 PM PST 24
Finished Feb 21 12:54:50 PM PST 24
Peak memory 217140 kb
Host smart-58ac023e-3ee5-4ec3-baf3-16e6d1058e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775632690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1775632690
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.3310249655
Short name T584
Test name
Test status
Simulation time 37604713 ps
CPU time 1.66 seconds
Started Feb 21 12:54:52 PM PST 24
Finished Feb 21 12:54:54 PM PST 24
Peak memory 217220 kb
Host smart-76b39b54-954a-4434-aa50-eb6367b2a953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310249655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3310249655
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.1981037870
Short name T194
Test name
Test status
Simulation time 60343414 ps
CPU time 1.87 seconds
Started Feb 21 12:54:51 PM PST 24
Finished Feb 21 12:54:53 PM PST 24
Peak memory 217436 kb
Host smart-e2452212-ee9b-4921-92d0-358c03ba6584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981037870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1981037870
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.981837037
Short name T489
Test name
Test status
Simulation time 24409205 ps
CPU time 1.18 seconds
Started Feb 21 12:52:51 PM PST 24
Finished Feb 21 12:52:53 PM PST 24
Peak memory 215236 kb
Host smart-b697894c-d126-4c62-a6d1-d46730f6c947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981837037 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.981837037
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.750001582
Short name T754
Test name
Test status
Simulation time 21251690 ps
CPU time 0.86 seconds
Started Feb 21 12:52:52 PM PST 24
Finished Feb 21 12:52:54 PM PST 24
Peak memory 215124 kb
Host smart-8ed0d0e0-c7ba-40e5-bce5-45fd1693cbdb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750001582 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.750001582
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1021379026
Short name T839
Test name
Test status
Simulation time 113304025 ps
CPU time 1.05 seconds
Started Feb 21 12:52:50 PM PST 24
Finished Feb 21 12:52:52 PM PST 24
Peak memory 215600 kb
Host smart-b3e17fc8-15ba-415f-98c1-9494522c4d02
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021379026 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1021379026
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.2311184255
Short name T90
Test name
Test status
Simulation time 21958394 ps
CPU time 0.99 seconds
Started Feb 21 12:52:51 PM PST 24
Finished Feb 21 12:52:53 PM PST 24
Peak memory 222416 kb
Host smart-50551273-a1e6-4415-b57e-543f0c983cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311184255 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2311184255
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.3641675174
Short name T476
Test name
Test status
Simulation time 93993885 ps
CPU time 1.11 seconds
Started Feb 21 12:52:53 PM PST 24
Finished Feb 21 12:52:55 PM PST 24
Peak memory 216176 kb
Host smart-13ba7ba6-651d-423d-a949-14c2b5084c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641675174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3641675174
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.4063300089
Short name T763
Test name
Test status
Simulation time 20736235 ps
CPU time 1.02 seconds
Started Feb 21 12:52:52 PM PST 24
Finished Feb 21 12:52:54 PM PST 24
Peak memory 215072 kb
Host smart-94a07828-b380-4c90-afa6-c1c758b1acab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063300089 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.4063300089
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.565651568
Short name T413
Test name
Test status
Simulation time 44771114 ps
CPU time 0.95 seconds
Started Feb 21 12:52:51 PM PST 24
Finished Feb 21 12:52:53 PM PST 24
Peak memory 214792 kb
Host smart-1814a967-8d8b-4428-9ef6-fe33bccc290b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565651568 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.565651568
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.3701252573
Short name T574
Test name
Test status
Simulation time 482729803 ps
CPU time 3.02 seconds
Started Feb 21 12:52:59 PM PST 24
Finished Feb 21 12:53:04 PM PST 24
Peak memory 214768 kb
Host smart-07a8a94c-2a95-4ac7-8488-38889c9a5ffe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701252573 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3701252573
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.4053373233
Short name T662
Test name
Test status
Simulation time 617307044146 ps
CPU time 933.58 seconds
Started Feb 21 12:52:52 PM PST 24
Finished Feb 21 01:08:26 PM PST 24
Peak memory 223212 kb
Host smart-d86dbc4b-ce9d-42fa-9b00-0dbc7c37382e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053373233 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.4053373233
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.1917303327
Short name T608
Test name
Test status
Simulation time 48980073 ps
CPU time 1.11 seconds
Started Feb 21 12:54:49 PM PST 24
Finished Feb 21 12:54:51 PM PST 24
Peak memory 215964 kb
Host smart-bbfc8cbc-4a23-420f-b7e5-45649b483e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917303327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1917303327
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.2053585925
Short name T729
Test name
Test status
Simulation time 128534522 ps
CPU time 1.31 seconds
Started Feb 21 12:54:51 PM PST 24
Finished Feb 21 12:54:53 PM PST 24
Peak memory 217560 kb
Host smart-6c08edc5-8d6f-441e-9be6-cb160ccb6c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053585925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2053585925
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2705739389
Short name T490
Test name
Test status
Simulation time 181810521 ps
CPU time 2.2 seconds
Started Feb 21 12:55:02 PM PST 24
Finished Feb 21 12:55:07 PM PST 24
Peak memory 218424 kb
Host smart-841fb83d-5b93-4cbe-bef5-dbf1562aae3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705739389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2705739389
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.3298637696
Short name T550
Test name
Test status
Simulation time 209806276 ps
CPU time 1.61 seconds
Started Feb 21 12:54:55 PM PST 24
Finished Feb 21 12:54:57 PM PST 24
Peak memory 217648 kb
Host smart-92789e37-abe6-4037-825e-e3ca6b735888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298637696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3298637696
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.971718596
Short name T286
Test name
Test status
Simulation time 62093851 ps
CPU time 1.59 seconds
Started Feb 21 12:54:38 PM PST 24
Finished Feb 21 12:54:41 PM PST 24
Peak memory 217496 kb
Host smart-258fbb38-572c-4d81-9096-e199c0587943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971718596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.971718596
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.4265316208
Short name T409
Test name
Test status
Simulation time 50194684 ps
CPU time 1.29 seconds
Started Feb 21 12:54:56 PM PST 24
Finished Feb 21 12:54:57 PM PST 24
Peak memory 217104 kb
Host smart-6d0f4331-df1a-4f36-9c08-c22e118eca2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265316208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.4265316208
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.144518692
Short name T14
Test name
Test status
Simulation time 74248199 ps
CPU time 1.26 seconds
Started Feb 21 12:55:01 PM PST 24
Finished Feb 21 12:55:05 PM PST 24
Peak memory 218016 kb
Host smart-0f1b563d-42ca-4542-9476-cd8dc5616576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144518692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.144518692
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.3286708509
Short name T463
Test name
Test status
Simulation time 82101214 ps
CPU time 1.6 seconds
Started Feb 21 12:54:57 PM PST 24
Finished Feb 21 12:55:00 PM PST 24
Peak memory 218164 kb
Host smart-45446981-77ad-4b22-8605-edecde29c933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286708509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3286708509
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3323269971
Short name T347
Test name
Test status
Simulation time 27770594 ps
CPU time 1.09 seconds
Started Feb 21 12:54:54 PM PST 24
Finished Feb 21 12:54:56 PM PST 24
Peak memory 215744 kb
Host smart-dd236f42-062f-4a4f-9793-a233a9126863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323269971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3323269971
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.772094066
Short name T238
Test name
Test status
Simulation time 16802419 ps
CPU time 0.83 seconds
Started Feb 21 12:52:59 PM PST 24
Finished Feb 21 12:53:02 PM PST 24
Peak memory 206260 kb
Host smart-03d010a8-25c5-45a5-8725-cc68f69d6d37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772094066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.772094066
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2068589471
Short name T110
Test name
Test status
Simulation time 81923632 ps
CPU time 0.84 seconds
Started Feb 21 12:52:58 PM PST 24
Finished Feb 21 12:53:00 PM PST 24
Peak memory 215136 kb
Host smart-bb515c8c-465e-4209-a0b7-25bbc6414586
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068589471 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2068589471
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1342934863
Short name T69
Test name
Test status
Simulation time 395479809 ps
CPU time 1.08 seconds
Started Feb 21 12:52:53 PM PST 24
Finished Feb 21 12:52:54 PM PST 24
Peak memory 215836 kb
Host smart-356482e4-1a3e-4daa-8ffd-87e301cb6f67
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342934863 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1342934863
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.1932593009
Short name T477
Test name
Test status
Simulation time 19259403 ps
CPU time 1.18 seconds
Started Feb 21 12:52:56 PM PST 24
Finished Feb 21 12:52:57 PM PST 24
Peak memory 222268 kb
Host smart-f0408e48-a7f3-4d19-aeff-c1c84a41caba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932593009 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1932593009
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.463292784
Short name T752
Test name
Test status
Simulation time 30380245 ps
CPU time 1.11 seconds
Started Feb 21 12:52:58 PM PST 24
Finished Feb 21 12:53:00 PM PST 24
Peak memory 217464 kb
Host smart-3627ea68-1f98-49d5-b790-fc8f186da55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463292784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.463292784
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1431107993
Short name T363
Test name
Test status
Simulation time 39189464 ps
CPU time 0.86 seconds
Started Feb 21 12:52:58 PM PST 24
Finished Feb 21 12:52:59 PM PST 24
Peak memory 214684 kb
Host smart-77b122ff-756d-43d8-be7a-a3bcb93866c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431107993 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1431107993
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.1696868450
Short name T206
Test name
Test status
Simulation time 67474665 ps
CPU time 0.89 seconds
Started Feb 21 12:52:51 PM PST 24
Finished Feb 21 12:52:53 PM PST 24
Peak memory 214736 kb
Host smart-4e742280-3406-4bd5-ae61-694431f78224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696868450 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1696868450
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.968325631
Short name T401
Test name
Test status
Simulation time 355847670 ps
CPU time 2.61 seconds
Started Feb 21 12:52:51 PM PST 24
Finished Feb 21 12:52:54 PM PST 24
Peak memory 218660 kb
Host smart-af7a1af4-0b10-43e8-b357-2a96fbdfb4f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968325631 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.968325631
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2994215381
Short name T358
Test name
Test status
Simulation time 9806403589 ps
CPU time 245.39 seconds
Started Feb 21 12:52:48 PM PST 24
Finished Feb 21 12:56:54 PM PST 24
Peak memory 223032 kb
Host smart-9bd54e80-8db8-4147-9ba6-ff604affcd3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994215381 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2994215381
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.3037975778
Short name T197
Test name
Test status
Simulation time 39785121 ps
CPU time 1.21 seconds
Started Feb 21 12:54:48 PM PST 24
Finished Feb 21 12:54:50 PM PST 24
Peak memory 215896 kb
Host smart-89f01103-183c-450b-8817-4a678a83222f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037975778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3037975778
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.621930311
Short name T242
Test name
Test status
Simulation time 67628925 ps
CPU time 1.61 seconds
Started Feb 21 12:54:39 PM PST 24
Finished Feb 21 12:54:42 PM PST 24
Peak memory 215968 kb
Host smart-274cbfa3-9b50-421f-b598-7d920578e496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621930311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.621930311
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.1348823391
Short name T747
Test name
Test status
Simulation time 47207637 ps
CPU time 1.59 seconds
Started Feb 21 12:54:49 PM PST 24
Finished Feb 21 12:54:52 PM PST 24
Peak memory 216036 kb
Host smart-0ef572e8-a3b6-4c64-9fba-2cde2030a3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348823391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1348823391
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.1848179212
Short name T251
Test name
Test status
Simulation time 70757581 ps
CPU time 1.13 seconds
Started Feb 21 12:54:51 PM PST 24
Finished Feb 21 12:54:53 PM PST 24
Peak memory 216296 kb
Host smart-24a444a3-7e18-41ad-afc4-a4cef7e44be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848179212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1848179212
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.1964632113
Short name T583
Test name
Test status
Simulation time 97570989 ps
CPU time 1.29 seconds
Started Feb 21 12:54:51 PM PST 24
Finished Feb 21 12:54:53 PM PST 24
Peak memory 217392 kb
Host smart-f6696ebf-9f3e-4c29-9038-6fdab91c1097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964632113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1964632113
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.2570734512
Short name T551
Test name
Test status
Simulation time 75881719 ps
CPU time 1.1 seconds
Started Feb 21 12:54:49 PM PST 24
Finished Feb 21 12:54:51 PM PST 24
Peak memory 217296 kb
Host smart-96941b95-74f1-4864-a614-b04ec958d62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570734512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2570734512
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.290678852
Short name T499
Test name
Test status
Simulation time 34945069 ps
CPU time 1.1 seconds
Started Feb 21 12:54:49 PM PST 24
Finished Feb 21 12:54:51 PM PST 24
Peak memory 216312 kb
Host smart-d3341e8e-1794-45f3-8609-3d5a92fbc814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290678852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.290678852
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.1393372175
Short name T786
Test name
Test status
Simulation time 64903811 ps
CPU time 0.98 seconds
Started Feb 21 12:54:47 PM PST 24
Finished Feb 21 12:54:50 PM PST 24
Peak memory 214804 kb
Host smart-857b84a9-3cd9-4fda-a6d0-71ce7faaf552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393372175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1393372175
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3665489193
Short name T267
Test name
Test status
Simulation time 428663476 ps
CPU time 1.56 seconds
Started Feb 21 12:52:52 PM PST 24
Finished Feb 21 12:52:54 PM PST 24
Peak memory 215000 kb
Host smart-6161e584-d027-4d49-bc86-2a6cdf992795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665489193 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3665489193
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3391839974
Short name T472
Test name
Test status
Simulation time 14051363 ps
CPU time 0.91 seconds
Started Feb 21 12:52:50 PM PST 24
Finished Feb 21 12:52:52 PM PST 24
Peak memory 206256 kb
Host smart-db8cbabc-a575-444f-b694-7bc30085b738
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391839974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3391839974
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.992162620
Short name T61
Test name
Test status
Simulation time 60235674 ps
CPU time 1.19 seconds
Started Feb 21 12:52:50 PM PST 24
Finished Feb 21 12:52:51 PM PST 24
Peak memory 215788 kb
Host smart-406fc542-1711-46f4-ae56-c9f9e9662652
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992162620 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.992162620
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1628551812
Short name T467
Test name
Test status
Simulation time 38963266 ps
CPU time 1.03 seconds
Started Feb 21 12:52:51 PM PST 24
Finished Feb 21 12:52:53 PM PST 24
Peak memory 216392 kb
Host smart-4433bd84-9d4a-43b3-8b1a-9ef9681ff38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628551812 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1628551812
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.466960379
Short name T209
Test name
Test status
Simulation time 46158099 ps
CPU time 1.66 seconds
Started Feb 21 12:52:59 PM PST 24
Finished Feb 21 12:53:03 PM PST 24
Peak memory 217184 kb
Host smart-94814d7e-8b26-4078-a012-88d38768b4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466960379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.466960379
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.3267956988
Short name T191
Test name
Test status
Simulation time 41757396 ps
CPU time 0.87 seconds
Started Feb 21 12:52:52 PM PST 24
Finished Feb 21 12:52:54 PM PST 24
Peak memory 215072 kb
Host smart-b04805a8-f3c4-420c-92fe-bc6c89a54a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267956988 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3267956988
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.4157062823
Short name T589
Test name
Test status
Simulation time 24038716 ps
CPU time 0.86 seconds
Started Feb 21 12:52:53 PM PST 24
Finished Feb 21 12:52:54 PM PST 24
Peak memory 214656 kb
Host smart-0dbee44e-4271-4413-9c29-d01582359123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157062823 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.4157062823
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3285918013
Short name T399
Test name
Test status
Simulation time 446567474 ps
CPU time 1.76 seconds
Started Feb 21 12:52:54 PM PST 24
Finished Feb 21 12:52:56 PM PST 24
Peak memory 215720 kb
Host smart-84f6947d-fc78-43c1-988f-db02ab8ecd9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285918013 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3285918013
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/131.edn_genbits.3417007520
Short name T706
Test name
Test status
Simulation time 227169310 ps
CPU time 2.35 seconds
Started Feb 21 12:54:45 PM PST 24
Finished Feb 21 12:54:47 PM PST 24
Peak memory 218540 kb
Host smart-8a62727e-317e-4a5d-8b57-cb9ab1434a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417007520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3417007520
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.2485077851
Short name T433
Test name
Test status
Simulation time 29773550 ps
CPU time 1.02 seconds
Started Feb 21 12:54:51 PM PST 24
Finished Feb 21 12:54:52 PM PST 24
Peak memory 216128 kb
Host smart-2e2a86dd-b704-47df-8bcf-e2085e74e43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485077851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2485077851
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.1193925010
Short name T430
Test name
Test status
Simulation time 39083937 ps
CPU time 1.33 seconds
Started Feb 21 12:54:46 PM PST 24
Finished Feb 21 12:54:47 PM PST 24
Peak memory 218524 kb
Host smart-0789f01c-5f0e-484d-9759-c5fcbddb8b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193925010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1193925010
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.2560828381
Short name T512
Test name
Test status
Simulation time 64360195 ps
CPU time 1.17 seconds
Started Feb 21 12:54:37 PM PST 24
Finished Feb 21 12:54:40 PM PST 24
Peak memory 216120 kb
Host smart-c73cc03d-ae08-4c61-b612-f90f5463365a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560828381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2560828381
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.3309421119
Short name T166
Test name
Test status
Simulation time 69699527 ps
CPU time 1.29 seconds
Started Feb 21 12:54:42 PM PST 24
Finished Feb 21 12:54:44 PM PST 24
Peak memory 217328 kb
Host smart-cbc43a54-21c9-4066-b83b-195d41eada1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309421119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3309421119
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.526420717
Short name T585
Test name
Test status
Simulation time 34279481 ps
CPU time 1.38 seconds
Started Feb 21 12:54:51 PM PST 24
Finished Feb 21 12:54:53 PM PST 24
Peak memory 217112 kb
Host smart-2efb883e-01d4-452f-9047-40d928a9dcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526420717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.526420717
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.669305906
Short name T426
Test name
Test status
Simulation time 79118573 ps
CPU time 1.79 seconds
Started Feb 21 12:54:44 PM PST 24
Finished Feb 21 12:54:46 PM PST 24
Peak memory 216124 kb
Host smart-a0e4d91d-8d91-441d-909e-32a6bbb663bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669305906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.669305906
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.3959198278
Short name T816
Test name
Test status
Simulation time 52036607 ps
CPU time 1.69 seconds
Started Feb 21 12:54:44 PM PST 24
Finished Feb 21 12:54:46 PM PST 24
Peak memory 217404 kb
Host smart-ce9300ac-88b1-4447-8f06-8f19c61cd501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959198278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3959198278
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.1094607116
Short name T253
Test name
Test status
Simulation time 54567955 ps
CPU time 1.88 seconds
Started Feb 21 12:54:49 PM PST 24
Finished Feb 21 12:54:51 PM PST 24
Peak memory 216992 kb
Host smart-3c98eecf-6ab4-4624-8bd4-5be4e0d62788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094607116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1094607116
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.4091118030
Short name T740
Test name
Test status
Simulation time 23449434 ps
CPU time 1.15 seconds
Started Feb 21 12:52:51 PM PST 24
Finished Feb 21 12:52:53 PM PST 24
Peak memory 215112 kb
Host smart-f0edddfb-f780-4e64-9284-53e54cd9855c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091118030 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.4091118030
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3521790995
Short name T596
Test name
Test status
Simulation time 61081567 ps
CPU time 0.88 seconds
Started Feb 21 12:52:53 PM PST 24
Finished Feb 21 12:52:54 PM PST 24
Peak memory 206276 kb
Host smart-fcb3d8da-97d6-4979-8d07-9d558ddd1556
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521790995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3521790995
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.3476510715
Short name T105
Test name
Test status
Simulation time 39771645 ps
CPU time 0.82 seconds
Started Feb 21 12:52:50 PM PST 24
Finished Feb 21 12:52:52 PM PST 24
Peak memory 215244 kb
Host smart-73d3cad0-84a1-4e52-8675-26cf0dd40025
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476510715 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3476510715
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2672096707
Short name T503
Test name
Test status
Simulation time 29355195 ps
CPU time 1.18 seconds
Started Feb 21 12:52:56 PM PST 24
Finished Feb 21 12:52:58 PM PST 24
Peak memory 218184 kb
Host smart-5f6ac5e1-6f6f-420b-8581-aec6a2c74f67
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672096707 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2672096707
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.97552018
Short name T758
Test name
Test status
Simulation time 25392061 ps
CPU time 0.89 seconds
Started Feb 21 12:52:53 PM PST 24
Finished Feb 21 12:52:55 PM PST 24
Peak memory 217692 kb
Host smart-34256bc2-7614-4c8a-9f7a-25221595616e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97552018 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.97552018
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1935100584
Short name T337
Test name
Test status
Simulation time 98634667 ps
CPU time 1.29 seconds
Started Feb 21 12:52:51 PM PST 24
Finished Feb 21 12:52:53 PM PST 24
Peak memory 217084 kb
Host smart-056821f2-2382-4efe-b4b3-333163c8fa3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935100584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1935100584
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_smoke.58309454
Short name T693
Test name
Test status
Simulation time 18219993 ps
CPU time 0.99 seconds
Started Feb 21 12:52:50 PM PST 24
Finished Feb 21 12:52:52 PM PST 24
Peak memory 214788 kb
Host smart-9a39ec20-65cb-4c18-8403-62bdc2c2ae35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58309454 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.58309454
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.987933850
Short name T579
Test name
Test status
Simulation time 243661392 ps
CPU time 2.93 seconds
Started Feb 21 12:52:54 PM PST 24
Finished Feb 21 12:52:57 PM PST 24
Peak memory 214752 kb
Host smart-5f7d9783-d306-4a57-a047-9ef49cbc1b23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987933850 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.987933850
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.873261084
Short name T459
Test name
Test status
Simulation time 401961989713 ps
CPU time 1012.31 seconds
Started Feb 21 12:52:54 PM PST 24
Finished Feb 21 01:09:47 PM PST 24
Peak memory 220660 kb
Host smart-79cae279-c023-4ad9-9de5-637a08b46b6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873261084 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.873261084
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.2682067497
Short name T310
Test name
Test status
Simulation time 35844117 ps
CPU time 1.45 seconds
Started Feb 21 12:54:48 PM PST 24
Finished Feb 21 12:54:50 PM PST 24
Peak memory 217360 kb
Host smart-7a3c6344-1a71-40df-b5cc-f403750cb1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682067497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2682067497
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.84224106
Short name T625
Test name
Test status
Simulation time 56606651 ps
CPU time 1.29 seconds
Started Feb 21 12:54:44 PM PST 24
Finished Feb 21 12:54:46 PM PST 24
Peak memory 217460 kb
Host smart-7f8f4760-5e8e-4b27-ad82-3431056bd4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84224106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.84224106
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.111824150
Short name T352
Test name
Test status
Simulation time 114479533 ps
CPU time 1.37 seconds
Started Feb 21 12:54:38 PM PST 24
Finished Feb 21 12:54:41 PM PST 24
Peak memory 217396 kb
Host smart-1214a716-b33b-4f0f-9bbb-21940b448d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111824150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.111824150
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.2100414192
Short name T545
Test name
Test status
Simulation time 30989349 ps
CPU time 1.17 seconds
Started Feb 21 12:54:44 PM PST 24
Finished Feb 21 12:54:46 PM PST 24
Peak memory 217348 kb
Host smart-0a690e3e-2161-4f00-b2f8-676eca764008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100414192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2100414192
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.1760537866
Short name T307
Test name
Test status
Simulation time 52354310 ps
CPU time 1.24 seconds
Started Feb 21 12:54:42 PM PST 24
Finished Feb 21 12:54:44 PM PST 24
Peak memory 217776 kb
Host smart-d0a95bd4-5dc5-44dc-8e4f-58e28ef82544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760537866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1760537866
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.2891386116
Short name T301
Test name
Test status
Simulation time 53562803 ps
CPU time 1.12 seconds
Started Feb 21 12:54:46 PM PST 24
Finished Feb 21 12:54:48 PM PST 24
Peak memory 216076 kb
Host smart-d6fe4e31-7093-43ec-9b3f-dab388517998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891386116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2891386116
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.1623951031
Short name T711
Test name
Test status
Simulation time 60456192 ps
CPU time 1.22 seconds
Started Feb 21 12:54:50 PM PST 24
Finished Feb 21 12:54:52 PM PST 24
Peak memory 216972 kb
Host smart-19cb9ee2-75e8-4449-ad4c-12d9baf15366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623951031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1623951031
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.3296460189
Short name T382
Test name
Test status
Simulation time 28370943 ps
CPU time 1.21 seconds
Started Feb 21 12:54:48 PM PST 24
Finished Feb 21 12:54:50 PM PST 24
Peak memory 217984 kb
Host smart-ed759e75-fa5d-4d67-b799-852b7446bef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296460189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3296460189
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.409412450
Short name T295
Test name
Test status
Simulation time 58840031 ps
CPU time 1.33 seconds
Started Feb 21 12:54:39 PM PST 24
Finished Feb 21 12:54:42 PM PST 24
Peak memory 217176 kb
Host smart-c81fe299-c9fa-4627-b958-a318f279fb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409412450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.409412450
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1646309750
Short name T725
Test name
Test status
Simulation time 51868489 ps
CPU time 1.38 seconds
Started Feb 21 12:54:50 PM PST 24
Finished Feb 21 12:54:52 PM PST 24
Peak memory 216936 kb
Host smart-2bf4d7af-9e34-4609-8865-c032829ec9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646309750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1646309750
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3706040971
Short name T134
Test name
Test status
Simulation time 108779309 ps
CPU time 1.23 seconds
Started Feb 21 12:52:52 PM PST 24
Finished Feb 21 12:52:54 PM PST 24
Peak memory 215136 kb
Host smart-960dbd7f-52be-42dd-b5cc-b29aa549bda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706040971 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3706040971
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.673484731
Short name T671
Test name
Test status
Simulation time 71390207 ps
CPU time 0.79 seconds
Started Feb 21 12:52:58 PM PST 24
Finished Feb 21 12:53:00 PM PST 24
Peak memory 205204 kb
Host smart-018c5e7b-69a1-4ace-ae32-9f46b87a8966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673484731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.673484731
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.192758871
Short name T163
Test name
Test status
Simulation time 31834692 ps
CPU time 0.83 seconds
Started Feb 21 12:52:56 PM PST 24
Finished Feb 21 12:52:57 PM PST 24
Peak memory 214924 kb
Host smart-561bb801-48a6-485f-bbac-5ef5b224a0e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192758871 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.192758871
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.51119131
Short name T62
Test name
Test status
Simulation time 31261706 ps
CPU time 1.17 seconds
Started Feb 21 12:52:56 PM PST 24
Finished Feb 21 12:52:57 PM PST 24
Peak memory 215864 kb
Host smart-13575110-9d72-4646-bf1d-fa78441e4912
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51119131 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_dis
able_auto_req_mode.51119131
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2135619916
Short name T16
Test name
Test status
Simulation time 28908376 ps
CPU time 1.3 seconds
Started Feb 21 12:52:57 PM PST 24
Finished Feb 21 12:52:59 PM PST 24
Peak memory 223488 kb
Host smart-088e6861-43ae-4715-b80b-068b6d846c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135619916 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2135619916
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.703671433
Short name T28
Test name
Test status
Simulation time 263026487 ps
CPU time 3.35 seconds
Started Feb 21 12:52:59 PM PST 24
Finished Feb 21 12:53:04 PM PST 24
Peak memory 217256 kb
Host smart-ad14ff48-6e00-4ae1-b02b-52aef0c9c38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703671433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.703671433
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.3537587813
Short name T822
Test name
Test status
Simulation time 16442580 ps
CPU time 0.93 seconds
Started Feb 21 12:52:52 PM PST 24
Finished Feb 21 12:52:53 PM PST 24
Peak memory 214736 kb
Host smart-38353c77-b04c-4bf5-b5e2-69ff3bea2cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537587813 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3537587813
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.246080408
Short name T692
Test name
Test status
Simulation time 464112658 ps
CPU time 4.56 seconds
Started Feb 21 12:52:58 PM PST 24
Finished Feb 21 12:53:04 PM PST 24
Peak memory 214780 kb
Host smart-5eb84757-e9ed-48b3-b8f2-9e658fb79603
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246080408 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.246080408
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2064810169
Short name T619
Test name
Test status
Simulation time 25368166434 ps
CPU time 583.9 seconds
Started Feb 21 12:52:54 PM PST 24
Finished Feb 21 01:02:38 PM PST 24
Peak memory 217300 kb
Host smart-2456776f-344d-45aa-a992-06032bd4b2a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064810169 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2064810169
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.262348551
Short name T634
Test name
Test status
Simulation time 48124521 ps
CPU time 1.26 seconds
Started Feb 21 12:54:43 PM PST 24
Finished Feb 21 12:54:45 PM PST 24
Peak memory 214688 kb
Host smart-cc30c92d-d0db-4dcf-9993-651382f59448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262348551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.262348551
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.380009518
Short name T617
Test name
Test status
Simulation time 42705988 ps
CPU time 1.18 seconds
Started Feb 21 12:54:42 PM PST 24
Finished Feb 21 12:54:44 PM PST 24
Peak memory 217016 kb
Host smart-b839b212-82f3-4673-b7af-a9a2aaa477ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380009518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.380009518
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.901222555
Short name T560
Test name
Test status
Simulation time 41216156 ps
CPU time 1.38 seconds
Started Feb 21 12:54:38 PM PST 24
Finished Feb 21 12:54:41 PM PST 24
Peak memory 215892 kb
Host smart-78a6f208-efce-48db-8f48-59ba8ba65492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901222555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.901222555
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.925829361
Short name T784
Test name
Test status
Simulation time 42217779 ps
CPU time 1.42 seconds
Started Feb 21 12:54:46 PM PST 24
Finished Feb 21 12:54:48 PM PST 24
Peak memory 217196 kb
Host smart-6511f885-d1b0-48e8-af1e-71c900f252ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925829361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.925829361
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.723262490
Short name T453
Test name
Test status
Simulation time 35288714 ps
CPU time 1.14 seconds
Started Feb 21 12:54:40 PM PST 24
Finished Feb 21 12:54:42 PM PST 24
Peak memory 218596 kb
Host smart-37c8cbad-e027-4fc3-9e92-29bfe2e94953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723262490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.723262490
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.1100626716
Short name T647
Test name
Test status
Simulation time 105542604 ps
CPU time 1.51 seconds
Started Feb 21 12:54:41 PM PST 24
Finished Feb 21 12:54:44 PM PST 24
Peak memory 217952 kb
Host smart-402ae12a-6051-4e18-9f46-5e6848d2108f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100626716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1100626716
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.112792959
Short name T196
Test name
Test status
Simulation time 54668594 ps
CPU time 1.2 seconds
Started Feb 21 12:54:42 PM PST 24
Finished Feb 21 12:54:44 PM PST 24
Peak memory 216152 kb
Host smart-3594f0d3-06f2-46c1-9cf8-3b291f3899eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112792959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.112792959
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.3293833311
Short name T160
Test name
Test status
Simulation time 31988740 ps
CPU time 1.21 seconds
Started Feb 21 12:54:46 PM PST 24
Finished Feb 21 12:54:48 PM PST 24
Peak memory 216064 kb
Host smart-81fbb586-c355-4476-a432-e1a7a7aaca8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293833311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3293833311
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.2408677542
Short name T636
Test name
Test status
Simulation time 46513303 ps
CPU time 1.34 seconds
Started Feb 21 12:54:49 PM PST 24
Finished Feb 21 12:54:51 PM PST 24
Peak memory 217148 kb
Host smart-f8681338-544a-4f68-ba35-dceff2f79b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408677542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2408677542
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.1372493304
Short name T475
Test name
Test status
Simulation time 93915109 ps
CPU time 1.13 seconds
Started Feb 21 12:54:47 PM PST 24
Finished Feb 21 12:54:50 PM PST 24
Peak memory 216052 kb
Host smart-196832ba-e56a-445a-86d9-979b31d3fe8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372493304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1372493304
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3586462564
Short name T137
Test name
Test status
Simulation time 29971636 ps
CPU time 1.26 seconds
Started Feb 21 12:52:56 PM PST 24
Finished Feb 21 12:52:57 PM PST 24
Peak memory 215096 kb
Host smart-6d341d0a-a942-4fdb-9200-e21e34fb3b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586462564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3586462564
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2114195236
Short name T697
Test name
Test status
Simulation time 16032255 ps
CPU time 0.91 seconds
Started Feb 21 12:53:00 PM PST 24
Finished Feb 21 12:53:02 PM PST 24
Peak memory 206272 kb
Host smart-71e2c460-33c3-4da1-8b0e-4467190b5e5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114195236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2114195236
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2525674552
Short name T541
Test name
Test status
Simulation time 23594061 ps
CPU time 0.92 seconds
Started Feb 21 12:53:01 PM PST 24
Finished Feb 21 12:53:03 PM PST 24
Peak memory 215264 kb
Host smart-1eab71ff-1317-4772-836e-d01ab2bc3812
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525674552 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2525674552
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.4061460659
Short name T676
Test name
Test status
Simulation time 28667461 ps
CPU time 0.82 seconds
Started Feb 21 12:52:54 PM PST 24
Finished Feb 21 12:52:55 PM PST 24
Peak memory 217240 kb
Host smart-6efe1588-5ce4-4a92-bb2b-9d9647127a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061460659 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.4061460659
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.1377438511
Short name T779
Test name
Test status
Simulation time 42857655 ps
CPU time 1.54 seconds
Started Feb 21 12:52:54 PM PST 24
Finished Feb 21 12:52:56 PM PST 24
Peak memory 217824 kb
Host smart-ae25fe6c-6af7-42d2-b1ac-8d5b568ebe2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377438511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1377438511
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3598072813
Short name T709
Test name
Test status
Simulation time 47846992 ps
CPU time 0.86 seconds
Started Feb 21 12:52:55 PM PST 24
Finished Feb 21 12:52:56 PM PST 24
Peak memory 214664 kb
Host smart-677a07f0-b3ae-49fa-88a8-7426ee1ca58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598072813 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3598072813
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.867083224
Short name T563
Test name
Test status
Simulation time 16175442 ps
CPU time 0.91 seconds
Started Feb 21 12:52:51 PM PST 24
Finished Feb 21 12:52:53 PM PST 24
Peak memory 214748 kb
Host smart-c2f942f9-cff2-424c-afd1-926c3de0fc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867083224 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.867083224
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2435660326
Short name T513
Test name
Test status
Simulation time 225285803 ps
CPU time 4.48 seconds
Started Feb 21 12:52:55 PM PST 24
Finished Feb 21 12:53:00 PM PST 24
Peak memory 218160 kb
Host smart-900ca134-a384-4507-98fe-5512d4607205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435660326 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2435660326
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.591932640
Short name T173
Test name
Test status
Simulation time 44439668121 ps
CPU time 560.8 seconds
Started Feb 21 12:52:50 PM PST 24
Finished Feb 21 01:02:12 PM PST 24
Peak memory 217156 kb
Host smart-42cc0b52-bbe4-490e-bd22-8b2918987dd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591932640 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.591932640
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.1534493682
Short name T435
Test name
Test status
Simulation time 97471344 ps
CPU time 1.17 seconds
Started Feb 21 12:54:37 PM PST 24
Finished Feb 21 12:54:41 PM PST 24
Peak memory 215972 kb
Host smart-1ed43f5f-6a42-49d3-8424-b851e6c4ceff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534493682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1534493682
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.332169424
Short name T437
Test name
Test status
Simulation time 41726677 ps
CPU time 1.31 seconds
Started Feb 21 12:54:46 PM PST 24
Finished Feb 21 12:54:48 PM PST 24
Peak memory 217140 kb
Host smart-20ca59e6-db64-4e2d-8b7f-0d3ac6708eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332169424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.332169424
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.2248601805
Short name T48
Test name
Test status
Simulation time 39099442 ps
CPU time 1.31 seconds
Started Feb 21 12:54:46 PM PST 24
Finished Feb 21 12:54:48 PM PST 24
Peak memory 216136 kb
Host smart-8c49171c-f50e-4b0b-b41e-8c8a5bd7957d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248601805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2248601805
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.301807509
Short name T403
Test name
Test status
Simulation time 69230742 ps
CPU time 1.34 seconds
Started Feb 21 12:54:42 PM PST 24
Finished Feb 21 12:54:44 PM PST 24
Peak memory 218836 kb
Host smart-cdf0feac-93a4-4a97-a95d-ad7c60433938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301807509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.301807509
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.2856591908
Short name T484
Test name
Test status
Simulation time 470258237 ps
CPU time 4.2 seconds
Started Feb 21 12:54:52 PM PST 24
Finished Feb 21 12:54:57 PM PST 24
Peak memory 216304 kb
Host smart-8c4bb847-5a28-4a29-8885-37e720538fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856591908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2856591908
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.3461302262
Short name T455
Test name
Test status
Simulation time 45488238 ps
CPU time 1.56 seconds
Started Feb 21 12:54:51 PM PST 24
Finished Feb 21 12:54:53 PM PST 24
Peak memory 217192 kb
Host smart-f3721287-2109-40c4-8c7f-ec1359b0e9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461302262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3461302262
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.3624691224
Short name T208
Test name
Test status
Simulation time 55450786 ps
CPU time 1.25 seconds
Started Feb 21 12:54:38 PM PST 24
Finished Feb 21 12:54:41 PM PST 24
Peak memory 217456 kb
Host smart-b4020bf6-504b-4250-a1ec-bdc9cb26f00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624691224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3624691224
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.1088527521
Short name T427
Test name
Test status
Simulation time 43408418 ps
CPU time 1.53 seconds
Started Feb 21 12:54:35 PM PST 24
Finished Feb 21 12:54:38 PM PST 24
Peak memory 218204 kb
Host smart-06d199b0-165b-4502-bff7-200efb6c72da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088527521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1088527521
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.2848332702
Short name T534
Test name
Test status
Simulation time 70825517 ps
CPU time 1.37 seconds
Started Feb 21 12:54:50 PM PST 24
Finished Feb 21 12:54:52 PM PST 24
Peak memory 217488 kb
Host smart-2963cf8e-0fc9-4560-bc3f-a9b2eb027567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848332702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2848332702
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1679756356
Short name T274
Test name
Test status
Simulation time 28712213 ps
CPU time 1.22 seconds
Started Feb 21 12:53:03 PM PST 24
Finished Feb 21 12:53:05 PM PST 24
Peak memory 215104 kb
Host smart-5037867b-ae42-487f-a6f7-35941c68a55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679756356 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1679756356
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2879432178
Short name T528
Test name
Test status
Simulation time 13037078 ps
CPU time 0.88 seconds
Started Feb 21 12:53:01 PM PST 24
Finished Feb 21 12:53:03 PM PST 24
Peak memory 205920 kb
Host smart-ac58cd07-390f-4bf4-afce-727b86c6b5ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879432178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2879432178
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3072922296
Short name T836
Test name
Test status
Simulation time 11596122 ps
CPU time 0.88 seconds
Started Feb 21 12:53:01 PM PST 24
Finished Feb 21 12:53:03 PM PST 24
Peak memory 215136 kb
Host smart-ce7d36b1-db82-4e6b-b92b-8d140a21d957
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072922296 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3072922296
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.4278272905
Short name T735
Test name
Test status
Simulation time 41328172 ps
CPU time 1.05 seconds
Started Feb 21 12:53:01 PM PST 24
Finished Feb 21 12:53:03 PM PST 24
Peak memory 216872 kb
Host smart-2eedb8e0-92a1-4a37-a6f9-08f1232efbe3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278272905 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.4278272905
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.179401469
Short name T66
Test name
Test status
Simulation time 26109953 ps
CPU time 1.1 seconds
Started Feb 21 12:53:02 PM PST 24
Finished Feb 21 12:53:04 PM PST 24
Peak memory 219364 kb
Host smart-22d719b3-9f45-4dd0-9ed6-f2f4b7aaf947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179401469 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.179401469
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2287770611
Short name T164
Test name
Test status
Simulation time 73619368 ps
CPU time 1.54 seconds
Started Feb 21 12:53:02 PM PST 24
Finished Feb 21 12:53:05 PM PST 24
Peak memory 217356 kb
Host smart-9e5ce072-2f8a-4652-8c7e-46283c42e1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287770611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2287770611
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.2606287173
Short name T731
Test name
Test status
Simulation time 93287115 ps
CPU time 0.79 seconds
Started Feb 21 12:53:01 PM PST 24
Finished Feb 21 12:53:04 PM PST 24
Peak memory 214828 kb
Host smart-df6b2077-98e6-4e88-ba8d-e331bcbb873a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606287173 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.2606287173
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.4245005541
Short name T678
Test name
Test status
Simulation time 53464029 ps
CPU time 0.96 seconds
Started Feb 21 12:52:59 PM PST 24
Finished Feb 21 12:53:02 PM PST 24
Peak memory 214748 kb
Host smart-d7669cb9-17a3-4d17-86d2-7169e70b50df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245005541 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.4245005541
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.4141810684
Short name T732
Test name
Test status
Simulation time 1360606694 ps
CPU time 3.36 seconds
Started Feb 21 12:53:01 PM PST 24
Finished Feb 21 12:53:05 PM PST 24
Peak memory 216144 kb
Host smart-a07afa64-581a-4455-88f4-4a225b65a8ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141810684 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.4141810684
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1998210041
Short name T666
Test name
Test status
Simulation time 52850857797 ps
CPU time 1332.08 seconds
Started Feb 21 12:53:00 PM PST 24
Finished Feb 21 01:15:14 PM PST 24
Peak memory 222264 kb
Host smart-5b1aa9d0-367a-4c92-8831-bbd32d639558
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998210041 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1998210041
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.2091295619
Short name T728
Test name
Test status
Simulation time 40150845 ps
CPU time 1.41 seconds
Started Feb 21 12:54:51 PM PST 24
Finished Feb 21 12:54:53 PM PST 24
Peak memory 217080 kb
Host smart-a1ebab5b-3565-406a-b89c-b507e4a78295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091295619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2091295619
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.2293412967
Short name T205
Test name
Test status
Simulation time 80708691 ps
CPU time 1.16 seconds
Started Feb 21 12:54:52 PM PST 24
Finished Feb 21 12:54:54 PM PST 24
Peak memory 217492 kb
Host smart-daa0180d-9548-4736-b2a6-8ccb5c252e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293412967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2293412967
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.4254337427
Short name T540
Test name
Test status
Simulation time 89884976 ps
CPU time 1.46 seconds
Started Feb 21 12:54:51 PM PST 24
Finished Feb 21 12:54:53 PM PST 24
Peak memory 216268 kb
Host smart-e806cad3-2f38-4fb9-9b90-a5ec5976a37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254337427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.4254337427
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.2340963508
Short name T721
Test name
Test status
Simulation time 60452968 ps
CPU time 1.33 seconds
Started Feb 21 12:54:47 PM PST 24
Finished Feb 21 12:54:48 PM PST 24
Peak memory 218108 kb
Host smart-65b59d3d-0c11-46a6-b361-293b93a2ec78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340963508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2340963508
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.934851549
Short name T167
Test name
Test status
Simulation time 33385660 ps
CPU time 1.45 seconds
Started Feb 21 12:54:54 PM PST 24
Finished Feb 21 12:54:56 PM PST 24
Peak memory 217184 kb
Host smart-725c6237-91c7-4847-af20-57229073f1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934851549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.934851549
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.3163196644
Short name T565
Test name
Test status
Simulation time 36631034 ps
CPU time 1.07 seconds
Started Feb 21 12:54:51 PM PST 24
Finished Feb 21 12:54:53 PM PST 24
Peak memory 217420 kb
Host smart-44ddcc02-9678-4086-8d79-2e6199813462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163196644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3163196644
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.3120673040
Short name T471
Test name
Test status
Simulation time 112219078 ps
CPU time 1.59 seconds
Started Feb 21 12:54:52 PM PST 24
Finished Feb 21 12:54:54 PM PST 24
Peak memory 217668 kb
Host smart-18c7fac4-b4bb-4e28-84a4-96bfb142449a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120673040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3120673040
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.1236900603
Short name T281
Test name
Test status
Simulation time 102062347 ps
CPU time 1.29 seconds
Started Feb 21 12:54:53 PM PST 24
Finished Feb 21 12:54:54 PM PST 24
Peak memory 217552 kb
Host smart-27d17775-0266-4fea-a593-a76df6ce556c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236900603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1236900603
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.1554133663
Short name T495
Test name
Test status
Simulation time 43356034 ps
CPU time 1.5 seconds
Started Feb 21 12:54:53 PM PST 24
Finished Feb 21 12:54:55 PM PST 24
Peak memory 214740 kb
Host smart-6571eb05-7551-4cb5-b3cd-06b66b153bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554133663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1554133663
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3666656317
Short name T272
Test name
Test status
Simulation time 30214934 ps
CPU time 1.22 seconds
Started Feb 21 12:53:06 PM PST 24
Finished Feb 21 12:53:08 PM PST 24
Peak memory 215168 kb
Host smart-3f081fd3-8189-4f9b-8feb-a94389a288c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666656317 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3666656317
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3875081822
Short name T398
Test name
Test status
Simulation time 36839509 ps
CPU time 0.94 seconds
Started Feb 21 12:53:07 PM PST 24
Finished Feb 21 12:53:08 PM PST 24
Peak memory 205548 kb
Host smart-262f7dc5-1797-4419-8803-057f24af2b5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875081822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3875081822
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3304465988
Short name T153
Test name
Test status
Simulation time 16033779 ps
CPU time 0.82 seconds
Started Feb 21 12:53:07 PM PST 24
Finished Feb 21 12:53:08 PM PST 24
Peak memory 215180 kb
Host smart-2959b2cc-032e-4cd3-bb37-240ec4898fdc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304465988 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3304465988
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2211901840
Short name T10
Test name
Test status
Simulation time 144912213 ps
CPU time 1.26 seconds
Started Feb 21 12:53:07 PM PST 24
Finished Feb 21 12:53:08 PM PST 24
Peak memory 218336 kb
Host smart-0bf63cd4-448d-438b-8800-63d2888a90a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211901840 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2211901840
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.3646778575
Short name T148
Test name
Test status
Simulation time 75151109 ps
CPU time 0.84 seconds
Started Feb 21 12:53:08 PM PST 24
Finished Feb 21 12:53:09 PM PST 24
Peak memory 217420 kb
Host smart-0ef3ca5d-3b80-4e5d-8a6e-1f0ca42dec55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646778575 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3646778575
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2555719882
Short name T543
Test name
Test status
Simulation time 43828921 ps
CPU time 1.7 seconds
Started Feb 21 12:53:08 PM PST 24
Finished Feb 21 12:53:10 PM PST 24
Peak memory 217408 kb
Host smart-92c2576b-50ca-4496-9162-1843da6cc466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555719882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2555719882
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.540221750
Short name T567
Test name
Test status
Simulation time 28238256 ps
CPU time 1.08 seconds
Started Feb 21 12:53:00 PM PST 24
Finished Feb 21 12:53:03 PM PST 24
Peak memory 222652 kb
Host smart-dbbb1790-189a-41d5-bdcd-f898c97fda3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540221750 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.540221750
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2475943835
Short name T745
Test name
Test status
Simulation time 98071800 ps
CPU time 0.94 seconds
Started Feb 21 12:53:00 PM PST 24
Finished Feb 21 12:53:02 PM PST 24
Peak memory 214712 kb
Host smart-f35822a3-80c2-47fa-b2b8-9f42265d2cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475943835 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2475943835
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1473323181
Short name T353
Test name
Test status
Simulation time 359674427 ps
CPU time 4.13 seconds
Started Feb 21 12:53:02 PM PST 24
Finished Feb 21 12:53:07 PM PST 24
Peak memory 217320 kb
Host smart-88231cf7-a64c-4cdb-b758-16505eef2c09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473323181 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1473323181
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1785621953
Short name T454
Test name
Test status
Simulation time 92340441982 ps
CPU time 2353.01 seconds
Started Feb 21 12:53:08 PM PST 24
Finished Feb 21 01:32:22 PM PST 24
Peak memory 230052 kb
Host smart-41e9f03d-23e2-4ab1-bb54-38d1d709022d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785621953 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1785621953
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.4099508328
Short name T362
Test name
Test status
Simulation time 33597936 ps
CPU time 1.04 seconds
Started Feb 21 12:54:53 PM PST 24
Finished Feb 21 12:54:54 PM PST 24
Peak memory 216372 kb
Host smart-9b07bba4-72d5-46f3-92d6-c68c60e7fc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099508328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.4099508328
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.1143010353
Short name T813
Test name
Test status
Simulation time 81122047 ps
CPU time 1.03 seconds
Started Feb 21 12:54:49 PM PST 24
Finished Feb 21 12:54:51 PM PST 24
Peak memory 216084 kb
Host smart-36b31000-3476-4961-ab0d-a8b041af2eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143010353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1143010353
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.2866813599
Short name T557
Test name
Test status
Simulation time 64663857 ps
CPU time 2.13 seconds
Started Feb 21 12:54:49 PM PST 24
Finished Feb 21 12:54:51 PM PST 24
Peak memory 216260 kb
Host smart-8470d1e4-f50b-4688-9b5c-030faf196c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866813599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2866813599
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.1357928093
Short name T580
Test name
Test status
Simulation time 45637146 ps
CPU time 1.4 seconds
Started Feb 21 12:54:49 PM PST 24
Finished Feb 21 12:54:51 PM PST 24
Peak memory 217316 kb
Host smart-cb835d51-239b-4372-adb8-586277582970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357928093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1357928093
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.3957194466
Short name T561
Test name
Test status
Simulation time 97311896 ps
CPU time 1.62 seconds
Started Feb 21 12:54:45 PM PST 24
Finished Feb 21 12:54:47 PM PST 24
Peak memory 217972 kb
Host smart-814fc14b-2b9a-48a4-952d-4ab9decc37a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957194466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3957194466
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.4105880597
Short name T210
Test name
Test status
Simulation time 145348837 ps
CPU time 2.33 seconds
Started Feb 21 12:54:49 PM PST 24
Finished Feb 21 12:54:52 PM PST 24
Peak memory 216232 kb
Host smart-a7a9db9d-15e2-4b28-bad9-7beee4d2f12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105880597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.4105880597
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.1515297594
Short name T369
Test name
Test status
Simulation time 87852223 ps
CPU time 1.11 seconds
Started Feb 21 12:54:49 PM PST 24
Finished Feb 21 12:54:51 PM PST 24
Peak memory 215500 kb
Host smart-61926ac6-786d-4915-a8e9-f1798d721135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515297594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1515297594
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.2162324560
Short name T357
Test name
Test status
Simulation time 25028796 ps
CPU time 1.07 seconds
Started Feb 21 12:54:45 PM PST 24
Finished Feb 21 12:54:46 PM PST 24
Peak memory 214740 kb
Host smart-75ab8e2d-1806-4049-acad-9c31e1bb742b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162324560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2162324560
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1470129509
Short name T737
Test name
Test status
Simulation time 45182295 ps
CPU time 1.2 seconds
Started Feb 21 12:54:48 PM PST 24
Finished Feb 21 12:54:50 PM PST 24
Peak memory 217344 kb
Host smart-684d1dc9-0b14-4e90-afdb-9540dc43833b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470129509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1470129509
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.632001294
Short name T440
Test name
Test status
Simulation time 37454459 ps
CPU time 1.37 seconds
Started Feb 21 12:54:55 PM PST 24
Finished Feb 21 12:54:57 PM PST 24
Peak memory 217060 kb
Host smart-32b48996-dcac-4061-8a48-5de3fa85c7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632001294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.632001294
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.3473597670
Short name T588
Test name
Test status
Simulation time 91109636 ps
CPU time 1.23 seconds
Started Feb 21 12:53:06 PM PST 24
Finished Feb 21 12:53:07 PM PST 24
Peak memory 215108 kb
Host smart-f9618ec1-0c77-40c5-9d23-3297e1126ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473597670 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3473597670
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2395196174
Short name T727
Test name
Test status
Simulation time 24318088 ps
CPU time 1.07 seconds
Started Feb 21 12:53:10 PM PST 24
Finished Feb 21 12:53:11 PM PST 24
Peak memory 206380 kb
Host smart-cc302f79-f5af-49ae-98df-2a6860f96d07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395196174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2395196174
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2719677825
Short name T83
Test name
Test status
Simulation time 38238132 ps
CPU time 0.74 seconds
Started Feb 21 12:53:02 PM PST 24
Finished Feb 21 12:53:04 PM PST 24
Peak memory 214856 kb
Host smart-1be3a823-a49b-42cf-89ed-e24d4db8e99e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719677825 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2719677825
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2989474210
Short name T386
Test name
Test status
Simulation time 25338022 ps
CPU time 1.08 seconds
Started Feb 21 12:53:06 PM PST 24
Finished Feb 21 12:53:07 PM PST 24
Peak memory 216836 kb
Host smart-dc70bcc6-f209-4135-99f7-17b3fa31a035
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989474210 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2989474210
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.3348396749
Short name T820
Test name
Test status
Simulation time 47374945 ps
CPU time 1.04 seconds
Started Feb 21 12:53:04 PM PST 24
Finished Feb 21 12:53:06 PM PST 24
Peak memory 230716 kb
Host smart-6542b533-8f74-4209-94cb-e7469c4e97e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348396749 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3348396749
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2635235684
Short name T723
Test name
Test status
Simulation time 25777793 ps
CPU time 1.11 seconds
Started Feb 21 12:53:02 PM PST 24
Finished Feb 21 12:53:04 PM PST 24
Peak memory 218724 kb
Host smart-beb635b7-6d38-483d-9d1e-40ab94801e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635235684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2635235684
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3904329515
Short name T120
Test name
Test status
Simulation time 28764121 ps
CPU time 0.87 seconds
Started Feb 21 12:53:01 PM PST 24
Finished Feb 21 12:53:03 PM PST 24
Peak memory 215064 kb
Host smart-46c89da9-268f-4b68-9da4-71691833f2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904329515 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3904329515
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3667381702
Short name T525
Test name
Test status
Simulation time 14781725 ps
CPU time 0.91 seconds
Started Feb 21 12:53:04 PM PST 24
Finished Feb 21 12:53:06 PM PST 24
Peak memory 214644 kb
Host smart-a511533e-34b1-47f8-83a3-67e135a73b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667381702 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3667381702
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3799505588
Short name T202
Test name
Test status
Simulation time 192244291 ps
CPU time 2.33 seconds
Started Feb 21 12:53:21 PM PST 24
Finished Feb 21 12:53:24 PM PST 24
Peak memory 214732 kb
Host smart-49a532d4-afc5-4d9e-aad9-55d23f522ca4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799505588 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3799505588
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2310021833
Short name T478
Test name
Test status
Simulation time 39883502670 ps
CPU time 431.08 seconds
Started Feb 21 12:53:09 PM PST 24
Finished Feb 21 01:00:21 PM PST 24
Peak memory 217348 kb
Host smart-661352b6-935a-48f1-ac8d-fff49741d1e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310021833 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2310021833
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.193718227
Short name T641
Test name
Test status
Simulation time 48075235 ps
CPU time 1.32 seconds
Started Feb 21 12:54:58 PM PST 24
Finished Feb 21 12:55:01 PM PST 24
Peak memory 217384 kb
Host smart-048283c9-508d-4030-b430-f7ffa3927bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193718227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.193718227
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.2763886390
Short name T632
Test name
Test status
Simulation time 54777082 ps
CPU time 2.14 seconds
Started Feb 21 12:54:54 PM PST 24
Finished Feb 21 12:54:57 PM PST 24
Peak memory 217308 kb
Host smart-d5865f1b-f7b7-4035-a133-7aa7e5da13bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763886390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2763886390
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.2169969011
Short name T372
Test name
Test status
Simulation time 31481634 ps
CPU time 1.16 seconds
Started Feb 21 12:54:51 PM PST 24
Finished Feb 21 12:54:53 PM PST 24
Peak memory 215844 kb
Host smart-16ace3d2-3700-4d9f-8b72-7ea2a4e815a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169969011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2169969011
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.2369389456
Short name T241
Test name
Test status
Simulation time 36519971 ps
CPU time 1.47 seconds
Started Feb 21 12:54:48 PM PST 24
Finished Feb 21 12:54:50 PM PST 24
Peak memory 218820 kb
Host smart-c9307630-ca29-4200-b450-b1efd8e9760a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369389456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2369389456
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.3535946018
Short name T502
Test name
Test status
Simulation time 81928032 ps
CPU time 1.05 seconds
Started Feb 21 12:54:51 PM PST 24
Finished Feb 21 12:54:53 PM PST 24
Peak memory 215868 kb
Host smart-29f0af4b-a184-4e70-8746-e0154b91c11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535946018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3535946018
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.3111918641
Short name T594
Test name
Test status
Simulation time 50920598 ps
CPU time 1.63 seconds
Started Feb 21 12:54:52 PM PST 24
Finished Feb 21 12:54:54 PM PST 24
Peak memory 217208 kb
Host smart-088c4ec6-2fbc-4922-850d-3a8dcdc8f1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111918641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3111918641
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.677242459
Short name T343
Test name
Test status
Simulation time 109717674 ps
CPU time 2.38 seconds
Started Feb 21 12:54:51 PM PST 24
Finished Feb 21 12:54:54 PM PST 24
Peak memory 216160 kb
Host smart-532e6d80-bffd-48eb-b763-51fc20ec0cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677242459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.677242459
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.3480730891
Short name T162
Test name
Test status
Simulation time 42430499 ps
CPU time 1.46 seconds
Started Feb 21 12:54:46 PM PST 24
Finished Feb 21 12:54:48 PM PST 24
Peak memory 218464 kb
Host smart-cec76bd7-d71a-43f9-b2cc-4ef3c2d5788b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480730891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3480730891
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.2132268890
Short name T611
Test name
Test status
Simulation time 37016908 ps
CPU time 1.35 seconds
Started Feb 21 12:54:48 PM PST 24
Finished Feb 21 12:54:50 PM PST 24
Peak memory 217156 kb
Host smart-855507c3-b6f9-4f3a-9e57-2c2f320e1062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132268890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2132268890
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.23305157
Short name T699
Test name
Test status
Simulation time 60290991 ps
CPU time 1.75 seconds
Started Feb 21 12:55:01 PM PST 24
Finished Feb 21 12:55:04 PM PST 24
Peak memory 217196 kb
Host smart-43eead26-d0ef-41de-9ca0-2167bcf4517b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23305157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.23305157
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2268205324
Short name T265
Test name
Test status
Simulation time 23021767 ps
CPU time 1.11 seconds
Started Feb 21 12:52:30 PM PST 24
Finished Feb 21 12:52:32 PM PST 24
Peak memory 215144 kb
Host smart-9bcc7a58-f223-4466-a4c4-1c5586096b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268205324 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2268205324
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.924091201
Short name T590
Test name
Test status
Simulation time 55436901 ps
CPU time 0.87 seconds
Started Feb 21 12:52:30 PM PST 24
Finished Feb 21 12:52:32 PM PST 24
Peak memory 205848 kb
Host smart-8b934eb2-a4ba-4ef0-a331-3f2981aacbed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924091201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.924091201
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1504766825
Short name T618
Test name
Test status
Simulation time 15466456 ps
CPU time 0.82 seconds
Started Feb 21 12:52:31 PM PST 24
Finished Feb 21 12:52:32 PM PST 24
Peak memory 214956 kb
Host smart-872d289e-476b-43fc-a908-ca4599bc8978
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504766825 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1504766825
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.2403127123
Short name T667
Test name
Test status
Simulation time 35030240 ps
CPU time 1.06 seconds
Started Feb 21 12:52:35 PM PST 24
Finished Feb 21 12:52:36 PM PST 24
Peak memory 216360 kb
Host smart-4b9b0ff4-c64b-4fda-83fe-e57462be9392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403127123 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2403127123
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1776136519
Short name T808
Test name
Test status
Simulation time 126039927 ps
CPU time 1.7 seconds
Started Feb 21 12:52:14 PM PST 24
Finished Feb 21 12:52:16 PM PST 24
Peak memory 217296 kb
Host smart-78fb171a-e692-49a0-9167-3d66438ffb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776136519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1776136519
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.538882527
Short name T332
Test name
Test status
Simulation time 108290722 ps
CPU time 0.8 seconds
Started Feb 21 12:52:28 PM PST 24
Finished Feb 21 12:52:30 PM PST 24
Peak memory 214592 kb
Host smart-40dc8081-adb9-4b14-a558-03cd3e28efb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538882527 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.538882527
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3519506778
Short name T193
Test name
Test status
Simulation time 30549948 ps
CPU time 0.94 seconds
Started Feb 21 12:52:20 PM PST 24
Finished Feb 21 12:52:21 PM PST 24
Peak memory 206452 kb
Host smart-8b9d9fe8-7627-48c0-879b-3fee4ac99591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519506778 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3519506778
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1811690537
Short name T44
Test name
Test status
Simulation time 385956083 ps
CPU time 3.1 seconds
Started Feb 21 12:52:26 PM PST 24
Finished Feb 21 12:52:30 PM PST 24
Peak memory 235064 kb
Host smart-eb8ea913-4add-4274-9f48-70ac808f97a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811690537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1811690537
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.764665349
Short name T637
Test name
Test status
Simulation time 17202589 ps
CPU time 0.98 seconds
Started Feb 21 12:52:24 PM PST 24
Finished Feb 21 12:52:25 PM PST 24
Peak memory 206580 kb
Host smart-17027935-3b3e-4ac4-a182-cc3cf23d4ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764665349 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.764665349
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1763638999
Short name T319
Test name
Test status
Simulation time 545166367 ps
CPU time 4.31 seconds
Started Feb 21 12:52:17 PM PST 24
Finished Feb 21 12:52:22 PM PST 24
Peak memory 215040 kb
Host smart-6404574c-9411-4ea4-a1ce-87c88caf18f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763638999 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1763638999
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1443184915
Short name T180
Test name
Test status
Simulation time 78926838443 ps
CPU time 425.4 seconds
Started Feb 21 12:52:18 PM PST 24
Finished Feb 21 12:59:24 PM PST 24
Peak memory 217476 kb
Host smart-b695244f-8fb8-45ca-be59-9c650d5a64fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443184915 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1443184915
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2935186856
Short name T135
Test name
Test status
Simulation time 287577759 ps
CPU time 1.38 seconds
Started Feb 21 12:53:19 PM PST 24
Finished Feb 21 12:53:22 PM PST 24
Peak memory 215112 kb
Host smart-b88d5425-83f0-421e-9850-efc5ab4595fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935186856 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2935186856
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3432990111
Short name T487
Test name
Test status
Simulation time 204321161 ps
CPU time 0.83 seconds
Started Feb 21 12:53:03 PM PST 24
Finished Feb 21 12:53:04 PM PST 24
Peak memory 206344 kb
Host smart-bb74f8d2-e371-42d9-867e-382e8c2b57ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432990111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3432990111
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1485333651
Short name T104
Test name
Test status
Simulation time 12477922 ps
CPU time 0.92 seconds
Started Feb 21 12:53:21 PM PST 24
Finished Feb 21 12:53:23 PM PST 24
Peak memory 215144 kb
Host smart-20e35529-7fa0-471c-bc12-6a429cb75e09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485333651 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1485333651
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2578166485
Short name T75
Test name
Test status
Simulation time 96828461 ps
CPU time 0.98 seconds
Started Feb 21 12:53:19 PM PST 24
Finished Feb 21 12:53:21 PM PST 24
Peak memory 216036 kb
Host smart-3d9d7cf2-5609-48ae-99ff-e9668f9d3068
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578166485 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2578166485
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2156598592
Short name T648
Test name
Test status
Simulation time 19926140 ps
CPU time 1.1 seconds
Started Feb 21 12:53:02 PM PST 24
Finished Feb 21 12:53:04 PM PST 24
Peak memory 222504 kb
Host smart-aa261b97-730b-42ee-882c-8822ce58c884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156598592 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2156598592
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3119079413
Short name T474
Test name
Test status
Simulation time 57715103 ps
CPU time 1.34 seconds
Started Feb 21 12:53:06 PM PST 24
Finished Feb 21 12:53:08 PM PST 24
Peak memory 216000 kb
Host smart-fe3c7e9a-93f4-4c1b-a4fe-8a99a107900b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119079413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3119079413
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1763347344
Short name T774
Test name
Test status
Simulation time 22527190 ps
CPU time 1.18 seconds
Started Feb 21 12:53:19 PM PST 24
Finished Feb 21 12:53:21 PM PST 24
Peak memory 231664 kb
Host smart-042a9880-6e78-406f-811b-860fd1b8845e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763347344 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1763347344
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2733838368
Short name T601
Test name
Test status
Simulation time 45726524 ps
CPU time 0.92 seconds
Started Feb 21 12:53:03 PM PST 24
Finished Feb 21 12:53:05 PM PST 24
Peak memory 214768 kb
Host smart-0775ccaf-8483-429f-b03a-45bd6abc87c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733838368 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2733838368
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2457928573
Short name T204
Test name
Test status
Simulation time 634368169 ps
CPU time 3.49 seconds
Started Feb 21 12:53:19 PM PST 24
Finished Feb 21 12:53:24 PM PST 24
Peak memory 215804 kb
Host smart-5fce85bd-da6c-4256-a100-7fda26826093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457928573 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2457928573
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3438277263
Short name T375
Test name
Test status
Simulation time 99039511873 ps
CPU time 1130.94 seconds
Started Feb 21 12:53:21 PM PST 24
Finished Feb 21 01:12:13 PM PST 24
Peak memory 221700 kb
Host smart-e75372c3-5653-4354-809d-d6c8d10fbbe6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438277263 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3438277263
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.4108779730
Short name T514
Test name
Test status
Simulation time 31261324 ps
CPU time 1.3 seconds
Started Feb 21 12:54:50 PM PST 24
Finished Feb 21 12:54:52 PM PST 24
Peak memory 215952 kb
Host smart-7630481c-47a6-4096-975d-a2826b8e9eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108779730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.4108779730
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2419865625
Short name T515
Test name
Test status
Simulation time 43093071 ps
CPU time 1.16 seconds
Started Feb 21 12:54:50 PM PST 24
Finished Feb 21 12:54:52 PM PST 24
Peak memory 216044 kb
Host smart-cf2d1a35-94d0-4b0f-901e-90278372755f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419865625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2419865625
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.140017639
Short name T640
Test name
Test status
Simulation time 58026266 ps
CPU time 1.24 seconds
Started Feb 21 12:55:01 PM PST 24
Finished Feb 21 12:55:05 PM PST 24
Peak memory 215780 kb
Host smart-ee922762-b632-4f7d-b92c-bd7b824acd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140017639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.140017639
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1396952447
Short name T54
Test name
Test status
Simulation time 90041963 ps
CPU time 1.5 seconds
Started Feb 21 12:54:53 PM PST 24
Finished Feb 21 12:54:55 PM PST 24
Peak memory 217556 kb
Host smart-2716117f-e49c-4a8d-86d9-cd2f7cf8efe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396952447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1396952447
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1463672475
Short name T447
Test name
Test status
Simulation time 458153988 ps
CPU time 3.48 seconds
Started Feb 21 12:55:01 PM PST 24
Finished Feb 21 12:55:07 PM PST 24
Peak memory 216496 kb
Host smart-34e8bb62-a2ed-4342-a6a5-337167e7c4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463672475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1463672475
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.820081417
Short name T653
Test name
Test status
Simulation time 73022431 ps
CPU time 1.73 seconds
Started Feb 21 12:54:59 PM PST 24
Finished Feb 21 12:55:02 PM PST 24
Peak memory 217188 kb
Host smart-5c0068ae-e0fc-4e26-8e87-e362a134b884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820081417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.820081417
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.748131242
Short name T688
Test name
Test status
Simulation time 43816777 ps
CPU time 1.43 seconds
Started Feb 21 12:55:02 PM PST 24
Finished Feb 21 12:55:06 PM PST 24
Peak memory 217192 kb
Host smart-65040be5-ac7b-4c23-84c9-7c6265c04ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748131242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.748131242
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3779467021
Short name T592
Test name
Test status
Simulation time 64801714 ps
CPU time 1.22 seconds
Started Feb 21 12:54:54 PM PST 24
Finished Feb 21 12:54:56 PM PST 24
Peak memory 217232 kb
Host smart-9db10663-f790-48c0-9270-0a3712e4dbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779467021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3779467021
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3553520864
Short name T655
Test name
Test status
Simulation time 54801887 ps
CPU time 1.6 seconds
Started Feb 21 12:54:53 PM PST 24
Finished Feb 21 12:54:55 PM PST 24
Peak memory 218448 kb
Host smart-195aa6c4-a5fb-4f6f-aed6-08827058b6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553520864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3553520864
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2369222985
Short name T624
Test name
Test status
Simulation time 161168379 ps
CPU time 2.28 seconds
Started Feb 21 12:55:02 PM PST 24
Finished Feb 21 12:55:07 PM PST 24
Peak memory 217896 kb
Host smart-bcf74a93-4317-445f-a8fc-36df0d4f7c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369222985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2369222985
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3964606024
Short name T720
Test name
Test status
Simulation time 81249644 ps
CPU time 1.29 seconds
Started Feb 21 12:53:23 PM PST 24
Finished Feb 21 12:53:25 PM PST 24
Peak memory 215128 kb
Host smart-f5635310-761a-49f2-838c-0d3f0d598d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964606024 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3964606024
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3977226352
Short name T791
Test name
Test status
Simulation time 61078586 ps
CPU time 0.86 seconds
Started Feb 21 12:53:20 PM PST 24
Finished Feb 21 12:53:22 PM PST 24
Peak memory 206228 kb
Host smart-b3e14014-a348-42a6-a28f-787bc23659b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977226352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3977226352
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.594590984
Short name T811
Test name
Test status
Simulation time 16585590 ps
CPU time 0.8 seconds
Started Feb 21 12:53:20 PM PST 24
Finished Feb 21 12:53:22 PM PST 24
Peak memory 215236 kb
Host smart-44482db5-7339-4881-8906-172e0f5c82b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594590984 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.594590984
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3694428892
Short name T309
Test name
Test status
Simulation time 20066706 ps
CPU time 0.92 seconds
Started Feb 21 12:53:18 PM PST 24
Finished Feb 21 12:53:19 PM PST 24
Peak memory 217016 kb
Host smart-9332c7b4-4a24-40af-a06d-a74b58ceabe3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694428892 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3694428892
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.896054651
Short name T150
Test name
Test status
Simulation time 65988509 ps
CPU time 0.83 seconds
Started Feb 21 12:53:23 PM PST 24
Finished Feb 21 12:53:25 PM PST 24
Peak memory 217336 kb
Host smart-399c6e9e-0344-419b-804f-1b81a73b9310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896054651 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.896054651
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3733916424
Short name T315
Test name
Test status
Simulation time 38041856 ps
CPU time 1.43 seconds
Started Feb 21 12:53:19 PM PST 24
Finished Feb 21 12:53:21 PM PST 24
Peak memory 217268 kb
Host smart-c4ef7dd0-a89d-4709-b073-4fc1745b65c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733916424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3733916424
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2249046959
Short name T118
Test name
Test status
Simulation time 25127803 ps
CPU time 0.92 seconds
Started Feb 21 12:53:18 PM PST 24
Finished Feb 21 12:53:19 PM PST 24
Peak memory 215216 kb
Host smart-e85bbb12-3dbd-49d4-93ff-cf96e26d5817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249046959 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2249046959
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1000497934
Short name T473
Test name
Test status
Simulation time 16772868 ps
CPU time 1.04 seconds
Started Feb 21 12:53:11 PM PST 24
Finished Feb 21 12:53:12 PM PST 24
Peak memory 214836 kb
Host smart-1fa6c7c1-e7d5-47dc-bfec-b66f3ce46dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000497934 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1000497934
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.353788686
Short name T518
Test name
Test status
Simulation time 794180542 ps
CPU time 4.02 seconds
Started Feb 21 12:53:19 PM PST 24
Finished Feb 21 12:53:25 PM PST 24
Peak memory 214732 kb
Host smart-f8092520-4e67-4447-8ca3-f0ca8debf170
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353788686 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.353788686
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2034769996
Short name T4
Test name
Test status
Simulation time 195137546869 ps
CPU time 1211.09 seconds
Started Feb 21 12:53:18 PM PST 24
Finished Feb 21 01:13:30 PM PST 24
Peak memory 223712 kb
Host smart-7bf158c3-2e56-44b7-8c4a-5f58f04b7f5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034769996 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2034769996
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2215555345
Short name T465
Test name
Test status
Simulation time 52609424 ps
CPU time 1.43 seconds
Started Feb 21 12:55:02 PM PST 24
Finished Feb 21 12:55:06 PM PST 24
Peak memory 217336 kb
Host smart-77e944bd-0b35-4c33-9173-08aa6dce6228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215555345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2215555345
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1911094431
Short name T685
Test name
Test status
Simulation time 156384849 ps
CPU time 1.25 seconds
Started Feb 21 12:55:02 PM PST 24
Finished Feb 21 12:55:05 PM PST 24
Peak memory 218732 kb
Host smart-9237f73f-f965-41c1-97f0-c6b90a4379ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911094431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1911094431
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.1687346996
Short name T282
Test name
Test status
Simulation time 49324029 ps
CPU time 1.45 seconds
Started Feb 21 12:55:01 PM PST 24
Finished Feb 21 12:55:05 PM PST 24
Peak memory 217604 kb
Host smart-273ef4f4-ce87-47e5-8077-b60a663003b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687346996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1687346996
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3997396767
Short name T746
Test name
Test status
Simulation time 186293400 ps
CPU time 1.09 seconds
Started Feb 21 12:55:01 PM PST 24
Finished Feb 21 12:55:04 PM PST 24
Peak memory 216060 kb
Host smart-07a12aa9-6cd5-4de4-a403-d6953445bf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997396767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3997396767
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.755069964
Short name T556
Test name
Test status
Simulation time 165449566 ps
CPU time 1.12 seconds
Started Feb 21 12:54:55 PM PST 24
Finished Feb 21 12:54:57 PM PST 24
Peak memory 216072 kb
Host smart-f7d102d6-3022-4b60-9e13-13d866cbbc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755069964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.755069964
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2366591753
Short name T741
Test name
Test status
Simulation time 67413817 ps
CPU time 1.23 seconds
Started Feb 21 12:54:54 PM PST 24
Finished Feb 21 12:54:56 PM PST 24
Peak memory 217296 kb
Host smart-d3d7857c-ba01-4739-805d-8f1ed00f9f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366591753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2366591753
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3659457147
Short name T777
Test name
Test status
Simulation time 65256868 ps
CPU time 1.69 seconds
Started Feb 21 12:54:58 PM PST 24
Finished Feb 21 12:55:01 PM PST 24
Peak memory 217392 kb
Host smart-e42444c4-e1c0-4881-8c8a-aef2396cab37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659457147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3659457147
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2984688584
Short name T776
Test name
Test status
Simulation time 82366251 ps
CPU time 1.06 seconds
Started Feb 21 12:55:01 PM PST 24
Finished Feb 21 12:55:04 PM PST 24
Peak memory 216328 kb
Host smart-0c43bb75-9ae1-474b-a86f-355f7c419a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984688584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2984688584
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1467291495
Short name T799
Test name
Test status
Simulation time 52540463 ps
CPU time 1.23 seconds
Started Feb 21 12:55:01 PM PST 24
Finished Feb 21 12:55:03 PM PST 24
Peak memory 216024 kb
Host smart-6c7e5e6f-3371-4137-8b64-255af7216fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467291495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1467291495
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.904912087
Short name T112
Test name
Test status
Simulation time 91165156 ps
CPU time 1.13 seconds
Started Feb 21 12:53:19 PM PST 24
Finished Feb 21 12:53:22 PM PST 24
Peak memory 215104 kb
Host smart-ae79d595-bcca-4f2b-9c02-2e03667d538a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904912087 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.904912087
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.4121679445
Short name T479
Test name
Test status
Simulation time 17768322 ps
CPU time 0.99 seconds
Started Feb 21 12:53:22 PM PST 24
Finished Feb 21 12:53:24 PM PST 24
Peak memory 206300 kb
Host smart-21ce5b68-087f-403a-a1be-dc534600d692
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121679445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.4121679445
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3833132679
Short name T170
Test name
Test status
Simulation time 11835082 ps
CPU time 0.88 seconds
Started Feb 21 12:53:19 PM PST 24
Finished Feb 21 12:53:21 PM PST 24
Peak memory 215228 kb
Host smart-24ab98e4-5965-4a94-a788-50f7f389f2c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833132679 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3833132679
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3123148215
Short name T792
Test name
Test status
Simulation time 49156415 ps
CPU time 1.09 seconds
Started Feb 21 12:53:21 PM PST 24
Finished Feb 21 12:53:23 PM PST 24
Peak memory 216900 kb
Host smart-92056b26-f98a-452e-b09e-158a84753d8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123148215 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3123148215
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3551820307
Short name T102
Test name
Test status
Simulation time 32449832 ps
CPU time 0.92 seconds
Started Feb 21 12:53:16 PM PST 24
Finished Feb 21 12:53:17 PM PST 24
Peak memory 222304 kb
Host smart-9e04a661-5b5e-4433-9f3c-784d0638f76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551820307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3551820307
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.1623623306
Short name T507
Test name
Test status
Simulation time 64989450 ps
CPU time 2.21 seconds
Started Feb 21 12:53:17 PM PST 24
Finished Feb 21 12:53:20 PM PST 24
Peak memory 218788 kb
Host smart-a8731523-9964-4dc3-9465-97a715ffc953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623623306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1623623306
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.926714662
Short name T498
Test name
Test status
Simulation time 46649274 ps
CPU time 0.82 seconds
Started Feb 21 12:53:18 PM PST 24
Finished Feb 21 12:53:19 PM PST 24
Peak memory 214684 kb
Host smart-e92ceaf0-c07a-4559-bdb7-237ae0190aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926714662 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.926714662
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.4283211864
Short name T807
Test name
Test status
Simulation time 36172753 ps
CPU time 0.87 seconds
Started Feb 21 12:53:20 PM PST 24
Finished Feb 21 12:53:22 PM PST 24
Peak memory 214732 kb
Host smart-f9492308-03f5-4d89-9815-0c53ddfb4115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283211864 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.4283211864
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.3421974501
Short name T468
Test name
Test status
Simulation time 164131504 ps
CPU time 3.41 seconds
Started Feb 21 12:53:18 PM PST 24
Finished Feb 21 12:53:22 PM PST 24
Peak memory 218704 kb
Host smart-317247e8-4d8b-472c-bfcf-ef4883eb4298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421974501 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3421974501
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.4086607217
Short name T187
Test name
Test status
Simulation time 77316928709 ps
CPU time 822.1 seconds
Started Feb 21 12:53:19 PM PST 24
Finished Feb 21 01:07:03 PM PST 24
Peak memory 218712 kb
Host smart-14d24041-ebcd-4c4c-baf2-8e6b8bc6cfb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086607217 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.4086607217
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3275322306
Short name T599
Test name
Test status
Simulation time 35281503 ps
CPU time 1.3 seconds
Started Feb 21 12:54:54 PM PST 24
Finished Feb 21 12:54:56 PM PST 24
Peak memory 216164 kb
Host smart-ce21a450-d294-4f6e-8789-bf2bf8045440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275322306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3275322306
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.398440551
Short name T597
Test name
Test status
Simulation time 203480564 ps
CPU time 2.97 seconds
Started Feb 21 12:55:01 PM PST 24
Finished Feb 21 12:55:06 PM PST 24
Peak memory 216400 kb
Host smart-24ef9ecb-3339-4cee-9401-69ff6c1ebf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398440551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.398440551
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2895261432
Short name T501
Test name
Test status
Simulation time 36630433 ps
CPU time 1.36 seconds
Started Feb 21 12:55:01 PM PST 24
Finished Feb 21 12:55:04 PM PST 24
Peak memory 218764 kb
Host smart-b6e8055b-5538-47a2-ad5f-ec993ef39196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895261432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2895261432
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1497332163
Short name T785
Test name
Test status
Simulation time 78994652 ps
CPU time 1.01 seconds
Started Feb 21 12:54:46 PM PST 24
Finished Feb 21 12:54:48 PM PST 24
Peak memory 216088 kb
Host smart-5466345e-7df8-4654-a0a0-468ebc7d94d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497332163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1497332163
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.1050460735
Short name T461
Test name
Test status
Simulation time 55810496 ps
CPU time 1.03 seconds
Started Feb 21 12:55:02 PM PST 24
Finished Feb 21 12:55:06 PM PST 24
Peak memory 218336 kb
Host smart-bbd6996b-499f-4a4b-b9f3-abe1e9e30aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050460735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1050460735
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.350978880
Short name T284
Test name
Test status
Simulation time 156780015 ps
CPU time 1.17 seconds
Started Feb 21 12:55:02 PM PST 24
Finished Feb 21 12:55:06 PM PST 24
Peak memory 215964 kb
Host smart-a404f666-23c6-4e11-96f2-75ddec5d981d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350978880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.350978880
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.175230233
Short name T581
Test name
Test status
Simulation time 83135172 ps
CPU time 2.98 seconds
Started Feb 21 12:55:01 PM PST 24
Finished Feb 21 12:55:07 PM PST 24
Peak memory 217184 kb
Host smart-16b39efb-8655-4b0d-ba24-ee689cdcdca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175230233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.175230233
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2139725210
Short name T757
Test name
Test status
Simulation time 77624020 ps
CPU time 1.35 seconds
Started Feb 21 12:54:58 PM PST 24
Finished Feb 21 12:55:00 PM PST 24
Peak memory 217176 kb
Host smart-3a3be91b-9ec4-4199-8a71-b591400e5c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139725210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2139725210
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.464603663
Short name T568
Test name
Test status
Simulation time 106777128 ps
CPU time 1.39 seconds
Started Feb 21 12:55:01 PM PST 24
Finished Feb 21 12:55:05 PM PST 24
Peak memory 217192 kb
Host smart-8ef6b95b-d552-4fb3-b664-c232d358cae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464603663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.464603663
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert_test.3982597746
Short name T485
Test name
Test status
Simulation time 28334361 ps
CPU time 0.87 seconds
Started Feb 21 12:53:16 PM PST 24
Finished Feb 21 12:53:17 PM PST 24
Peak memory 205940 kb
Host smart-098ae252-b513-4f86-a28d-910adef7e652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982597746 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3982597746
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.190570676
Short name T342
Test name
Test status
Simulation time 46442591 ps
CPU time 0.81 seconds
Started Feb 21 12:53:19 PM PST 24
Finished Feb 21 12:53:20 PM PST 24
Peak memory 214800 kb
Host smart-8b1a3c96-01ff-4bd3-8070-b7a0c99002c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190570676 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.190570676
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2727856756
Short name T155
Test name
Test status
Simulation time 183920197 ps
CPU time 1.02 seconds
Started Feb 21 12:53:18 PM PST 24
Finished Feb 21 12:53:20 PM PST 24
Peak memory 215980 kb
Host smart-f3a12245-d961-4347-87fc-2121e6aed5f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727856756 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2727856756
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.2028452987
Short name T407
Test name
Test status
Simulation time 19664117 ps
CPU time 1.06 seconds
Started Feb 21 12:53:22 PM PST 24
Finished Feb 21 12:53:24 PM PST 24
Peak memory 217444 kb
Host smart-b35a8ee4-f6f5-46d7-b446-8bcf2385d12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028452987 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.2028452987
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.4015618538
Short name T496
Test name
Test status
Simulation time 101142047 ps
CPU time 1.21 seconds
Started Feb 21 12:53:18 PM PST 24
Finished Feb 21 12:53:20 PM PST 24
Peak memory 217880 kb
Host smart-a5f7f0b4-9755-42e0-98a7-5ee46d11ad7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015618538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.4015618538
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.304678820
Short name T781
Test name
Test status
Simulation time 23557824 ps
CPU time 1 seconds
Started Feb 21 12:53:22 PM PST 24
Finished Feb 21 12:53:24 PM PST 24
Peak memory 215020 kb
Host smart-2eb0256a-e13e-40fe-8de8-176a21d50489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304678820 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.304678820
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3185892641
Short name T51
Test name
Test status
Simulation time 17431285 ps
CPU time 1 seconds
Started Feb 21 12:53:15 PM PST 24
Finished Feb 21 12:53:16 PM PST 24
Peak memory 214744 kb
Host smart-a4fd7255-3824-4ebc-b6ae-4aa5c4aef863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185892641 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3185892641
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2365137704
Short name T411
Test name
Test status
Simulation time 837888196 ps
CPU time 4.9 seconds
Started Feb 21 12:53:20 PM PST 24
Finished Feb 21 12:53:26 PM PST 24
Peak memory 215752 kb
Host smart-fc90bcf6-80ab-40b4-96cc-0b17e7b1281d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365137704 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2365137704
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3510632700
Short name T368
Test name
Test status
Simulation time 27711800300 ps
CPU time 206.7 seconds
Started Feb 21 12:53:16 PM PST 24
Finished Feb 21 12:56:43 PM PST 24
Peak memory 217104 kb
Host smart-0e19fd5c-0f97-4814-b30b-ac9fcea543d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510632700 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3510632700
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1871504320
Short name T308
Test name
Test status
Simulation time 88715337 ps
CPU time 1.19 seconds
Started Feb 21 12:55:01 PM PST 24
Finished Feb 21 12:55:04 PM PST 24
Peak memory 217184 kb
Host smart-9e4458bc-6a4d-443a-96dd-8d6aaaa3e5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871504320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1871504320
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1575923124
Short name T713
Test name
Test status
Simulation time 44711263 ps
CPU time 1.41 seconds
Started Feb 21 12:54:50 PM PST 24
Finished Feb 21 12:54:53 PM PST 24
Peak memory 217084 kb
Host smart-bcdc7147-42b9-46e2-95e3-3b57fd3213da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575923124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1575923124
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3791277015
Short name T402
Test name
Test status
Simulation time 74831975 ps
CPU time 1.16 seconds
Started Feb 21 12:54:58 PM PST 24
Finished Feb 21 12:55:00 PM PST 24
Peak memory 217204 kb
Host smart-a65806ca-f968-4e00-89eb-3145f1d576f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791277015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3791277015
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3264039242
Short name T600
Test name
Test status
Simulation time 447426891 ps
CPU time 2.59 seconds
Started Feb 21 12:54:59 PM PST 24
Finished Feb 21 12:55:03 PM PST 24
Peak memory 217332 kb
Host smart-24ab7b1d-1eac-4e24-b0c9-da569bc5978e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264039242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3264039242
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3000834894
Short name T376
Test name
Test status
Simulation time 76453766 ps
CPU time 1.04 seconds
Started Feb 21 12:54:58 PM PST 24
Finished Feb 21 12:55:00 PM PST 24
Peak memory 215912 kb
Host smart-361ac4bd-ef4b-4f34-bd2a-484d7d8b6249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000834894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3000834894
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2256712186
Short name T303
Test name
Test status
Simulation time 52985145 ps
CPU time 1.56 seconds
Started Feb 21 12:55:01 PM PST 24
Finished Feb 21 12:55:04 PM PST 24
Peak memory 216964 kb
Host smart-cb16b74f-0863-44af-bcb8-ce234131ba95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256712186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2256712186
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3100716375
Short name T598
Test name
Test status
Simulation time 216813975 ps
CPU time 1.09 seconds
Started Feb 21 12:55:01 PM PST 24
Finished Feb 21 12:55:05 PM PST 24
Peak memory 215812 kb
Host smart-72b830fe-93be-48e7-aedc-db1f8202fafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100716375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3100716375
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2096001446
Short name T742
Test name
Test status
Simulation time 54523378 ps
CPU time 1.6 seconds
Started Feb 21 12:55:02 PM PST 24
Finished Feb 21 12:55:06 PM PST 24
Peak memory 217296 kb
Host smart-14e51e9a-2c34-4761-b037-cbc2f9a122fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096001446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2096001446
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1946767430
Short name T825
Test name
Test status
Simulation time 60008286 ps
CPU time 1.22 seconds
Started Feb 21 12:55:08 PM PST 24
Finished Feb 21 12:55:09 PM PST 24
Peak memory 217244 kb
Host smart-69c37fd9-8e4f-4648-bd46-830b89d02ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946767430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1946767430
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2463172123
Short name T730
Test name
Test status
Simulation time 40617954 ps
CPU time 1.14 seconds
Started Feb 21 12:53:18 PM PST 24
Finished Feb 21 12:53:20 PM PST 24
Peak memory 215088 kb
Host smart-df437c28-2c91-4b4b-8d2c-6cd575d2cbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463172123 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2463172123
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.1606383674
Short name T572
Test name
Test status
Simulation time 134261056 ps
CPU time 0.87 seconds
Started Feb 21 12:53:36 PM PST 24
Finished Feb 21 12:53:37 PM PST 24
Peak memory 205260 kb
Host smart-e83c7a3f-c804-4247-bcbd-e824d280866f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606383674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1606383674
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1991365991
Short name T620
Test name
Test status
Simulation time 11189372 ps
CPU time 0.85 seconds
Started Feb 21 12:53:20 PM PST 24
Finished Feb 21 12:53:22 PM PST 24
Peak memory 214860 kb
Host smart-eff2edb5-0497-422f-887a-2b4facdce660
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991365991 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1991365991
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.4133541741
Short name T462
Test name
Test status
Simulation time 71621647 ps
CPU time 1.23 seconds
Started Feb 21 12:53:35 PM PST 24
Finished Feb 21 12:53:37 PM PST 24
Peak memory 215664 kb
Host smart-387a0cfc-04cd-42ea-aa77-f325275bb72d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133541741 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.4133541741
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.2075641140
Short name T416
Test name
Test status
Simulation time 24932392 ps
CPU time 0.95 seconds
Started Feb 21 12:53:21 PM PST 24
Finished Feb 21 12:53:24 PM PST 24
Peak memory 217520 kb
Host smart-d3ecbac2-a0f3-46eb-91fd-30d62db4f9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075641140 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2075641140
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2512482878
Short name T207
Test name
Test status
Simulation time 95291890 ps
CPU time 1.51 seconds
Started Feb 21 12:53:17 PM PST 24
Finished Feb 21 12:53:19 PM PST 24
Peak memory 217628 kb
Host smart-28b23eae-2671-4f57-a116-7fa0eea3ad28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512482878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2512482878
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.338145556
Short name T123
Test name
Test status
Simulation time 20400850 ps
CPU time 1.03 seconds
Started Feb 21 12:53:17 PM PST 24
Finished Feb 21 12:53:18 PM PST 24
Peak memory 215204 kb
Host smart-5df61350-d610-4757-af02-3617cd47f680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338145556 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.338145556
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.327854190
Short name T689
Test name
Test status
Simulation time 149856525 ps
CPU time 0.9 seconds
Started Feb 21 12:53:24 PM PST 24
Finished Feb 21 12:53:26 PM PST 24
Peak memory 214792 kb
Host smart-5151953a-b93b-44a5-9e1d-3628ac37f7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327854190 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.327854190
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3755065752
Short name T144
Test name
Test status
Simulation time 167816449 ps
CPU time 1.43 seconds
Started Feb 21 12:53:19 PM PST 24
Finished Feb 21 12:53:22 PM PST 24
Peak memory 215920 kb
Host smart-39b90b54-79f0-4045-b382-5e45c450542a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755065752 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3755065752
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3826531147
Short name T406
Test name
Test status
Simulation time 47329197480 ps
CPU time 260.79 seconds
Started Feb 21 12:53:18 PM PST 24
Finished Feb 21 12:57:40 PM PST 24
Peak memory 223112 kb
Host smart-d0514bfd-a52d-4ea2-beff-541556cfbfdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826531147 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3826531147
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.801425828
Short name T778
Test name
Test status
Simulation time 95766072 ps
CPU time 1.25 seconds
Started Feb 21 12:54:59 PM PST 24
Finished Feb 21 12:55:01 PM PST 24
Peak memory 215908 kb
Host smart-a68482fd-4d9b-4356-a5fb-2cd3eca27f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801425828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.801425828
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.511244211
Short name T53
Test name
Test status
Simulation time 76693827 ps
CPU time 1.25 seconds
Started Feb 21 12:54:58 PM PST 24
Finished Feb 21 12:55:00 PM PST 24
Peak memory 217336 kb
Host smart-8d649c51-19cb-4a7a-9196-2268695426ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511244211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.511244211
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3907158627
Short name T288
Test name
Test status
Simulation time 34720036 ps
CPU time 1.37 seconds
Started Feb 21 12:54:58 PM PST 24
Finished Feb 21 12:55:01 PM PST 24
Peak memory 218228 kb
Host smart-dc2a5fff-eb9b-4af2-8953-2f427b3069bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907158627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3907158627
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2876741215
Short name T260
Test name
Test status
Simulation time 74967182 ps
CPU time 1.27 seconds
Started Feb 21 12:55:00 PM PST 24
Finished Feb 21 12:55:02 PM PST 24
Peak memory 218424 kb
Host smart-400cf033-8f02-48a9-8a9b-94997d02e1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876741215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2876741215
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3427624447
Short name T290
Test name
Test status
Simulation time 27983400 ps
CPU time 0.94 seconds
Started Feb 21 12:55:05 PM PST 24
Finished Feb 21 12:55:07 PM PST 24
Peak memory 215788 kb
Host smart-fe7a9495-c592-403b-a902-8c74f7f4afb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427624447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3427624447
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1071506467
Short name T29
Test name
Test status
Simulation time 173561310 ps
CPU time 1.2 seconds
Started Feb 21 12:54:59 PM PST 24
Finished Feb 21 12:55:02 PM PST 24
Peak memory 216228 kb
Host smart-254274c5-a4cd-4c3e-b884-892f297f2525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071506467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1071506467
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3742865129
Short name T47
Test name
Test status
Simulation time 140795897 ps
CPU time 1.89 seconds
Started Feb 21 12:55:06 PM PST 24
Finished Feb 21 12:55:08 PM PST 24
Peak memory 218872 kb
Host smart-a7fa6c48-ffec-4fc5-9ea4-5e0a2f492d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742865129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3742865129
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1616234014
Short name T695
Test name
Test status
Simulation time 90442112 ps
CPU time 1.33 seconds
Started Feb 21 12:55:05 PM PST 24
Finished Feb 21 12:55:08 PM PST 24
Peak memory 217364 kb
Host smart-131fd744-27f6-4753-9dcb-8d60f77defbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616234014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1616234014
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1245810336
Short name T291
Test name
Test status
Simulation time 49733676 ps
CPU time 1.39 seconds
Started Feb 21 12:54:57 PM PST 24
Finished Feb 21 12:54:58 PM PST 24
Peak memory 217508 kb
Host smart-faed1a8a-7266-499f-a880-2ac419ab7561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245810336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1245810336
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1463584159
Short name T492
Test name
Test status
Simulation time 53444466 ps
CPU time 1.44 seconds
Started Feb 21 12:55:02 PM PST 24
Finished Feb 21 12:55:06 PM PST 24
Peak memory 217068 kb
Host smart-d8ffd493-241e-4951-9cba-b09a881d9ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463584159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1463584159
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3244901608
Short name T828
Test name
Test status
Simulation time 27696122 ps
CPU time 1.2 seconds
Started Feb 21 12:53:32 PM PST 24
Finished Feb 21 12:53:34 PM PST 24
Peak memory 215136 kb
Host smart-3cd9425d-341a-4da9-ac0a-6c823b6becf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244901608 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3244901608
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2330681519
Short name T322
Test name
Test status
Simulation time 52818646 ps
CPU time 0.87 seconds
Started Feb 21 12:53:36 PM PST 24
Finished Feb 21 12:53:37 PM PST 24
Peak memory 206236 kb
Host smart-f1811ff0-5668-446a-8858-a5f8c1167823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330681519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2330681519
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_genbits.1870287354
Short name T533
Test name
Test status
Simulation time 60051071 ps
CPU time 1.27 seconds
Started Feb 21 12:53:36 PM PST 24
Finished Feb 21 12:53:38 PM PST 24
Peak memory 215940 kb
Host smart-bf0049a6-fc96-4723-9d2e-680f2e03cc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870287354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1870287354
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.928340898
Short name T125
Test name
Test status
Simulation time 22712156 ps
CPU time 1.06 seconds
Started Feb 21 12:53:34 PM PST 24
Finished Feb 21 12:53:36 PM PST 24
Peak memory 215192 kb
Host smart-898b0b57-fb93-4fcc-ba22-26af64e5876e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928340898 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.928340898
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.398350395
Short name T734
Test name
Test status
Simulation time 43337832 ps
CPU time 0.84 seconds
Started Feb 21 12:53:31 PM PST 24
Finished Feb 21 12:53:32 PM PST 24
Peak memory 214720 kb
Host smart-720962c1-d5bc-446e-a387-7bfcacfd1e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398350395 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.398350395
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2765092395
Short name T646
Test name
Test status
Simulation time 882746245 ps
CPU time 2.55 seconds
Started Feb 21 12:53:35 PM PST 24
Finished Feb 21 12:53:38 PM PST 24
Peak memory 215944 kb
Host smart-6d751bda-b7ad-4fb2-80bb-43ab0f4cfc4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765092395 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2765092395
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1636685007
Short name T175
Test name
Test status
Simulation time 96606935359 ps
CPU time 2118.15 seconds
Started Feb 21 12:53:32 PM PST 24
Finished Feb 21 01:28:51 PM PST 24
Peak memory 225968 kb
Host smart-c227cddc-2e69-439d-b14d-04b8b601f2a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636685007 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1636685007
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.176553752
Short name T504
Test name
Test status
Simulation time 39820054 ps
CPU time 1.55 seconds
Started Feb 21 12:55:02 PM PST 24
Finished Feb 21 12:55:06 PM PST 24
Peak memory 218704 kb
Host smart-eca6b82e-11c5-477f-b8fa-5e0f723fd40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176553752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.176553752
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1320607033
Short name T629
Test name
Test status
Simulation time 138462892 ps
CPU time 2.81 seconds
Started Feb 21 12:54:59 PM PST 24
Finished Feb 21 12:55:03 PM PST 24
Peak memory 217492 kb
Host smart-f17acb6f-5738-4b5b-961f-327e457983cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320607033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1320607033
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2901354527
Short name T161
Test name
Test status
Simulation time 65260413 ps
CPU time 1.03 seconds
Started Feb 21 12:55:02 PM PST 24
Finished Feb 21 12:55:05 PM PST 24
Peak memory 216268 kb
Host smart-7bb8a4a9-11cd-4bf5-8897-ca0078253146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901354527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2901354527
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2384791429
Short name T615
Test name
Test status
Simulation time 62132308 ps
CPU time 1.83 seconds
Started Feb 21 12:55:04 PM PST 24
Finished Feb 21 12:55:08 PM PST 24
Peak memory 217012 kb
Host smart-47b7e829-a57c-4af9-a706-1283d53ff0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384791429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2384791429
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2143614090
Short name T245
Test name
Test status
Simulation time 34535909 ps
CPU time 1.38 seconds
Started Feb 21 12:54:58 PM PST 24
Finished Feb 21 12:55:01 PM PST 24
Peak memory 216112 kb
Host smart-2a6b8e21-a706-4e1e-9684-47b1b81d009c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143614090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2143614090
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.939024792
Short name T391
Test name
Test status
Simulation time 46636517 ps
CPU time 1.61 seconds
Started Feb 21 12:55:07 PM PST 24
Finished Feb 21 12:55:09 PM PST 24
Peak memory 217200 kb
Host smart-221adb88-e93a-4641-b1e1-d2afe8acd887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939024792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.939024792
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2826458223
Short name T345
Test name
Test status
Simulation time 117482595 ps
CPU time 1 seconds
Started Feb 21 12:55:02 PM PST 24
Finished Feb 21 12:55:06 PM PST 24
Peak memory 216096 kb
Host smart-6d250b00-1815-482d-b0c8-582e788fd163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826458223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2826458223
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.703017590
Short name T705
Test name
Test status
Simulation time 60261545 ps
CPU time 0.96 seconds
Started Feb 21 12:55:06 PM PST 24
Finished Feb 21 12:55:07 PM PST 24
Peak memory 215916 kb
Host smart-85ce0906-4205-4635-90d6-4813d1dd94d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703017590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.703017590
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3873444882
Short name T500
Test name
Test status
Simulation time 40354494 ps
CPU time 1.06 seconds
Started Feb 21 12:55:06 PM PST 24
Finished Feb 21 12:55:08 PM PST 24
Peak memory 214736 kb
Host smart-fa6fb675-5fa1-4d3b-aba4-993bb6b35ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873444882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3873444882
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3002982353
Short name T111
Test name
Test status
Simulation time 45033834 ps
CPU time 1.14 seconds
Started Feb 21 12:53:34 PM PST 24
Finished Feb 21 12:53:36 PM PST 24
Peak memory 215120 kb
Host smart-7f151ecd-8ebb-49e6-9f4a-d201045777c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002982353 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3002982353
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1056364200
Short name T837
Test name
Test status
Simulation time 37914701 ps
CPU time 0.98 seconds
Started Feb 21 12:53:44 PM PST 24
Finished Feb 21 12:53:46 PM PST 24
Peak memory 206316 kb
Host smart-c29ebc9a-cdba-4ab9-829d-34a73ed00b5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056364200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1056364200
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.344347445
Short name T32
Test name
Test status
Simulation time 32945743 ps
CPU time 0.84 seconds
Started Feb 21 12:53:34 PM PST 24
Finished Feb 21 12:53:36 PM PST 24
Peak memory 214880 kb
Host smart-f5f52b07-1e50-4587-be8c-656c49e03746
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344347445 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.344347445
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.2337040307
Short name T834
Test name
Test status
Simulation time 28191262 ps
CPU time 1.35 seconds
Started Feb 21 12:53:37 PM PST 24
Finished Feb 21 12:53:38 PM PST 24
Peak memory 231828 kb
Host smart-4c08ab2d-bbac-4b94-bcd5-54a0919d7c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337040307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2337040307
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1164462127
Short name T389
Test name
Test status
Simulation time 27137705 ps
CPU time 1.19 seconds
Started Feb 21 12:53:35 PM PST 24
Finished Feb 21 12:53:37 PM PST 24
Peak memory 217984 kb
Host smart-16a8c2e3-0e81-4e8f-b168-4a377fda0546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164462127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1164462127
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3323591828
Short name T751
Test name
Test status
Simulation time 25851324 ps
CPU time 0.91 seconds
Started Feb 21 12:53:33 PM PST 24
Finished Feb 21 12:53:34 PM PST 24
Peak memory 214892 kb
Host smart-7c7d1fbc-0888-47d8-b1df-d80975a03b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323591828 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3323591828
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.139440112
Short name T356
Test name
Test status
Simulation time 23709002 ps
CPU time 0.88 seconds
Started Feb 21 12:53:31 PM PST 24
Finished Feb 21 12:53:33 PM PST 24
Peak memory 214696 kb
Host smart-8a15a0bd-5503-44a0-917b-82e62eee712b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139440112 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.139440112
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.945365726
Short name T445
Test name
Test status
Simulation time 142420554 ps
CPU time 1.23 seconds
Started Feb 21 12:53:41 PM PST 24
Finished Feb 21 12:53:43 PM PST 24
Peak memory 215852 kb
Host smart-0d10ff33-b940-483e-bd98-9cbd9d7e11ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945365726 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.945365726
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.485272929
Short name T183
Test name
Test status
Simulation time 34575069778 ps
CPU time 752.88 seconds
Started Feb 21 12:53:32 PM PST 24
Finished Feb 21 01:06:06 PM PST 24
Peak memory 223104 kb
Host smart-6bc7f895-3b16-4457-8f20-154000568751
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485272929 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.485272929
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1598089799
Short name T340
Test name
Test status
Simulation time 48539262 ps
CPU time 1.77 seconds
Started Feb 21 12:55:01 PM PST 24
Finished Feb 21 12:55:04 PM PST 24
Peak memory 219076 kb
Host smart-de8cc586-bd2a-4380-a6b4-8f7baf40e0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598089799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1598089799
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1781031606
Short name T388
Test name
Test status
Simulation time 31627373 ps
CPU time 1.31 seconds
Started Feb 21 12:54:56 PM PST 24
Finished Feb 21 12:54:57 PM PST 24
Peak memory 215888 kb
Host smart-707a3ba3-fef9-4469-bc29-4512b7d76538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781031606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1781031606
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2566539958
Short name T143
Test name
Test status
Simulation time 107489333 ps
CPU time 1.25 seconds
Started Feb 21 12:55:04 PM PST 24
Finished Feb 21 12:55:07 PM PST 24
Peak memory 215928 kb
Host smart-a58e0042-ea5f-4b00-80c7-b278cf73ea57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566539958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2566539958
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2257470977
Short name T782
Test name
Test status
Simulation time 76565651 ps
CPU time 1.16 seconds
Started Feb 21 12:55:13 PM PST 24
Finished Feb 21 12:55:14 PM PST 24
Peak memory 218560 kb
Host smart-cc827799-ede3-43a8-aa3f-d2acd93d1552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257470977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2257470977
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1703069338
Short name T330
Test name
Test status
Simulation time 67311332 ps
CPU time 1.66 seconds
Started Feb 21 12:55:12 PM PST 24
Finished Feb 21 12:55:14 PM PST 24
Peak memory 217364 kb
Host smart-ccc073ca-db1f-4c8b-a0e2-7bbe6896114f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703069338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1703069338
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2033517225
Short name T11
Test name
Test status
Simulation time 103924286 ps
CPU time 2.2 seconds
Started Feb 21 12:55:02 PM PST 24
Finished Feb 21 12:55:06 PM PST 24
Peak memory 217124 kb
Host smart-3502c3ac-c203-4530-ae42-2f2a92d9899e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033517225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2033517225
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3814027988
Short name T668
Test name
Test status
Simulation time 45491499 ps
CPU time 1.44 seconds
Started Feb 21 12:55:13 PM PST 24
Finished Feb 21 12:55:16 PM PST 24
Peak memory 216428 kb
Host smart-cbb5fc1c-417f-4d1b-8615-05634fd949bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814027988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3814027988
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.170116985
Short name T425
Test name
Test status
Simulation time 52943626 ps
CPU time 1.63 seconds
Started Feb 21 12:55:04 PM PST 24
Finished Feb 21 12:55:08 PM PST 24
Peak memory 216164 kb
Host smart-b338391f-a65e-48e9-b72e-c62f0b634040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170116985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.170116985
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1875693432
Short name T12
Test name
Test status
Simulation time 114079070 ps
CPU time 1.23 seconds
Started Feb 21 12:54:58 PM PST 24
Finished Feb 21 12:55:00 PM PST 24
Peak memory 218480 kb
Host smart-ba217f50-6594-484e-8aed-7ab3e14cb277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875693432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1875693432
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1785625087
Short name T696
Test name
Test status
Simulation time 35692734 ps
CPU time 1.1 seconds
Started Feb 21 12:55:00 PM PST 24
Finished Feb 21 12:55:03 PM PST 24
Peak memory 215932 kb
Host smart-1093a089-8fdf-4a65-b5a7-6e520aeaf2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785625087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1785625087
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert_test.1464342804
Short name T819
Test name
Test status
Simulation time 45048262 ps
CPU time 0.86 seconds
Started Feb 21 12:53:44 PM PST 24
Finished Feb 21 12:53:46 PM PST 24
Peak memory 205952 kb
Host smart-734d1e18-1a32-4f9f-b730-4e6bdcab6659
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464342804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1464342804
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3044850300
Short name T40
Test name
Test status
Simulation time 114262401 ps
CPU time 1.19 seconds
Started Feb 21 12:53:35 PM PST 24
Finished Feb 21 12:53:36 PM PST 24
Peak memory 215704 kb
Host smart-5593f347-71a0-4b23-823a-d0b9240fada5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044850300 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3044850300
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.626168241
Short name T679
Test name
Test status
Simulation time 25132059 ps
CPU time 1.14 seconds
Started Feb 21 12:53:34 PM PST 24
Finished Feb 21 12:53:36 PM PST 24
Peak memory 217632 kb
Host smart-202b4bf0-b7ad-4fab-949c-5d37e7764f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626168241 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.626168241
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2152301622
Short name T493
Test name
Test status
Simulation time 34077832 ps
CPU time 1.26 seconds
Started Feb 21 12:53:36 PM PST 24
Finished Feb 21 12:53:38 PM PST 24
Peak memory 217284 kb
Host smart-864fc154-e281-4cae-966f-78319295a6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152301622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2152301622
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.247167211
Short name T739
Test name
Test status
Simulation time 20677759 ps
CPU time 1.07 seconds
Started Feb 21 12:53:41 PM PST 24
Finished Feb 21 12:53:43 PM PST 24
Peak memory 215220 kb
Host smart-11e9bd79-9ae2-4960-ab93-eaef2da6c2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247167211 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.247167211
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2268116838
Short name T722
Test name
Test status
Simulation time 48324876 ps
CPU time 0.93 seconds
Started Feb 21 12:53:32 PM PST 24
Finished Feb 21 12:53:34 PM PST 24
Peak memory 214744 kb
Host smart-878eb84c-c2a4-4482-b83e-01ba6a59897b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268116838 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2268116838
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.4232802422
Short name T192
Test name
Test status
Simulation time 1094825117 ps
CPU time 5.54 seconds
Started Feb 21 12:53:33 PM PST 24
Finished Feb 21 12:53:39 PM PST 24
Peak memory 214736 kb
Host smart-16f23e1e-aa48-44b9-9568-774831075f51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232802422 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.4232802422
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3060933883
Short name T642
Test name
Test status
Simulation time 5617088268 ps
CPU time 136.32 seconds
Started Feb 21 12:53:37 PM PST 24
Finished Feb 21 12:55:54 PM PST 24
Peak memory 217052 kb
Host smart-04cb6cdb-1ba4-456e-8cbb-1c15c09956e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060933883 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3060933883
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.3242246570
Short name T677
Test name
Test status
Simulation time 38976951 ps
CPU time 1.67 seconds
Started Feb 21 12:55:04 PM PST 24
Finished Feb 21 12:55:08 PM PST 24
Peak memory 217476 kb
Host smart-c4b39735-ad09-424d-8aed-96f971fed4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242246570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3242246570
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.214543192
Short name T276
Test name
Test status
Simulation time 32393968 ps
CPU time 1.32 seconds
Started Feb 21 12:55:13 PM PST 24
Finished Feb 21 12:55:16 PM PST 24
Peak memory 217104 kb
Host smart-3bd92dfc-cf54-4759-b7e6-8e563e9704f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214543192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.214543192
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1679111325
Short name T316
Test name
Test status
Simulation time 61434410 ps
CPU time 1.71 seconds
Started Feb 21 12:55:12 PM PST 24
Finished Feb 21 12:55:14 PM PST 24
Peak memory 217044 kb
Host smart-bf9b614e-cbb3-4220-a6d5-127dd79063ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679111325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1679111325
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2177231853
Short name T775
Test name
Test status
Simulation time 51950375 ps
CPU time 1.03 seconds
Started Feb 21 12:54:58 PM PST 24
Finished Feb 21 12:54:59 PM PST 24
Peak memory 218516 kb
Host smart-5c1018a8-5cc8-4fa1-a9b2-14e55ed5139a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177231853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2177231853
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3577519062
Short name T394
Test name
Test status
Simulation time 36948516 ps
CPU time 1.59 seconds
Started Feb 21 12:55:00 PM PST 24
Finished Feb 21 12:55:02 PM PST 24
Peak memory 217452 kb
Host smart-37e44f38-86f7-4945-bcca-b88fd8f8d384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577519062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3577519062
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.346595747
Short name T558
Test name
Test status
Simulation time 47193216 ps
CPU time 1.16 seconds
Started Feb 21 12:55:02 PM PST 24
Finished Feb 21 12:55:05 PM PST 24
Peak memory 217188 kb
Host smart-6614c05d-9ba3-47e6-96ab-52da3c42d179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346595747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.346595747
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.617267976
Short name T243
Test name
Test status
Simulation time 80428311 ps
CPU time 1 seconds
Started Feb 21 12:55:12 PM PST 24
Finished Feb 21 12:55:13 PM PST 24
Peak memory 215976 kb
Host smart-5dac83dd-9ca2-4465-8abc-385a2141862f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617267976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.617267976
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.632523380
Short name T380
Test name
Test status
Simulation time 83541477 ps
CPU time 1.09 seconds
Started Feb 21 12:55:02 PM PST 24
Finished Feb 21 12:55:06 PM PST 24
Peak memory 215960 kb
Host smart-a50227c5-6805-4a67-b51e-7c2bc9b2a6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632523380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.632523380
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1193393937
Short name T544
Test name
Test status
Simulation time 62675868 ps
CPU time 1.25 seconds
Started Feb 21 12:55:01 PM PST 24
Finished Feb 21 12:55:03 PM PST 24
Peak memory 215860 kb
Host smart-ae65ea53-74fb-49dc-82c0-8a87affafc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193393937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1193393937
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.714736402
Short name T412
Test name
Test status
Simulation time 29232847 ps
CPU time 1.21 seconds
Started Feb 21 12:55:13 PM PST 24
Finished Feb 21 12:55:15 PM PST 24
Peak memory 217240 kb
Host smart-8b96b7ae-fe2c-44af-9dbc-96160660b372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714736402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.714736402
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2183626373
Short name T780
Test name
Test status
Simulation time 44261517 ps
CPU time 1.08 seconds
Started Feb 21 12:53:38 PM PST 24
Finished Feb 21 12:53:39 PM PST 24
Peak memory 215076 kb
Host smart-20a92974-9017-4169-b288-78462df1592f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183626373 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2183626373
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1204412833
Short name T765
Test name
Test status
Simulation time 151503421 ps
CPU time 0.77 seconds
Started Feb 21 12:53:37 PM PST 24
Finished Feb 21 12:53:38 PM PST 24
Peak memory 205004 kb
Host smart-1c8c273c-adf4-4d31-a48f-3a4671fb6443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204412833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1204412833
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.122966348
Short name T821
Test name
Test status
Simulation time 12896524 ps
CPU time 0.86 seconds
Started Feb 21 12:53:39 PM PST 24
Finished Feb 21 12:53:41 PM PST 24
Peak memory 215144 kb
Host smart-02ee6ca7-e3a7-4ef0-b7ac-07f2d5fbb5de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122966348 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.122966348
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3538177554
Short name T548
Test name
Test status
Simulation time 38112927 ps
CPU time 1.24 seconds
Started Feb 21 12:53:38 PM PST 24
Finished Feb 21 12:53:39 PM PST 24
Peak memory 215828 kb
Host smart-07a4907f-4f3b-4910-b503-18e09496308e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538177554 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3538177554
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.674474819
Short name T638
Test name
Test status
Simulation time 25838307 ps
CPU time 1.28 seconds
Started Feb 21 12:53:37 PM PST 24
Finished Feb 21 12:53:39 PM PST 24
Peak memory 229312 kb
Host smart-05a52b90-1266-414f-8b74-e9f39b456042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674474819 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.674474819
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.65940504
Short name T630
Test name
Test status
Simulation time 43045200 ps
CPU time 1.17 seconds
Started Feb 21 12:53:35 PM PST 24
Finished Feb 21 12:53:37 PM PST 24
Peak memory 216976 kb
Host smart-32db254f-2815-4b34-a960-4899ecd6ab58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65940504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.65940504
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2300882441
Short name T702
Test name
Test status
Simulation time 91362172 ps
CPU time 0.88 seconds
Started Feb 21 12:53:36 PM PST 24
Finished Feb 21 12:53:37 PM PST 24
Peak memory 222492 kb
Host smart-7e408db5-8c08-4340-9ae4-e37c4d8ebb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300882441 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2300882441
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1060508248
Short name T2
Test name
Test status
Simulation time 17284157 ps
CPU time 0.89 seconds
Started Feb 21 12:53:37 PM PST 24
Finished Feb 21 12:53:38 PM PST 24
Peak memory 214760 kb
Host smart-ab312f00-fdd2-4d13-bacf-0e7ee338cd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060508248 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1060508248
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1177074505
Short name T436
Test name
Test status
Simulation time 726954853 ps
CPU time 4.35 seconds
Started Feb 21 12:53:35 PM PST 24
Finished Feb 21 12:53:41 PM PST 24
Peak memory 215860 kb
Host smart-5e1170cc-639d-4295-a215-fec034c3ee41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177074505 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1177074505
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2819874419
Short name T176
Test name
Test status
Simulation time 118260080389 ps
CPU time 1525.23 seconds
Started Feb 21 12:53:34 PM PST 24
Finished Feb 21 01:19:00 PM PST 24
Peak memory 225744 kb
Host smart-1616bc63-9f5f-4b61-9241-cd771a46a7a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819874419 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2819874419
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1490709497
Short name T788
Test name
Test status
Simulation time 220802412 ps
CPU time 1.08 seconds
Started Feb 21 12:55:00 PM PST 24
Finished Feb 21 12:55:02 PM PST 24
Peak memory 215988 kb
Host smart-53c0f6b0-f365-4cc8-ba5a-20de396062d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490709497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1490709497
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3754258830
Short name T680
Test name
Test status
Simulation time 107672146 ps
CPU time 1.22 seconds
Started Feb 21 12:55:12 PM PST 24
Finished Feb 21 12:55:13 PM PST 24
Peak memory 215980 kb
Host smart-2672b46a-de0a-476e-a531-b5524e64735d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754258830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3754258830
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1190404217
Short name T469
Test name
Test status
Simulation time 86311277 ps
CPU time 1.25 seconds
Started Feb 21 12:55:12 PM PST 24
Finished Feb 21 12:55:13 PM PST 24
Peak memory 217308 kb
Host smart-90dbd8a8-1593-479a-87bd-1f29c6c8b8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190404217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1190404217
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1757752317
Short name T658
Test name
Test status
Simulation time 130706697 ps
CPU time 2.54 seconds
Started Feb 21 12:55:12 PM PST 24
Finished Feb 21 12:55:15 PM PST 24
Peak memory 218332 kb
Host smart-47d9a52b-3d36-4344-aa34-582d08869dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757752317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1757752317
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.85051571
Short name T338
Test name
Test status
Simulation time 142253131 ps
CPU time 3.04 seconds
Started Feb 21 12:55:12 PM PST 24
Finished Feb 21 12:55:16 PM PST 24
Peak memory 216160 kb
Host smart-ceee305a-d4cf-412e-8e1d-df6020bd92ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85051571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.85051571
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2340595642
Short name T710
Test name
Test status
Simulation time 93386690 ps
CPU time 1.18 seconds
Started Feb 21 12:55:04 PM PST 24
Finished Feb 21 12:55:07 PM PST 24
Peak memory 217616 kb
Host smart-0fc72e25-9382-491c-b4d8-f67c3fa54976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340595642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2340595642
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.1662368719
Short name T623
Test name
Test status
Simulation time 109772681 ps
CPU time 0.97 seconds
Started Feb 21 12:55:01 PM PST 24
Finished Feb 21 12:55:04 PM PST 24
Peak memory 215984 kb
Host smart-c727946c-542b-4217-9752-fa2ff9ab7167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662368719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1662368719
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3354192018
Short name T189
Test name
Test status
Simulation time 262582210 ps
CPU time 2.9 seconds
Started Feb 21 12:55:02 PM PST 24
Finished Feb 21 12:55:07 PM PST 24
Peak memory 216148 kb
Host smart-e5d21754-b4ef-477f-9ce3-53c0338b6a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354192018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3354192018
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.4236099668
Short name T509
Test name
Test status
Simulation time 36468186 ps
CPU time 1.61 seconds
Started Feb 21 12:55:04 PM PST 24
Finished Feb 21 12:55:08 PM PST 24
Peak memory 217364 kb
Host smart-c1ac6c4f-df3c-45e7-a305-8f3cddb47d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236099668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.4236099668
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1965757952
Short name T142
Test name
Test status
Simulation time 34866300 ps
CPU time 1.27 seconds
Started Feb 21 12:53:44 PM PST 24
Finished Feb 21 12:53:46 PM PST 24
Peak memory 215124 kb
Host smart-abd9d4a4-cbbc-4e35-9a91-e52ed55a8b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965757952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1965757952
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1796387711
Short name T198
Test name
Test status
Simulation time 23286977 ps
CPU time 0.95 seconds
Started Feb 21 12:53:36 PM PST 24
Finished Feb 21 12:53:37 PM PST 24
Peak memory 205852 kb
Host smart-0e4459c0-92e6-4daa-b444-fe3315975a38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796387711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1796387711
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1968085301
Short name T109
Test name
Test status
Simulation time 46066567 ps
CPU time 0.8 seconds
Started Feb 21 12:53:42 PM PST 24
Finished Feb 21 12:53:43 PM PST 24
Peak memory 215140 kb
Host smart-4ac044dd-65eb-4ebc-832f-9d725f8ee339
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968085301 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1968085301
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3883261083
Short name T68
Test name
Test status
Simulation time 25954120 ps
CPU time 0.96 seconds
Started Feb 21 12:53:41 PM PST 24
Finished Feb 21 12:53:42 PM PST 24
Peak memory 215720 kb
Host smart-a79049f5-f55d-452b-9a7b-644841c5860d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883261083 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3883261083
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1371097232
Short name T607
Test name
Test status
Simulation time 21061783 ps
CPU time 1.11 seconds
Started Feb 21 12:53:34 PM PST 24
Finished Feb 21 12:53:36 PM PST 24
Peak memory 230720 kb
Host smart-078a6ae5-8e8b-40b5-98b2-4c0f06fb058b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371097232 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1371097232
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2341508906
Short name T420
Test name
Test status
Simulation time 28088915 ps
CPU time 1.4 seconds
Started Feb 21 12:53:44 PM PST 24
Finished Feb 21 12:53:47 PM PST 24
Peak memory 217056 kb
Host smart-bc75b516-d69c-4a87-a404-6ffbdcf9750a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341508906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2341508906
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.952637200
Short name T582
Test name
Test status
Simulation time 26933375 ps
CPU time 0.91 seconds
Started Feb 21 12:53:37 PM PST 24
Finished Feb 21 12:53:38 PM PST 24
Peak memory 214844 kb
Host smart-5bfad199-4ec8-4bca-8d2d-f77ea0093d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952637200 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.952637200
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1582606048
Short name T443
Test name
Test status
Simulation time 175634797 ps
CPU time 0.87 seconds
Started Feb 21 12:53:37 PM PST 24
Finished Feb 21 12:53:38 PM PST 24
Peak memory 214572 kb
Host smart-8fe20fcb-6a69-459b-94e2-993c7e412583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582606048 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1582606048
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3221354642
Short name T480
Test name
Test status
Simulation time 2725531734 ps
CPU time 3.78 seconds
Started Feb 21 12:53:36 PM PST 24
Finished Feb 21 12:53:40 PM PST 24
Peak memory 214848 kb
Host smart-18c012fb-d30b-474d-8f33-8f5791226cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221354642 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3221354642
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3752954567
Short name T542
Test name
Test status
Simulation time 21984853905 ps
CPU time 519.54 seconds
Started Feb 21 12:53:41 PM PST 24
Finished Feb 21 01:02:21 PM PST 24
Peak memory 215024 kb
Host smart-218068d6-81b9-4a2f-a070-90c19cad1ce4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752954567 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3752954567
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1178482228
Short name T831
Test name
Test status
Simulation time 75428678 ps
CPU time 1.03 seconds
Started Feb 21 12:55:04 PM PST 24
Finished Feb 21 12:55:07 PM PST 24
Peak memory 215788 kb
Host smart-b55732c8-bff1-4af1-ac10-e462a00cd877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178482228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1178482228
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1469688655
Short name T554
Test name
Test status
Simulation time 28052546 ps
CPU time 1 seconds
Started Feb 21 12:55:04 PM PST 24
Finished Feb 21 12:55:07 PM PST 24
Peak memory 217280 kb
Host smart-9b850205-aa90-4658-963d-3cf05bb5f13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469688655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1469688655
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1441019971
Short name T552
Test name
Test status
Simulation time 85247040 ps
CPU time 1.14 seconds
Started Feb 21 12:55:03 PM PST 24
Finished Feb 21 12:55:07 PM PST 24
Peak memory 218284 kb
Host smart-8af6336b-3ed5-425b-a3aa-2743c98c0182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441019971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1441019971
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.901721050
Short name T766
Test name
Test status
Simulation time 76078144 ps
CPU time 1.35 seconds
Started Feb 21 12:55:19 PM PST 24
Finished Feb 21 12:55:21 PM PST 24
Peak memory 219340 kb
Host smart-78d6caac-2e10-4b39-8150-c4bfc8dbfafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901721050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.901721050
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1144834564
Short name T395
Test name
Test status
Simulation time 58219267 ps
CPU time 1.15 seconds
Started Feb 21 12:55:15 PM PST 24
Finished Feb 21 12:55:17 PM PST 24
Peak memory 215992 kb
Host smart-785b41d0-c508-4f03-ab46-a9782b439ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144834564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1144834564
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1730456361
Short name T421
Test name
Test status
Simulation time 58450396 ps
CPU time 1.28 seconds
Started Feb 21 12:55:14 PM PST 24
Finished Feb 21 12:55:16 PM PST 24
Peak memory 214752 kb
Host smart-dae584fe-214c-40d8-91d7-4533e8882065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730456361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1730456361
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1432957358
Short name T656
Test name
Test status
Simulation time 177003237 ps
CPU time 1.05 seconds
Started Feb 21 12:55:15 PM PST 24
Finished Feb 21 12:55:17 PM PST 24
Peak memory 215984 kb
Host smart-131cd4c5-4521-4e22-9cac-5623a6e11039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432957358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1432957358
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1929721082
Short name T687
Test name
Test status
Simulation time 345928801 ps
CPU time 4.56 seconds
Started Feb 21 12:55:19 PM PST 24
Finished Feb 21 12:55:25 PM PST 24
Peak memory 219300 kb
Host smart-1046b8f7-e386-43bd-a77c-8f00eddf79d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929721082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1929721082
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1388479575
Short name T374
Test name
Test status
Simulation time 51871350 ps
CPU time 1.1 seconds
Started Feb 21 12:55:23 PM PST 24
Finished Feb 21 12:55:25 PM PST 24
Peak memory 215864 kb
Host smart-ec58717b-0b55-434c-8976-291636481f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388479575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1388479575
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1495186052
Short name T672
Test name
Test status
Simulation time 101338266 ps
CPU time 1.22 seconds
Started Feb 21 12:52:28 PM PST 24
Finished Feb 21 12:52:31 PM PST 24
Peak memory 215112 kb
Host smart-2c88c799-d32e-4979-8a6a-f631c1a2d9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495186052 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1495186052
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1059085640
Short name T482
Test name
Test status
Simulation time 45403286 ps
CPU time 0.89 seconds
Started Feb 21 12:52:29 PM PST 24
Finished Feb 21 12:52:30 PM PST 24
Peak memory 205424 kb
Host smart-8a8e0815-039f-4380-9c35-5a6c96de24cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059085640 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1059085640
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1832127275
Short name T683
Test name
Test status
Simulation time 46619353 ps
CPU time 0.83 seconds
Started Feb 21 12:52:33 PM PST 24
Finished Feb 21 12:52:34 PM PST 24
Peak memory 214860 kb
Host smart-7c7f67c9-53c3-4979-b640-74138510356c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832127275 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1832127275
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2328895039
Short name T790
Test name
Test status
Simulation time 202573105 ps
CPU time 1.24 seconds
Started Feb 21 12:52:30 PM PST 24
Finished Feb 21 12:52:32 PM PST 24
Peak memory 216000 kb
Host smart-091a67f7-1654-4f8c-a978-7c77e6f08661
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328895039 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2328895039
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2052777547
Short name T575
Test name
Test status
Simulation time 47893671 ps
CPU time 1.03 seconds
Started Feb 21 12:52:32 PM PST 24
Finished Feb 21 12:52:33 PM PST 24
Peak memory 218840 kb
Host smart-6915b5f5-8f2a-4a9f-a6d0-98737ef24774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052777547 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2052777547
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.962288179
Short name T506
Test name
Test status
Simulation time 65563933 ps
CPU time 2.06 seconds
Started Feb 21 12:52:35 PM PST 24
Finished Feb 21 12:52:38 PM PST 24
Peak memory 218688 kb
Host smart-02876590-89df-4e3e-b915-631ebf9e5fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962288179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.962288179
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3820732005
Short name T645
Test name
Test status
Simulation time 22338322 ps
CPU time 1 seconds
Started Feb 21 12:52:28 PM PST 24
Finished Feb 21 12:52:30 PM PST 24
Peak memory 215244 kb
Host smart-47d9cb1a-31d8-4b0d-af47-6012d254b3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820732005 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3820732005
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_smoke.153235054
Short name T838
Test name
Test status
Simulation time 15236921 ps
CPU time 0.9 seconds
Started Feb 21 12:52:34 PM PST 24
Finished Feb 21 12:52:35 PM PST 24
Peak memory 214748 kb
Host smart-fe79521c-0b8b-409e-b43a-b5cbcaae470c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153235054 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.153235054
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.122371147
Short name T131
Test name
Test status
Simulation time 2576320690 ps
CPU time 3.15 seconds
Started Feb 21 12:52:42 PM PST 24
Finished Feb 21 12:52:46 PM PST 24
Peak memory 215944 kb
Host smart-61590359-b413-41ab-90f4-230ce039a5b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122371147 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.122371147
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.679086589
Short name T718
Test name
Test status
Simulation time 161300911283 ps
CPU time 1661.78 seconds
Started Feb 21 12:52:31 PM PST 24
Finished Feb 21 01:20:14 PM PST 24
Peak memory 223524 kb
Host smart-1d26821e-b468-4ad9-8cd7-a9e159101867
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679086589 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.679086589
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3567589044
Short name T803
Test name
Test status
Simulation time 26938755 ps
CPU time 1.25 seconds
Started Feb 21 12:53:39 PM PST 24
Finished Feb 21 12:53:41 PM PST 24
Peak memory 215160 kb
Host smart-b7c401a0-a9bd-4624-995c-6b061eea659b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567589044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3567589044
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1488494345
Short name T523
Test name
Test status
Simulation time 112074501 ps
CPU time 0.98 seconds
Started Feb 21 12:53:41 PM PST 24
Finished Feb 21 12:53:43 PM PST 24
Peak memory 206320 kb
Host smart-d0b477b9-b6d5-41f3-9139-7ff54f89787f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488494345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1488494345
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1870072554
Short name T85
Test name
Test status
Simulation time 19195309 ps
CPU time 0.86 seconds
Started Feb 21 12:53:44 PM PST 24
Finished Feb 21 12:53:46 PM PST 24
Peak memory 215148 kb
Host smart-2678cd44-a400-43ff-897d-a00ca33e743c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870072554 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1870072554
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.164935479
Short name T578
Test name
Test status
Simulation time 25257858 ps
CPU time 1.02 seconds
Started Feb 21 12:53:39 PM PST 24
Finished Feb 21 12:53:41 PM PST 24
Peak memory 215848 kb
Host smart-2f4d0385-5047-4b2e-9d42-f0c6b37db5c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164935479 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.164935479
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3111024691
Short name T536
Test name
Test status
Simulation time 24143984 ps
CPU time 0.86 seconds
Started Feb 21 12:53:42 PM PST 24
Finished Feb 21 12:53:43 PM PST 24
Peak memory 217116 kb
Host smart-cde00b05-878c-4b82-882f-1d43cf4c8f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111024691 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3111024691
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1490269055
Short name T562
Test name
Test status
Simulation time 89373279 ps
CPU time 1.92 seconds
Started Feb 21 12:53:36 PM PST 24
Finished Feb 21 12:53:39 PM PST 24
Peak memory 216188 kb
Host smart-878d2096-b464-4d93-9833-d265b595bdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490269055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1490269055
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3338082362
Short name T510
Test name
Test status
Simulation time 71503920 ps
CPU time 0.82 seconds
Started Feb 21 12:53:42 PM PST 24
Finished Feb 21 12:53:44 PM PST 24
Peak memory 214556 kb
Host smart-dc345266-f1b4-4fac-815f-bff61c3a6a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338082362 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3338082362
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2292091588
Short name T329
Test name
Test status
Simulation time 34846471 ps
CPU time 0.85 seconds
Started Feb 21 12:53:39 PM PST 24
Finished Feb 21 12:53:41 PM PST 24
Peak memory 214528 kb
Host smart-08c7807f-18b4-4eb7-9321-59cbd894cc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292091588 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2292091588
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2810470635
Short name T365
Test name
Test status
Simulation time 682163301 ps
CPU time 3.94 seconds
Started Feb 21 12:53:45 PM PST 24
Finished Feb 21 12:53:49 PM PST 24
Peak memory 215740 kb
Host smart-7b20f5bd-7844-4621-880e-5920fb6cca51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810470635 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2810470635
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2478333425
Short name T483
Test name
Test status
Simulation time 158604330279 ps
CPU time 893.29 seconds
Started Feb 21 12:53:44 PM PST 24
Finished Feb 21 01:08:38 PM PST 24
Peak memory 220956 kb
Host smart-d0417391-3fc8-462d-88fc-a4094c2bb2e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478333425 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2478333425
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1684920259
Short name T756
Test name
Test status
Simulation time 65117213 ps
CPU time 1.09 seconds
Started Feb 21 12:53:44 PM PST 24
Finished Feb 21 12:53:46 PM PST 24
Peak memory 215104 kb
Host smart-1a9980ec-6885-4a2d-b7b6-a4aeaab70295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684920259 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1684920259
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3603049906
Short name T521
Test name
Test status
Simulation time 19469422 ps
CPU time 0.98 seconds
Started Feb 21 12:53:38 PM PST 24
Finished Feb 21 12:53:40 PM PST 24
Peak memory 205504 kb
Host smart-3f062819-4e3e-47cb-aac7-dc17242193da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603049906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3603049906
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.986221341
Short name T33
Test name
Test status
Simulation time 26411258 ps
CPU time 0.86 seconds
Started Feb 21 12:53:42 PM PST 24
Finished Feb 21 12:53:43 PM PST 24
Peak memory 215124 kb
Host smart-6257d262-fdfd-4aab-9a82-cf151a8c9ea6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986221341 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.986221341
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.590844951
Short name T78
Test name
Test status
Simulation time 57433261 ps
CPU time 1.12 seconds
Started Feb 21 12:53:43 PM PST 24
Finished Feb 21 12:53:45 PM PST 24
Peak memory 215960 kb
Host smart-7d064f1e-02fb-4767-85c3-caf92976f9dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590844951 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_di
sable_auto_req_mode.590844951
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2574567676
Short name T555
Test name
Test status
Simulation time 26896068 ps
CPU time 0.98 seconds
Started Feb 21 12:53:42 PM PST 24
Finished Feb 21 12:53:43 PM PST 24
Peak memory 222444 kb
Host smart-091d2c97-4db7-4dab-99af-1dd3fb106735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574567676 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2574567676
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3244285690
Short name T27
Test name
Test status
Simulation time 122660888 ps
CPU time 2.72 seconds
Started Feb 21 12:53:44 PM PST 24
Finished Feb 21 12:53:47 PM PST 24
Peak memory 217480 kb
Host smart-8963d6d4-8d00-4a2c-b39e-40b00217eb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244285690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3244285690
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3608902025
Short name T312
Test name
Test status
Simulation time 22883151 ps
CPU time 1.08 seconds
Started Feb 21 12:53:43 PM PST 24
Finished Feb 21 12:53:45 PM PST 24
Peak memory 215036 kb
Host smart-a82298d0-4bf8-44a0-b9c6-c4f75bf648e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608902025 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3608902025
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2184826873
Short name T833
Test name
Test status
Simulation time 138493021 ps
CPU time 0.84 seconds
Started Feb 21 12:53:41 PM PST 24
Finished Feb 21 12:53:42 PM PST 24
Peak memory 214732 kb
Host smart-c758c47a-7d81-4106-bd45-dab720726e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184826873 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2184826873
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.428364792
Short name T522
Test name
Test status
Simulation time 323491173 ps
CPU time 3.68 seconds
Started Feb 21 12:53:40 PM PST 24
Finished Feb 21 12:53:45 PM PST 24
Peak memory 214768 kb
Host smart-1c0f6890-97b8-47f0-a2c0-f8b176040c21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428364792 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.428364792
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2088067176
Short name T24
Test name
Test status
Simulation time 25663327000 ps
CPU time 565.65 seconds
Started Feb 21 12:53:42 PM PST 24
Finished Feb 21 01:03:08 PM PST 24
Peak memory 217124 kb
Host smart-8635ec06-41a3-41c5-965d-fd1ae3acc92e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088067176 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2088067176
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.4125949110
Short name T271
Test name
Test status
Simulation time 29640802 ps
CPU time 1.31 seconds
Started Feb 21 12:53:39 PM PST 24
Finished Feb 21 12:53:41 PM PST 24
Peak memory 215116 kb
Host smart-3e666b64-8d0e-4ad7-b9d2-61d32d591e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125949110 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.4125949110
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.128397187
Short name T835
Test name
Test status
Simulation time 108969657 ps
CPU time 0.83 seconds
Started Feb 21 12:53:41 PM PST 24
Finished Feb 21 12:53:43 PM PST 24
Peak memory 206100 kb
Host smart-63ccf0a2-79e7-4b83-86e9-7ea99af53ac1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128397187 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.128397187
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2447315268
Short name T826
Test name
Test status
Simulation time 38950545 ps
CPU time 0.86 seconds
Started Feb 21 12:53:40 PM PST 24
Finished Feb 21 12:53:41 PM PST 24
Peak memory 215156 kb
Host smart-fd83f271-fd5b-4c41-93a2-d7a706566eff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447315268 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2447315268
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_err.3729182939
Short name T152
Test name
Test status
Simulation time 22138958 ps
CPU time 1.12 seconds
Started Feb 21 12:53:38 PM PST 24
Finished Feb 21 12:53:39 PM PST 24
Peak memory 218880 kb
Host smart-06d0683a-4ed9-43da-8ef0-6095cc0335f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729182939 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3729182939
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1385615376
Short name T294
Test name
Test status
Simulation time 57378386 ps
CPU time 1.79 seconds
Started Feb 21 12:53:43 PM PST 24
Finished Feb 21 12:53:45 PM PST 24
Peak memory 217156 kb
Host smart-869e81c7-98e5-4ad7-a73e-5deee6236fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385615376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1385615376
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.134918924
Short name T124
Test name
Test status
Simulation time 40074706 ps
CPU time 0.79 seconds
Started Feb 21 12:53:44 PM PST 24
Finished Feb 21 12:53:45 PM PST 24
Peak memory 215004 kb
Host smart-9f174eb8-6732-455a-b914-8e94fc1ef7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134918924 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.134918924
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.629442786
Short name T438
Test name
Test status
Simulation time 17117541 ps
CPU time 0.94 seconds
Started Feb 21 12:53:44 PM PST 24
Finished Feb 21 12:53:45 PM PST 24
Peak memory 214624 kb
Host smart-9f1e5a72-596c-4ae0-80a7-b1667c1b8ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629442786 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.629442786
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2354078305
Short name T418
Test name
Test status
Simulation time 761487636 ps
CPU time 4.57 seconds
Started Feb 21 12:53:36 PM PST 24
Finished Feb 21 12:53:41 PM PST 24
Peak memory 214824 kb
Host smart-924a8388-51a0-43fa-a4a7-5cff576d8bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354078305 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2354078305
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_alert_test.2596892844
Short name T635
Test name
Test status
Simulation time 120128131 ps
CPU time 0.82 seconds
Started Feb 21 12:53:44 PM PST 24
Finished Feb 21 12:53:46 PM PST 24
Peak memory 205492 kb
Host smart-a04bb0d3-85c5-4220-9c11-728d991d4861
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596892844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2596892844
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2044354628
Short name T151
Test name
Test status
Simulation time 43494105 ps
CPU time 1.08 seconds
Started Feb 21 12:53:49 PM PST 24
Finished Feb 21 12:53:51 PM PST 24
Peak memory 216156 kb
Host smart-538505b5-a04d-4281-a305-b1963b1f5596
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044354628 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2044354628
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.697296687
Short name T458
Test name
Test status
Simulation time 29090817 ps
CPU time 0.8 seconds
Started Feb 21 12:53:40 PM PST 24
Finished Feb 21 12:53:42 PM PST 24
Peak memory 216992 kb
Host smart-c0e5f9b3-bc13-4958-b7be-6775191ee711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697296687 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.697296687
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3948497925
Short name T42
Test name
Test status
Simulation time 58690891 ps
CPU time 1.01 seconds
Started Feb 21 12:53:36 PM PST 24
Finished Feb 21 12:53:38 PM PST 24
Peak memory 216420 kb
Host smart-93d40f5c-15dc-490a-9cfb-99aeec7d954f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948497925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3948497925
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1939051773
Short name T393
Test name
Test status
Simulation time 25280031 ps
CPU time 1.05 seconds
Started Feb 21 12:53:44 PM PST 24
Finished Feb 21 12:53:46 PM PST 24
Peak memory 214948 kb
Host smart-38a1a1f1-cb65-4af3-817c-7694d8315eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939051773 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1939051773
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3573548943
Short name T626
Test name
Test status
Simulation time 21220053 ps
CPU time 0.89 seconds
Started Feb 21 12:53:39 PM PST 24
Finished Feb 21 12:53:40 PM PST 24
Peak memory 214732 kb
Host smart-c9fa945a-4187-4791-9628-6146ace1b322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573548943 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3573548943
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.4024880023
Short name T674
Test name
Test status
Simulation time 92906733 ps
CPU time 2.31 seconds
Started Feb 21 12:53:37 PM PST 24
Finished Feb 21 12:53:39 PM PST 24
Peak memory 215880 kb
Host smart-6cb9200e-5e92-4f72-8179-1b9011470ca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024880023 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.4024880023
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1403898915
Short name T185
Test name
Test status
Simulation time 122166432160 ps
CPU time 1907.08 seconds
Started Feb 21 12:53:40 PM PST 24
Finished Feb 21 01:25:28 PM PST 24
Peak memory 224972 kb
Host smart-f2478a16-5f4e-4bc1-b17c-32932f88082c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403898915 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1403898915
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert_test.84415782
Short name T441
Test name
Test status
Simulation time 109706122 ps
CPU time 0.94 seconds
Started Feb 21 12:53:44 PM PST 24
Finished Feb 21 12:53:46 PM PST 24
Peak memory 205496 kb
Host smart-18757071-7791-4a98-b2e4-6645d13640fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84415782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.84415782
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.448928848
Short name T524
Test name
Test status
Simulation time 12169561 ps
CPU time 0.85 seconds
Started Feb 21 12:53:48 PM PST 24
Finished Feb 21 12:53:49 PM PST 24
Peak memory 214968 kb
Host smart-37510f33-0d59-4d71-9d90-be652d721c61
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448928848 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.448928848
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3464185571
Short name T46
Test name
Test status
Simulation time 53992237 ps
CPU time 1.11 seconds
Started Feb 21 12:53:52 PM PST 24
Finished Feb 21 12:53:53 PM PST 24
Peak memory 217196 kb
Host smart-87df90d1-b287-4514-bed0-3ea9cac13a8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464185571 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3464185571
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.94822528
Short name T378
Test name
Test status
Simulation time 22152110 ps
CPU time 0.88 seconds
Started Feb 21 12:53:49 PM PST 24
Finished Feb 21 12:53:50 PM PST 24
Peak memory 217028 kb
Host smart-a4e9e217-b2ab-4533-a72c-ca9c3861d561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94822528 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.94822528
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2738740759
Short name T381
Test name
Test status
Simulation time 144535123 ps
CPU time 1.1 seconds
Started Feb 21 12:53:47 PM PST 24
Finished Feb 21 12:53:48 PM PST 24
Peak memory 215872 kb
Host smart-8adc898e-6755-4c67-9736-401c5aabd9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738740759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2738740759
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.965618030
Short name T768
Test name
Test status
Simulation time 22743849 ps
CPU time 1.22 seconds
Started Feb 21 12:53:47 PM PST 24
Finished Feb 21 12:53:48 PM PST 24
Peak memory 222872 kb
Host smart-2f5d938c-24c2-492a-bbe2-decc1d14a506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965618030 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.965618030
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.793521489
Short name T549
Test name
Test status
Simulation time 22745482 ps
CPU time 0.85 seconds
Started Feb 21 12:53:43 PM PST 24
Finished Feb 21 12:53:45 PM PST 24
Peak memory 214728 kb
Host smart-d65cc53f-a911-4e6b-9831-725ff71b05ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793521489 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.793521489
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2562922120
Short name T460
Test name
Test status
Simulation time 398711660 ps
CPU time 2.66 seconds
Started Feb 21 12:53:42 PM PST 24
Finished Feb 21 12:53:45 PM PST 24
Peak memory 214628 kb
Host smart-52c61f3e-f14d-45b2-8b98-477e19dc2ebc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562922120 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2562922120
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1886131202
Short name T546
Test name
Test status
Simulation time 158251117186 ps
CPU time 780.44 seconds
Started Feb 21 12:53:49 PM PST 24
Finished Feb 21 01:06:49 PM PST 24
Peak memory 223132 kb
Host smart-25becb8b-176c-4357-a3f2-2abf56401053
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886131202 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1886131202
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1125339120
Short name T93
Test name
Test status
Simulation time 83401732 ps
CPU time 1.16 seconds
Started Feb 21 12:53:47 PM PST 24
Finished Feb 21 12:53:48 PM PST 24
Peak memory 215124 kb
Host smart-a5c4656b-4112-4cf8-ba1e-35c9026d6d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125339120 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1125339120
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.584035009
Short name T400
Test name
Test status
Simulation time 68604317 ps
CPU time 0.84 seconds
Started Feb 21 12:53:42 PM PST 24
Finished Feb 21 12:53:44 PM PST 24
Peak memory 205964 kb
Host smart-9856911b-9b57-41cb-89c3-37e5ac532c87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584035009 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.584035009
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2756810477
Short name T84
Test name
Test status
Simulation time 22352864 ps
CPU time 0.86 seconds
Started Feb 21 12:53:45 PM PST 24
Finished Feb 21 12:53:46 PM PST 24
Peak memory 214752 kb
Host smart-db701110-d16a-44f8-b194-5ab8847af3d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756810477 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2756810477
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_err.1810390695
Short name T34
Test name
Test status
Simulation time 53143927 ps
CPU time 0.9 seconds
Started Feb 21 12:53:44 PM PST 24
Finished Feb 21 12:53:45 PM PST 24
Peak memory 222328 kb
Host smart-64c5e003-0752-4fe5-bdc0-ea031b4a65d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810390695 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1810390695
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2772255527
Short name T397
Test name
Test status
Simulation time 38700662 ps
CPU time 1.37 seconds
Started Feb 21 12:53:49 PM PST 24
Finished Feb 21 12:53:51 PM PST 24
Peak memory 215848 kb
Host smart-057d161e-901b-4998-a486-6122255a3929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772255527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2772255527
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.965413099
Short name T829
Test name
Test status
Simulation time 22654544 ps
CPU time 1.04 seconds
Started Feb 21 12:53:45 PM PST 24
Finished Feb 21 12:53:47 PM PST 24
Peak memory 214416 kb
Host smart-a8e7ccd2-4ee7-40ec-bf4e-b1272dfcd73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965413099 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.965413099
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.599055781
Short name T812
Test name
Test status
Simulation time 42603562 ps
CPU time 0.85 seconds
Started Feb 21 12:53:48 PM PST 24
Finished Feb 21 12:53:49 PM PST 24
Peak memory 214696 kb
Host smart-16742eee-7dda-45c7-8db3-4825ebd4a28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599055781 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.599055781
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1353188372
Short name T199
Test name
Test status
Simulation time 303438651 ps
CPU time 3.29 seconds
Started Feb 21 12:53:51 PM PST 24
Finished Feb 21 12:53:55 PM PST 24
Peak memory 217224 kb
Host smart-4aec4d12-8be8-4f9d-af3b-30032aa55b44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353188372 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1353188372
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1701870251
Short name T444
Test name
Test status
Simulation time 37174342833 ps
CPU time 385.68 seconds
Started Feb 21 12:53:44 PM PST 24
Finished Feb 21 01:00:10 PM PST 24
Peak memory 218036 kb
Host smart-20bd94b1-c6db-4ccf-97e0-1b413f09a9a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701870251 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1701870251
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3567408355
Short name T88
Test name
Test status
Simulation time 31894622 ps
CPU time 1.32 seconds
Started Feb 21 12:53:49 PM PST 24
Finished Feb 21 12:53:51 PM PST 24
Peak memory 215128 kb
Host smart-060e04d9-864b-4ad5-860a-97ccfd9d5652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567408355 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3567408355
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3141190507
Short name T815
Test name
Test status
Simulation time 18281101 ps
CPU time 0.95 seconds
Started Feb 21 12:53:49 PM PST 24
Finished Feb 21 12:53:50 PM PST 24
Peak memory 206336 kb
Host smart-ee6e7e80-a161-4879-bbcd-12cc2f5895e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141190507 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3141190507
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2058133525
Short name T800
Test name
Test status
Simulation time 12581158 ps
CPU time 0.85 seconds
Started Feb 21 12:53:40 PM PST 24
Finished Feb 21 12:53:41 PM PST 24
Peak memory 215428 kb
Host smart-3b7a3c76-a2ff-45df-b19c-98759cfe3397
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058133525 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2058133525
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_err.1538109883
Short name T341
Test name
Test status
Simulation time 33598980 ps
CPU time 0.89 seconds
Started Feb 21 12:53:46 PM PST 24
Finished Feb 21 12:53:47 PM PST 24
Peak memory 217696 kb
Host smart-63734e19-5f20-4ce8-b76a-9d3a2e57537d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538109883 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1538109883
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1839712165
Short name T714
Test name
Test status
Simulation time 42384034 ps
CPU time 1.04 seconds
Started Feb 21 12:53:44 PM PST 24
Finished Feb 21 12:53:45 PM PST 24
Peak memory 215952 kb
Host smart-c857e8a1-8e01-41fa-b090-e72c1e44c8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839712165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1839712165
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3066896933
Short name T439
Test name
Test status
Simulation time 22691656 ps
CPU time 1.05 seconds
Started Feb 21 12:53:44 PM PST 24
Finished Feb 21 12:53:45 PM PST 24
Peak memory 215032 kb
Host smart-2b44a067-cf22-41b1-8744-9216d808b4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066896933 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3066896933
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1725367461
Short name T331
Test name
Test status
Simulation time 187042776 ps
CPU time 0.94 seconds
Started Feb 21 12:53:47 PM PST 24
Finished Feb 21 12:53:48 PM PST 24
Peak memory 214536 kb
Host smart-e99c432b-9896-43a3-910a-132a2ddc8006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725367461 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1725367461
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3184652773
Short name T132
Test name
Test status
Simulation time 1326024990 ps
CPU time 4.41 seconds
Started Feb 21 12:53:44 PM PST 24
Finished Feb 21 12:53:50 PM PST 24
Peak memory 215844 kb
Host smart-f1f11b1a-503a-4cf7-adea-c9d25cc79829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184652773 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3184652773
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2695945619
Short name T181
Test name
Test status
Simulation time 54749222343 ps
CPU time 602.5 seconds
Started Feb 21 12:53:52 PM PST 24
Finished Feb 21 01:03:55 PM PST 24
Peak memory 217804 kb
Host smart-e3d35720-c593-4851-b639-b59f6b78c915
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695945619 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2695945619
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3178222500
Short name T814
Test name
Test status
Simulation time 46258385 ps
CPU time 1.15 seconds
Started Feb 21 12:53:47 PM PST 24
Finished Feb 21 12:53:48 PM PST 24
Peak memory 215120 kb
Host smart-e086155d-616e-454d-a756-5618f92bfa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178222500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3178222500
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.4020046836
Short name T373
Test name
Test status
Simulation time 38934098 ps
CPU time 0.99 seconds
Started Feb 21 12:53:47 PM PST 24
Finished Feb 21 12:53:49 PM PST 24
Peak memory 206008 kb
Host smart-3138599d-ee03-471c-91b4-22e85c35a8aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020046836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.4020046836
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2273664992
Short name T736
Test name
Test status
Simulation time 22637373 ps
CPU time 0.85 seconds
Started Feb 21 12:53:47 PM PST 24
Finished Feb 21 12:53:49 PM PST 24
Peak memory 214892 kb
Host smart-5ac77f17-1a5f-466e-a90e-4e4151d062d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273664992 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2273664992
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2614980930
Short name T70
Test name
Test status
Simulation time 53714582 ps
CPU time 1.09 seconds
Started Feb 21 12:53:53 PM PST 24
Finished Feb 21 12:53:54 PM PST 24
Peak memory 217068 kb
Host smart-86edb6ea-139e-4551-8602-724b639d449f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614980930 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2614980930
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3772564754
Short name T37
Test name
Test status
Simulation time 23933328 ps
CPU time 1.04 seconds
Started Feb 21 12:53:49 PM PST 24
Finished Feb 21 12:53:51 PM PST 24
Peak memory 222556 kb
Host smart-62e925e0-5665-4359-a73d-458287d9091b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772564754 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3772564754
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1911070724
Short name T292
Test name
Test status
Simulation time 51888751 ps
CPU time 1.31 seconds
Started Feb 21 12:53:52 PM PST 24
Finished Feb 21 12:53:54 PM PST 24
Peak memory 217492 kb
Host smart-07c5395d-0c28-45e9-815c-6cbd2b4996be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911070724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1911070724
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2310089059
Short name T344
Test name
Test status
Simulation time 24664002 ps
CPU time 0.94 seconds
Started Feb 21 12:53:49 PM PST 24
Finished Feb 21 12:53:51 PM PST 24
Peak memory 214880 kb
Host smart-237151e5-3d80-4849-95b2-37bc37af8929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310089059 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2310089059
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3115201330
Short name T604
Test name
Test status
Simulation time 15649357 ps
CPU time 0.96 seconds
Started Feb 21 12:53:48 PM PST 24
Finished Feb 21 12:53:50 PM PST 24
Peak memory 214740 kb
Host smart-d759d5bf-9ea2-4bae-ae94-7137024a22ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115201330 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3115201330
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3230253328
Short name T200
Test name
Test status
Simulation time 489796750 ps
CPU time 5.89 seconds
Started Feb 21 12:53:48 PM PST 24
Finished Feb 21 12:53:55 PM PST 24
Peak memory 217152 kb
Host smart-d7b0a7eb-145b-4cf7-bc51-eb48223bddfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230253328 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3230253328
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1376960724
Short name T743
Test name
Test status
Simulation time 86330183748 ps
CPU time 2152.76 seconds
Started Feb 21 12:53:46 PM PST 24
Finished Feb 21 01:29:40 PM PST 24
Peak memory 229628 kb
Host smart-55db5348-b638-487f-a222-75db5cfd5455
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376960724 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1376960724
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3507567260
Short name T92
Test name
Test status
Simulation time 83529620 ps
CPU time 1 seconds
Started Feb 21 12:53:45 PM PST 24
Finished Feb 21 12:53:47 PM PST 24
Peak memory 215128 kb
Host smart-551148a5-cec3-40b4-a960-3afba9355f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507567260 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3507567260
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.4172024120
Short name T141
Test name
Test status
Simulation time 14022297 ps
CPU time 0.89 seconds
Started Feb 21 12:53:47 PM PST 24
Finished Feb 21 12:53:48 PM PST 24
Peak memory 206556 kb
Host smart-12f0abe6-2fa9-4d63-a137-783b4d8e1e32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172024120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.4172024120
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2149128980
Short name T172
Test name
Test status
Simulation time 16663653 ps
CPU time 0.88 seconds
Started Feb 21 12:54:00 PM PST 24
Finished Feb 21 12:54:01 PM PST 24
Peak memory 214988 kb
Host smart-167d2509-4646-4dae-a881-65b9ddc323a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149128980 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2149128980
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.1670808960
Short name T538
Test name
Test status
Simulation time 18569288 ps
CPU time 0.98 seconds
Started Feb 21 12:53:58 PM PST 24
Finished Feb 21 12:53:59 PM PST 24
Peak memory 217180 kb
Host smart-05930fa7-a684-4e70-8e82-a62193f67036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670808960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1670808960
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.384721928
Short name T708
Test name
Test status
Simulation time 40253024 ps
CPU time 1.39 seconds
Started Feb 21 12:53:47 PM PST 24
Finished Feb 21 12:53:49 PM PST 24
Peak memory 216288 kb
Host smart-3638c9bd-330b-422b-8b00-804915a7b269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384721928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.384721928
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1487244412
Short name T797
Test name
Test status
Simulation time 48676817 ps
CPU time 0.96 seconds
Started Feb 21 12:54:00 PM PST 24
Finished Feb 21 12:54:01 PM PST 24
Peak memory 223240 kb
Host smart-258791eb-b7bc-499e-90f5-996367df2271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487244412 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1487244412
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1604735071
Short name T370
Test name
Test status
Simulation time 17380316 ps
CPU time 1.05 seconds
Started Feb 21 12:53:51 PM PST 24
Finished Feb 21 12:53:53 PM PST 24
Peak memory 214756 kb
Host smart-2186ceb0-4479-4edb-9972-a0d800c16f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604735071 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1604735071
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.1945620237
Short name T669
Test name
Test status
Simulation time 176858741 ps
CPU time 2.14 seconds
Started Feb 21 12:53:58 PM PST 24
Finished Feb 21 12:54:01 PM PST 24
Peak memory 215780 kb
Host smart-1dd6d8da-5adf-452f-81c4-bb81d67a3146
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945620237 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1945620237
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.4065530369
Short name T587
Test name
Test status
Simulation time 557060099479 ps
CPU time 3532.04 seconds
Started Feb 21 12:53:53 PM PST 24
Finished Feb 21 01:52:46 PM PST 24
Peak memory 237676 kb
Host smart-375ef95a-6650-44c9-9514-e9b2c8e1f9a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065530369 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.4065530369
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2538963909
Short name T169
Test name
Test status
Simulation time 25434016 ps
CPU time 1.21 seconds
Started Feb 21 12:53:53 PM PST 24
Finished Feb 21 12:53:54 PM PST 24
Peak memory 215028 kb
Host smart-be7d1a6e-1b32-4c5d-a64f-e202ecdfe419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538963909 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2538963909
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1270774551
Short name T670
Test name
Test status
Simulation time 81225154 ps
CPU time 0.79 seconds
Started Feb 21 12:53:44 PM PST 24
Finished Feb 21 12:53:45 PM PST 24
Peak memory 205724 kb
Host smart-71c767b0-21ab-4d91-a35e-96a3089ef5b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270774551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1270774551
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3850522258
Short name T772
Test name
Test status
Simulation time 54815223 ps
CPU time 0.8 seconds
Started Feb 21 12:53:58 PM PST 24
Finished Feb 21 12:53:59 PM PST 24
Peak memory 214776 kb
Host smart-fea1595d-e410-4f58-87b3-a5c7b8f44248
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850522258 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3850522258
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.349453964
Short name T537
Test name
Test status
Simulation time 108872607 ps
CPU time 0.96 seconds
Started Feb 21 12:53:58 PM PST 24
Finished Feb 21 12:53:59 PM PST 24
Peak memory 216784 kb
Host smart-dd38accc-2f93-4376-8735-8cb0e4044eaf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349453964 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.349453964
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.882606175
Short name T38
Test name
Test status
Simulation time 29165343 ps
CPU time 1.24 seconds
Started Feb 21 12:53:43 PM PST 24
Finished Feb 21 12:53:45 PM PST 24
Peak memory 223580 kb
Host smart-5d0afc65-d048-4b36-9402-9ad77874c704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882606175 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.882606175
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2006884847
Short name T320
Test name
Test status
Simulation time 52045800 ps
CPU time 1.72 seconds
Started Feb 21 12:53:43 PM PST 24
Finished Feb 21 12:53:45 PM PST 24
Peak memory 218812 kb
Host smart-a82d101b-7b93-49ab-ad44-6ace1d70b6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006884847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2006884847
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.4214436756
Short name T698
Test name
Test status
Simulation time 29367324 ps
CPU time 0.97 seconds
Started Feb 21 12:53:53 PM PST 24
Finished Feb 21 12:53:54 PM PST 24
Peak memory 214944 kb
Host smart-15924194-1cae-41db-b59a-53960fb39d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214436756 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.4214436756
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.341633532
Short name T593
Test name
Test status
Simulation time 16552039 ps
CPU time 0.95 seconds
Started Feb 21 12:53:52 PM PST 24
Finished Feb 21 12:53:53 PM PST 24
Peak memory 214780 kb
Host smart-b9472249-265f-4328-b076-d6a86ef046b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341633532 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.341633532
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2126395742
Short name T324
Test name
Test status
Simulation time 192678740 ps
CPU time 2.39 seconds
Started Feb 21 12:53:57 PM PST 24
Finished Feb 21 12:54:00 PM PST 24
Peak memory 214732 kb
Host smart-aefc0623-2ac1-4583-b550-414d9a97467f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126395742 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2126395742
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_alert_test.798845609
Short name T304
Test name
Test status
Simulation time 32097782 ps
CPU time 0.95 seconds
Started Feb 21 12:52:33 PM PST 24
Finished Feb 21 12:52:34 PM PST 24
Peak memory 205908 kb
Host smart-5db5fcc6-9cc0-4f75-8def-35f2bdbecaf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798845609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.798845609
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1397654415
Short name T570
Test name
Test status
Simulation time 38402979 ps
CPU time 0.85 seconds
Started Feb 21 12:52:28 PM PST 24
Finished Feb 21 12:52:30 PM PST 24
Peak memory 214852 kb
Host smart-9306965e-f2ea-44cb-b696-ae71fbf6af97
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397654415 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1397654415
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2773702775
Short name T359
Test name
Test status
Simulation time 30807621 ps
CPU time 1.01 seconds
Started Feb 21 12:52:27 PM PST 24
Finished Feb 21 12:52:28 PM PST 24
Peak memory 216976 kb
Host smart-d1b7372e-bb21-43c1-82b6-c6515f73a50e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773702775 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2773702775
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1136216211
Short name T804
Test name
Test status
Simulation time 33423693 ps
CPU time 0.81 seconds
Started Feb 21 12:52:33 PM PST 24
Finished Feb 21 12:52:34 PM PST 24
Peak memory 217020 kb
Host smart-16cf7e18-beeb-4646-b152-682b0e1bad63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136216211 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1136216211
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.167172913
Short name T733
Test name
Test status
Simulation time 279930922 ps
CPU time 3.84 seconds
Started Feb 21 12:52:28 PM PST 24
Finished Feb 21 12:52:33 PM PST 24
Peak memory 218628 kb
Host smart-db5da1ee-9dba-4721-94c2-0464be9c34cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167172913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.167172913
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.719427620
Short name T595
Test name
Test status
Simulation time 21619686 ps
CPU time 0.99 seconds
Started Feb 21 12:52:27 PM PST 24
Finished Feb 21 12:52:28 PM PST 24
Peak memory 214908 kb
Host smart-31fd1f04-3e5a-4eb0-8816-f62f0febc8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719427620 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.719427620
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.143849654
Short name T114
Test name
Test status
Simulation time 22515108 ps
CPU time 0.97 seconds
Started Feb 21 12:52:28 PM PST 24
Finished Feb 21 12:52:30 PM PST 24
Peak memory 206540 kb
Host smart-d1babccd-70c4-4ba9-83f3-192e7dde94df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143849654 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.143849654
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.97516162
Short name T488
Test name
Test status
Simulation time 71856301 ps
CPU time 0.93 seconds
Started Feb 21 12:52:29 PM PST 24
Finished Feb 21 12:52:30 PM PST 24
Peak memory 214748 kb
Host smart-69eb579c-d331-4793-97eb-cd2f25e9b1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97516162 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.97516162
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2908034424
Short name T414
Test name
Test status
Simulation time 521203435 ps
CPU time 5.54 seconds
Started Feb 21 12:52:31 PM PST 24
Finished Feb 21 12:52:38 PM PST 24
Peak memory 215724 kb
Host smart-87a834bb-1d38-4ba2-a4a2-7847e2ed466a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908034424 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2908034424
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.724469309
Short name T350
Test name
Test status
Simulation time 62369883586 ps
CPU time 1399 seconds
Started Feb 21 12:52:29 PM PST 24
Finished Feb 21 01:15:49 PM PST 24
Peak memory 221748 kb
Host smart-3a83248a-cb48-4438-97c2-e86d9ff238ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724469309 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.724469309
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2038663717
Short name T622
Test name
Test status
Simulation time 36076710 ps
CPU time 1.07 seconds
Started Feb 21 12:53:55 PM PST 24
Finished Feb 21 12:53:56 PM PST 24
Peak memory 215112 kb
Host smart-f325b305-0471-4ed9-94e5-eb3dfe65efc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038663717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2038663717
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2070968206
Short name T30
Test name
Test status
Simulation time 31663172 ps
CPU time 0.93 seconds
Started Feb 21 12:54:02 PM PST 24
Finished Feb 21 12:54:03 PM PST 24
Peak memory 206332 kb
Host smart-066b3e50-ddf0-4f3c-9321-b8628c1042d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070968206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2070968206
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2590037255
Short name T627
Test name
Test status
Simulation time 132763734 ps
CPU time 1.05 seconds
Started Feb 21 12:54:06 PM PST 24
Finished Feb 21 12:54:08 PM PST 24
Peak memory 215940 kb
Host smart-b913ec42-3500-492d-9e3a-573c2bac7f50
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590037255 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2590037255
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1316755578
Short name T149
Test name
Test status
Simulation time 58113811 ps
CPU time 0.96 seconds
Started Feb 21 12:53:57 PM PST 24
Finished Feb 21 12:53:58 PM PST 24
Peak memory 218628 kb
Host smart-a8115acf-1081-44a3-af00-982d5d9b5736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316755578 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1316755578
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3509406231
Short name T434
Test name
Test status
Simulation time 89913579 ps
CPU time 1.27 seconds
Started Feb 21 12:53:47 PM PST 24
Finished Feb 21 12:53:49 PM PST 24
Peak memory 217692 kb
Host smart-cfc51108-fd2b-4b20-b822-768d234ba82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509406231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3509406231
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3447290292
Short name T457
Test name
Test status
Simulation time 28688306 ps
CPU time 0.87 seconds
Started Feb 21 12:54:06 PM PST 24
Finished Feb 21 12:54:07 PM PST 24
Peak memory 215292 kb
Host smart-279e29c2-3a79-4203-852e-2ce99c3d42d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447290292 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3447290292
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1296401056
Short name T691
Test name
Test status
Simulation time 18543017 ps
CPU time 0.97 seconds
Started Feb 21 12:53:49 PM PST 24
Finished Feb 21 12:53:50 PM PST 24
Peak memory 214732 kb
Host smart-d3b85701-7115-4323-86a5-36149a6b9b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296401056 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1296401056
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2752230563
Short name T328
Test name
Test status
Simulation time 217461019 ps
CPU time 4.28 seconds
Started Feb 21 12:53:48 PM PST 24
Finished Feb 21 12:53:53 PM PST 24
Peak memory 215868 kb
Host smart-d41f77aa-85da-4a2c-8765-0b6888731e91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752230563 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2752230563
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.208155698
Short name T606
Test name
Test status
Simulation time 319106015501 ps
CPU time 1956.66 seconds
Started Feb 21 12:54:02 PM PST 24
Finished Feb 21 01:26:39 PM PST 24
Peak memory 224628 kb
Host smart-0aa0b82e-fce6-4da4-a1cd-7a5ae6a5abea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208155698 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.208155698
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert_test.4208597425
Short name T31
Test name
Test status
Simulation time 42265865 ps
CPU time 0.84 seconds
Started Feb 21 12:54:07 PM PST 24
Finished Feb 21 12:54:09 PM PST 24
Peak memory 205608 kb
Host smart-521883fe-5efe-46f7-a516-3a0169b7c1aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208597425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.4208597425
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3109153182
Short name T535
Test name
Test status
Simulation time 25767291 ps
CPU time 0.8 seconds
Started Feb 21 12:54:10 PM PST 24
Finished Feb 21 12:54:11 PM PST 24
Peak memory 214352 kb
Host smart-7636c274-f7d4-4532-b9e0-6dedb66634f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109153182 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3109153182
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1647332316
Short name T505
Test name
Test status
Simulation time 33149104 ps
CPU time 1.12 seconds
Started Feb 21 12:54:07 PM PST 24
Finished Feb 21 12:54:09 PM PST 24
Peak memory 215652 kb
Host smart-531d54a2-7a45-4a31-bab7-1a9ca9316334
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647332316 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1647332316
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.1540389109
Short name T58
Test name
Test status
Simulation time 24800471 ps
CPU time 1.26 seconds
Started Feb 21 12:54:10 PM PST 24
Finished Feb 21 12:54:11 PM PST 24
Peak memory 218752 kb
Host smart-7e68dd58-aa4b-4d51-a3ff-a8f895a02c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540389109 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1540389109
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.510017537
Short name T327
Test name
Test status
Simulation time 48285661 ps
CPU time 1.46 seconds
Started Feb 21 12:53:59 PM PST 24
Finished Feb 21 12:54:01 PM PST 24
Peak memory 217372 kb
Host smart-b883e5dc-01f5-4a55-9fb2-3b644cb72183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510017537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.510017537
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.141817981
Short name T117
Test name
Test status
Simulation time 26637692 ps
CPU time 0.82 seconds
Started Feb 21 12:54:06 PM PST 24
Finished Feb 21 12:54:07 PM PST 24
Peak memory 215256 kb
Host smart-b31604d5-2405-4752-b96e-6d447295374d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141817981 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.141817981
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3354808905
Short name T335
Test name
Test status
Simulation time 16704328 ps
CPU time 0.94 seconds
Started Feb 21 12:53:57 PM PST 24
Finished Feb 21 12:53:58 PM PST 24
Peak memory 214744 kb
Host smart-de0a90a5-3ba7-43b6-a828-0eeefc3689d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354808905 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3354808905
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.2273240194
Short name T385
Test name
Test status
Simulation time 608745904 ps
CPU time 3.33 seconds
Started Feb 21 12:53:56 PM PST 24
Finished Feb 21 12:54:00 PM PST 24
Peak memory 216076 kb
Host smart-497535f2-618d-4554-bff8-7b0a4cd9c47e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273240194 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2273240194
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2715121150
Short name T177
Test name
Test status
Simulation time 429766691467 ps
CPU time 2220.38 seconds
Started Feb 21 12:53:59 PM PST 24
Finished Feb 21 01:31:00 PM PST 24
Peak memory 228680 kb
Host smart-20735153-70aa-4b52-b213-641b0d8f47ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715121150 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2715121150
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1699668896
Short name T762
Test name
Test status
Simulation time 26960301 ps
CPU time 1.2 seconds
Started Feb 21 12:54:07 PM PST 24
Finished Feb 21 12:54:09 PM PST 24
Peak memory 215032 kb
Host smart-0220359b-9714-43e3-9068-167f43db26f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699668896 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1699668896
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2426437432
Short name T840
Test name
Test status
Simulation time 15830335 ps
CPU time 0.9 seconds
Started Feb 21 12:53:59 PM PST 24
Finished Feb 21 12:54:01 PM PST 24
Peak memory 205792 kb
Host smart-91b0d64c-d468-4408-963e-fee794066aa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426437432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2426437432
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.891582935
Short name T553
Test name
Test status
Simulation time 71940210 ps
CPU time 0.77 seconds
Started Feb 21 12:54:06 PM PST 24
Finished Feb 21 12:54:08 PM PST 24
Peak memory 214836 kb
Host smart-2c102b07-6fd0-449f-bd08-c8e738c53836
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891582935 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.891582935
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1010142533
Short name T156
Test name
Test status
Simulation time 29702506 ps
CPU time 1.08 seconds
Started Feb 21 12:54:07 PM PST 24
Finished Feb 21 12:54:09 PM PST 24
Peak memory 215384 kb
Host smart-814a3be0-3947-4b9c-9659-310325b7781a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010142533 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1010142533
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.957184943
Short name T60
Test name
Test status
Simulation time 58973165 ps
CPU time 0.97 seconds
Started Feb 21 12:53:55 PM PST 24
Finished Feb 21 12:53:56 PM PST 24
Peak memory 219504 kb
Host smart-3bca91f1-ee43-41c9-88eb-d2ea6b3e3efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957184943 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.957184943
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.553298713
Short name T573
Test name
Test status
Simulation time 34853425 ps
CPU time 1.08 seconds
Started Feb 21 12:54:07 PM PST 24
Finished Feb 21 12:54:09 PM PST 24
Peak memory 218344 kb
Host smart-31ca99a5-b57e-4168-9803-7847b23116f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553298713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.553298713
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.333359145
Short name T675
Test name
Test status
Simulation time 33485278 ps
CPU time 0.88 seconds
Started Feb 21 12:53:57 PM PST 24
Finished Feb 21 12:53:58 PM PST 24
Peak memory 215072 kb
Host smart-90edbce3-58c5-4919-8b21-24577d51901f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333359145 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.333359145
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3185152812
Short name T464
Test name
Test status
Simulation time 27525138 ps
CPU time 0.92 seconds
Started Feb 21 12:53:57 PM PST 24
Finished Feb 21 12:53:58 PM PST 24
Peak memory 214708 kb
Host smart-ea9daf00-5a1d-41f1-8a9f-726c6ea4a75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185152812 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3185152812
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2228815965
Short name T571
Test name
Test status
Simulation time 2676651372 ps
CPU time 5.07 seconds
Started Feb 21 12:53:58 PM PST 24
Finished Feb 21 12:54:03 PM PST 24
Peak memory 216056 kb
Host smart-1d9abffd-1a7f-4f9d-9227-2d5010184e9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228815965 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2228815965
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3116574350
Short name T174
Test name
Test status
Simulation time 187560954089 ps
CPU time 1195.42 seconds
Started Feb 21 12:53:59 PM PST 24
Finished Feb 21 01:13:55 PM PST 24
Peak memory 221788 kb
Host smart-9369bba3-1596-4268-8159-df59b9d32af2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116574350 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3116574350
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2177784544
Short name T269
Test name
Test status
Simulation time 46032305 ps
CPU time 1.13 seconds
Started Feb 21 12:54:07 PM PST 24
Finished Feb 21 12:54:09 PM PST 24
Peak memory 215036 kb
Host smart-6db51ef3-5835-4b51-918a-37eec389ae6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177784544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2177784544
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.914112158
Short name T511
Test name
Test status
Simulation time 71294526 ps
CPU time 1.17 seconds
Started Feb 21 12:54:06 PM PST 24
Finished Feb 21 12:54:07 PM PST 24
Peak memory 205644 kb
Host smart-7608277c-722f-43c1-aae7-f14af18b03d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914112158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.914112158
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2368004753
Short name T520
Test name
Test status
Simulation time 35941081 ps
CPU time 0.85 seconds
Started Feb 21 12:53:55 PM PST 24
Finished Feb 21 12:53:56 PM PST 24
Peak memory 215156 kb
Host smart-0bf00549-0c1c-47f8-8e37-fb90d0d49402
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368004753 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2368004753
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1207070939
Short name T517
Test name
Test status
Simulation time 32325316 ps
CPU time 1.2 seconds
Started Feb 21 12:54:09 PM PST 24
Finished Feb 21 12:54:11 PM PST 24
Peak memory 216032 kb
Host smart-9cd3cb25-d8d9-4249-a36e-5e8e562a7a14
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207070939 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1207070939
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1868310833
Short name T755
Test name
Test status
Simulation time 31059348 ps
CPU time 1.06 seconds
Started Feb 21 12:53:59 PM PST 24
Finished Feb 21 12:54:00 PM PST 24
Peak memory 218808 kb
Host smart-5b2f05d2-0645-4ccc-b303-807bbb1d44be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868310833 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1868310833
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2076604741
Short name T789
Test name
Test status
Simulation time 32286346 ps
CPU time 1.31 seconds
Started Feb 21 12:54:10 PM PST 24
Finished Feb 21 12:54:12 PM PST 24
Peak memory 217236 kb
Host smart-9eb69bc6-83ec-4206-ba13-466a6be0b0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076604741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2076604741
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1816431623
Short name T128
Test name
Test status
Simulation time 20198821 ps
CPU time 1.03 seconds
Started Feb 21 12:54:07 PM PST 24
Finished Feb 21 12:54:08 PM PST 24
Peak memory 215336 kb
Host smart-c7a0bfa4-93b2-4c14-a535-cfc8e62a8eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816431623 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1816431623
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2533149758
Short name T306
Test name
Test status
Simulation time 16414391 ps
CPU time 1.04 seconds
Started Feb 21 12:54:10 PM PST 24
Finished Feb 21 12:54:11 PM PST 24
Peak memory 214712 kb
Host smart-5b68b58c-bfbb-4039-9040-43a40ccfbf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533149758 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2533149758
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1955736072
Short name T827
Test name
Test status
Simulation time 533492665 ps
CPU time 2.29 seconds
Started Feb 21 12:53:55 PM PST 24
Finished Feb 21 12:53:57 PM PST 24
Peak memory 214732 kb
Host smart-8e8bdc2c-bac8-4edd-abbb-387a00d30689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955736072 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1955736072
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3305332812
Short name T408
Test name
Test status
Simulation time 216499243635 ps
CPU time 2855.55 seconds
Started Feb 21 12:54:06 PM PST 24
Finished Feb 21 01:41:42 PM PST 24
Peak memory 233204 kb
Host smart-b4da5b16-1efb-40e2-92b2-f16c1620339e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305332812 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3305332812
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.1319219041
Short name T724
Test name
Test status
Simulation time 52712238 ps
CPU time 1.25 seconds
Started Feb 21 12:54:05 PM PST 24
Finished Feb 21 12:54:06 PM PST 24
Peak memory 215144 kb
Host smart-d61c34ba-b68c-460e-9cd4-9c5a63d0ebe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319219041 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1319219041
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.748808221
Short name T448
Test name
Test status
Simulation time 14086885 ps
CPU time 0.84 seconds
Started Feb 21 12:54:01 PM PST 24
Finished Feb 21 12:54:02 PM PST 24
Peak memory 205416 kb
Host smart-0f014836-6a80-47c0-846a-9f390cae2e38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748808221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.748808221
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.4000395392
Short name T147
Test name
Test status
Simulation time 10420456 ps
CPU time 0.84 seconds
Started Feb 21 12:54:05 PM PST 24
Finished Feb 21 12:54:06 PM PST 24
Peak memory 214992 kb
Host smart-ba196be9-4752-432d-9695-b63c1f27e87a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000395392 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.4000395392
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3575176245
Short name T64
Test name
Test status
Simulation time 82730837 ps
CPU time 1.37 seconds
Started Feb 21 12:54:05 PM PST 24
Finished Feb 21 12:54:06 PM PST 24
Peak memory 215944 kb
Host smart-eb4957a1-540c-4933-906f-7ea07dd5b607
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575176245 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3575176245
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.261046224
Short name T748
Test name
Test status
Simulation time 38877334 ps
CPU time 0.79 seconds
Started Feb 21 12:54:05 PM PST 24
Finished Feb 21 12:54:06 PM PST 24
Peak memory 217020 kb
Host smart-0e52a437-7a3e-478b-904d-fd2d4f98242e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261046224 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.261046224
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3469265717
Short name T449
Test name
Test status
Simulation time 43140447 ps
CPU time 1.49 seconds
Started Feb 21 12:54:10 PM PST 24
Finished Feb 21 12:54:12 PM PST 24
Peak memory 216308 kb
Host smart-57069ad5-ba26-43eb-b6cb-d4da31cd61db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469265717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3469265717
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2821264219
Short name T681
Test name
Test status
Simulation time 25833972 ps
CPU time 1.05 seconds
Started Feb 21 12:54:01 PM PST 24
Finished Feb 21 12:54:03 PM PST 24
Peak memory 222480 kb
Host smart-efee0e1f-fef3-4d87-9690-01563b8a7ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821264219 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2821264219
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.810714145
Short name T603
Test name
Test status
Simulation time 15658451 ps
CPU time 0.93 seconds
Started Feb 21 12:53:55 PM PST 24
Finished Feb 21 12:53:56 PM PST 24
Peak memory 214780 kb
Host smart-feb48203-4f63-421b-bb44-7c5a229d19aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810714145 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.810714145
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3171228909
Short name T686
Test name
Test status
Simulation time 228888661 ps
CPU time 4.82 seconds
Started Feb 21 12:53:56 PM PST 24
Finished Feb 21 12:54:01 PM PST 24
Peak memory 214820 kb
Host smart-3aa4118f-9e87-4a06-b5d7-b502f0285f26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171228909 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3171228909
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1631927233
Short name T182
Test name
Test status
Simulation time 122972645255 ps
CPU time 716.88 seconds
Started Feb 21 12:54:01 PM PST 24
Finished Feb 21 01:05:59 PM PST 24
Peak memory 218860 kb
Host smart-f5749a5d-65fa-4386-a205-60332d76c38f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631927233 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1631927233
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1531661031
Short name T140
Test name
Test status
Simulation time 110138414 ps
CPU time 1.42 seconds
Started Feb 21 12:54:06 PM PST 24
Finished Feb 21 12:54:08 PM PST 24
Peak memory 215124 kb
Host smart-97b7dbfc-9c2a-4ae2-b11e-59454e1eca35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531661031 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1531661031
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1660417930
Short name T384
Test name
Test status
Simulation time 22180643 ps
CPU time 1.01 seconds
Started Feb 21 12:54:08 PM PST 24
Finished Feb 21 12:54:10 PM PST 24
Peak memory 205468 kb
Host smart-d417a957-b51f-47c2-8933-82763dd0d812
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660417930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1660417930
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1621450495
Short name T823
Test name
Test status
Simulation time 14212576 ps
CPU time 0.91 seconds
Started Feb 21 12:54:10 PM PST 24
Finished Feb 21 12:54:11 PM PST 24
Peak memory 215040 kb
Host smart-e677e3b4-4f30-4232-a628-040c05b067bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621450495 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1621450495
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.4079837224
Short name T760
Test name
Test status
Simulation time 47450036 ps
CPU time 1.02 seconds
Started Feb 21 12:54:16 PM PST 24
Finished Feb 21 12:54:17 PM PST 24
Peak memory 215764 kb
Host smart-3345995d-65a3-4eb8-bb9e-c43ad8ded34c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079837224 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.4079837224
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3107585878
Short name T59
Test name
Test status
Simulation time 38486654 ps
CPU time 1.13 seconds
Started Feb 21 12:54:10 PM PST 24
Finished Feb 21 12:54:12 PM PST 24
Peak memory 219476 kb
Host smart-5f67dadb-058d-440c-bbb7-48b1534d52cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107585878 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3107585878
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.538925638
Short name T456
Test name
Test status
Simulation time 64584259 ps
CPU time 1.28 seconds
Started Feb 21 12:54:05 PM PST 24
Finished Feb 21 12:54:06 PM PST 24
Peak memory 217444 kb
Host smart-3cee99b9-dc1f-4bfc-ac8d-8690e4d30478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538925638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.538925638
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1016473158
Short name T127
Test name
Test status
Simulation time 20290990 ps
CPU time 1.01 seconds
Started Feb 21 12:54:10 PM PST 24
Finished Feb 21 12:54:12 PM PST 24
Peak memory 215232 kb
Host smart-16c04853-ea92-4e0b-9cde-75ba85376bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016473158 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1016473158
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1173420355
Short name T239
Test name
Test status
Simulation time 15006588 ps
CPU time 0.98 seconds
Started Feb 21 12:54:01 PM PST 24
Finished Feb 21 12:54:02 PM PST 24
Peak memory 206592 kb
Host smart-c40b73df-2ac9-4a8f-a979-c85844bd9e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173420355 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1173420355
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2077406052
Short name T661
Test name
Test status
Simulation time 121515974 ps
CPU time 1.32 seconds
Started Feb 21 12:54:01 PM PST 24
Finished Feb 21 12:54:03 PM PST 24
Peak memory 215952 kb
Host smart-8b1044d3-7c25-4432-bb02-02aed407f59e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077406052 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2077406052
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2924086988
Short name T184
Test name
Test status
Simulation time 18577219419 ps
CPU time 428.92 seconds
Started Feb 21 12:53:59 PM PST 24
Finished Feb 21 01:01:09 PM PST 24
Peak memory 223096 kb
Host smart-653b1d76-0826-4d84-8e5c-901f5a9c8e24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924086988 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2924086988
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3739211181
Short name T793
Test name
Test status
Simulation time 50534787 ps
CPU time 1.21 seconds
Started Feb 21 12:54:19 PM PST 24
Finished Feb 21 12:54:20 PM PST 24
Peak memory 215128 kb
Host smart-9f9e2c90-8b9a-4c4a-b30a-832be44708cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739211181 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3739211181
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.577145759
Short name T817
Test name
Test status
Simulation time 43875713 ps
CPU time 0.8 seconds
Started Feb 21 12:54:10 PM PST 24
Finished Feb 21 12:54:12 PM PST 24
Peak memory 205108 kb
Host smart-4ec0c26a-9a17-4fe7-9a9e-8f5ac0165f45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577145759 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.577145759
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2818739262
Short name T97
Test name
Test status
Simulation time 34573803 ps
CPU time 0.84 seconds
Started Feb 21 12:54:24 PM PST 24
Finished Feb 21 12:54:26 PM PST 24
Peak memory 215140 kb
Host smart-a1c775e7-97a3-430d-b356-518c2f1add72
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818739262 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2818739262
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_err.4087214491
Short name T818
Test name
Test status
Simulation time 26722660 ps
CPU time 0.95 seconds
Started Feb 21 12:54:15 PM PST 24
Finished Feb 21 12:54:16 PM PST 24
Peak memory 217700 kb
Host smart-92dba1f9-a21c-4bd3-bbeb-408616702a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087214491 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.4087214491
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1369465496
Short name T769
Test name
Test status
Simulation time 53176415 ps
CPU time 1.32 seconds
Started Feb 21 12:54:13 PM PST 24
Finished Feb 21 12:54:15 PM PST 24
Peak memory 217400 kb
Host smart-db82d532-e065-4e43-88b8-cebf501e4b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369465496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1369465496
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1526705859
Short name T613
Test name
Test status
Simulation time 26380289 ps
CPU time 1.18 seconds
Started Feb 21 12:54:14 PM PST 24
Finished Feb 21 12:54:16 PM PST 24
Peak memory 223544 kb
Host smart-4f1d4cb2-fac1-4d71-b435-410b394042ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526705859 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1526705859
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3416471821
Short name T313
Test name
Test status
Simulation time 43520113 ps
CPU time 0.85 seconds
Started Feb 21 12:54:18 PM PST 24
Finished Feb 21 12:54:19 PM PST 24
Peak memory 214640 kb
Host smart-e480bd65-e70b-450c-bb0d-226fbe00dc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416471821 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3416471821
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.4074275978
Short name T787
Test name
Test status
Simulation time 242143783 ps
CPU time 4.36 seconds
Started Feb 21 12:54:17 PM PST 24
Finished Feb 21 12:54:21 PM PST 24
Peak memory 215980 kb
Host smart-108fed11-af21-4d84-a530-ad5b0fac6990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074275978 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.4074275978
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3396198682
Short name T643
Test name
Test status
Simulation time 707782747483 ps
CPU time 1753.41 seconds
Started Feb 21 12:54:12 PM PST 24
Finished Feb 21 01:23:26 PM PST 24
Peak memory 223100 kb
Host smart-b958789a-d994-4d05-afdc-ca12d8accf3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396198682 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3396198682
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1340040913
Short name T139
Test name
Test status
Simulation time 33343412 ps
CPU time 1.23 seconds
Started Feb 21 12:54:37 PM PST 24
Finished Feb 21 12:54:39 PM PST 24
Peak memory 215052 kb
Host smart-936b506e-e23e-4368-92df-d91428884323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340040913 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1340040913
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1429204006
Short name T783
Test name
Test status
Simulation time 231135667 ps
CPU time 0.99 seconds
Started Feb 21 12:54:18 PM PST 24
Finished Feb 21 12:54:20 PM PST 24
Peak memory 205432 kb
Host smart-f666eafc-1017-4a34-ace8-b9b3bab03d8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429204006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1429204006
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3040066414
Short name T87
Test name
Test status
Simulation time 43772473 ps
CPU time 0.87 seconds
Started Feb 21 12:54:25 PM PST 24
Finished Feb 21 12:54:27 PM PST 24
Peak memory 215136 kb
Host smart-79e6a158-b03c-4e26-b367-f58dccee8a49
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040066414 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3040066414
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.4126625705
Short name T159
Test name
Test status
Simulation time 146291935 ps
CPU time 1.15 seconds
Started Feb 21 12:54:19 PM PST 24
Finished Feb 21 12:54:20 PM PST 24
Peak memory 215708 kb
Host smart-432f047a-7b48-4f8c-a86b-929c81c173b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126625705 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.4126625705
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.4181310519
Short name T145
Test name
Test status
Simulation time 33094702 ps
CPU time 0.87 seconds
Started Feb 21 12:54:37 PM PST 24
Finished Feb 21 12:54:39 PM PST 24
Peak memory 217200 kb
Host smart-1e7f4000-45a0-4c01-92b0-1b3ea56700f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181310519 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.4181310519
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.275332378
Short name T764
Test name
Test status
Simulation time 94920211 ps
CPU time 1.15 seconds
Started Feb 21 12:54:15 PM PST 24
Finished Feb 21 12:54:17 PM PST 24
Peak memory 216976 kb
Host smart-620584eb-9127-4d74-b4c9-de6fb45d7fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275332378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.275332378
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2807687854
Short name T348
Test name
Test status
Simulation time 39041688 ps
CPU time 0.95 seconds
Started Feb 21 12:54:19 PM PST 24
Finished Feb 21 12:54:21 PM PST 24
Peak memory 222400 kb
Host smart-57c82e4a-d5cf-4395-b0b5-1356d8e1a7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807687854 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2807687854
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.27000122
Short name T371
Test name
Test status
Simulation time 51350554 ps
CPU time 0.93 seconds
Started Feb 21 12:54:26 PM PST 24
Finished Feb 21 12:54:28 PM PST 24
Peak memory 214716 kb
Host smart-22dd67a9-c9b9-4554-bb7a-517ec93a1e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27000122 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.27000122
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.48475625
Short name T190
Test name
Test status
Simulation time 85775964 ps
CPU time 2.16 seconds
Started Feb 21 12:54:37 PM PST 24
Finished Feb 21 12:54:41 PM PST 24
Peak memory 214752 kb
Host smart-b6e2d91e-5b3f-4b1d-87f2-d1c7b9139389
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48475625 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.48475625
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1950146738
Short name T366
Test name
Test status
Simulation time 108784003140 ps
CPU time 601.66 seconds
Started Feb 21 12:54:15 PM PST 24
Finished Feb 21 01:04:17 PM PST 24
Peak memory 219312 kb
Host smart-65f2d322-d002-4999-bf99-03260e1c108b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950146738 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1950146738
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2086393847
Short name T716
Test name
Test status
Simulation time 64186216 ps
CPU time 1.11 seconds
Started Feb 21 12:54:35 PM PST 24
Finished Feb 21 12:54:38 PM PST 24
Peak memory 215076 kb
Host smart-485fef51-3d8d-4129-aad9-bf7fc025076b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086393847 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2086393847
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3081471023
Short name T424
Test name
Test status
Simulation time 15086378 ps
CPU time 0.9 seconds
Started Feb 21 12:54:54 PM PST 24
Finished Feb 21 12:54:56 PM PST 24
Peak memory 206300 kb
Host smart-8e7db7e6-6f93-4196-b4f5-005404638f6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081471023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3081471023
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3579971274
Short name T532
Test name
Test status
Simulation time 58113718 ps
CPU time 0.98 seconds
Started Feb 21 12:54:30 PM PST 24
Finished Feb 21 12:54:32 PM PST 24
Peak memory 215724 kb
Host smart-91dc0fa3-196c-4ec6-a79e-f315cac84a2a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579971274 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3579971274
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.1549281918
Short name T50
Test name
Test status
Simulation time 49069010 ps
CPU time 0.89 seconds
Started Feb 21 12:54:32 PM PST 24
Finished Feb 21 12:54:33 PM PST 24
Peak memory 217204 kb
Host smart-30ed0960-eec2-4527-8d0f-be81d95a3f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549281918 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1549281918
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2614633547
Short name T773
Test name
Test status
Simulation time 284166572 ps
CPU time 1.16 seconds
Started Feb 21 12:54:14 PM PST 24
Finished Feb 21 12:54:15 PM PST 24
Peak memory 215940 kb
Host smart-4b04b1dc-5089-4683-81ae-b86cbb78080d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614633547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2614633547
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3728109975
Short name T410
Test name
Test status
Simulation time 21229144 ps
CPU time 1.05 seconds
Started Feb 21 12:54:18 PM PST 24
Finished Feb 21 12:54:19 PM PST 24
Peak memory 214944 kb
Host smart-070036fe-68fb-48fc-a2d0-828c0b722b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728109975 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3728109975
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1354469595
Short name T450
Test name
Test status
Simulation time 50369031 ps
CPU time 0.88 seconds
Started Feb 21 12:54:31 PM PST 24
Finished Feb 21 12:54:32 PM PST 24
Peak memory 214756 kb
Host smart-fd7ea5bd-4652-4c45-92c6-c1a0c148ede2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354469595 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1354469595
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.872900573
Short name T717
Test name
Test status
Simulation time 28426386 ps
CPU time 0.99 seconds
Started Feb 21 12:54:19 PM PST 24
Finished Feb 21 12:54:21 PM PST 24
Peak memory 214740 kb
Host smart-5c5a9b52-563f-46e2-8b9e-52b924c60bbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872900573 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.872900573
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1025068132
Short name T657
Test name
Test status
Simulation time 809237552596 ps
CPU time 1363.03 seconds
Started Feb 21 12:54:32 PM PST 24
Finished Feb 21 01:17:16 PM PST 24
Peak memory 220216 kb
Host smart-e01021cf-62ac-4dbc-abbd-58a4c66207bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025068132 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1025068132
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1547533657
Short name T659
Test name
Test status
Simulation time 47980069 ps
CPU time 1.17 seconds
Started Feb 21 12:54:41 PM PST 24
Finished Feb 21 12:54:43 PM PST 24
Peak memory 215172 kb
Host smart-de04407a-a10e-4e6c-8bf2-f9f5f2543713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547533657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1547533657
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3594126137
Short name T351
Test name
Test status
Simulation time 14119708 ps
CPU time 0.93 seconds
Started Feb 21 12:54:38 PM PST 24
Finished Feb 21 12:54:41 PM PST 24
Peak memory 205932 kb
Host smart-0b3ae303-1fe4-4347-aada-aeade334144a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594126137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3594126137
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.452785963
Short name T470
Test name
Test status
Simulation time 36538504 ps
CPU time 0.86 seconds
Started Feb 21 12:54:36 PM PST 24
Finished Feb 21 12:54:38 PM PST 24
Peak memory 214804 kb
Host smart-c0db7568-828d-4a5e-99a4-cc2f9548f48e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452785963 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.452785963
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_err.1074203603
Short name T23
Test name
Test status
Simulation time 22435442 ps
CPU time 0.97 seconds
Started Feb 21 12:54:40 PM PST 24
Finished Feb 21 12:54:42 PM PST 24
Peak memory 217680 kb
Host smart-50659ada-48dd-431f-b357-6726b9c1ffae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074203603 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1074203603
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.805877155
Short name T452
Test name
Test status
Simulation time 57866796 ps
CPU time 1.15 seconds
Started Feb 21 12:54:37 PM PST 24
Finished Feb 21 12:54:40 PM PST 24
Peak memory 216148 kb
Host smart-8503f6c7-7eaa-421d-a418-9e6a33244407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805877155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.805877155
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1538005926
Short name T305
Test name
Test status
Simulation time 25113497 ps
CPU time 0.91 seconds
Started Feb 21 12:54:36 PM PST 24
Finished Feb 21 12:54:39 PM PST 24
Peak memory 215064 kb
Host smart-b2bd9335-d90f-4351-ae11-31e3747cfbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538005926 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1538005926
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3670689588
Short name T701
Test name
Test status
Simulation time 63718005 ps
CPU time 0.88 seconds
Started Feb 21 12:54:40 PM PST 24
Finished Feb 21 12:54:42 PM PST 24
Peak memory 214756 kb
Host smart-ec6ca2c9-0ca6-40ff-bcd5-602bd8ae8aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670689588 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3670689588
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.569740085
Short name T201
Test name
Test status
Simulation time 182188849 ps
CPU time 3.52 seconds
Started Feb 21 12:54:37 PM PST 24
Finished Feb 21 12:54:43 PM PST 24
Peak memory 214724 kb
Host smart-866b0d21-dad9-4192-9031-43c5c9ec4536
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569740085 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.569740085
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1870243453
Short name T186
Test name
Test status
Simulation time 254793715699 ps
CPU time 2606.85 seconds
Started Feb 21 12:54:38 PM PST 24
Finished Feb 21 01:38:07 PM PST 24
Peak memory 227988 kb
Host smart-e3e0386f-e140-48ee-a65a-a8a3dce78f90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870243453 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1870243453
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.559794898
Short name T89
Test name
Test status
Simulation time 63041584 ps
CPU time 1.19 seconds
Started Feb 21 12:52:31 PM PST 24
Finished Feb 21 12:52:33 PM PST 24
Peak memory 215228 kb
Host smart-2cfe8524-7767-4b63-94fe-3a8538f7abd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559794898 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.559794898
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2354377285
Short name T694
Test name
Test status
Simulation time 25230449 ps
CPU time 0.9 seconds
Started Feb 21 12:52:29 PM PST 24
Finished Feb 21 12:52:31 PM PST 24
Peak memory 205468 kb
Host smart-56cd758c-0fc3-46c2-a302-bb835bf080cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354377285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2354377285
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3198814252
Short name T1
Test name
Test status
Simulation time 13985705 ps
CPU time 1.21 seconds
Started Feb 21 12:52:39 PM PST 24
Finished Feb 21 12:52:41 PM PST 24
Peak memory 215460 kb
Host smart-ff309f8c-93fb-427f-b6d9-df1ec01dff07
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198814252 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3198814252
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1343166569
Short name T79
Test name
Test status
Simulation time 49798383 ps
CPU time 1.38 seconds
Started Feb 21 12:52:36 PM PST 24
Finished Feb 21 12:52:37 PM PST 24
Peak memory 215892 kb
Host smart-76d5f15e-f797-44b4-b98e-0640e7635edf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343166569 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1343166569
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.135058138
Short name T100
Test name
Test status
Simulation time 31926515 ps
CPU time 0.91 seconds
Started Feb 21 12:52:32 PM PST 24
Finished Feb 21 12:52:34 PM PST 24
Peak memory 222280 kb
Host smart-c669c465-dbb4-4706-94c6-da5b2ee3a67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135058138 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.135058138
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.84336592
Short name T446
Test name
Test status
Simulation time 39705051 ps
CPU time 1.58 seconds
Started Feb 21 12:52:31 PM PST 24
Finished Feb 21 12:52:33 PM PST 24
Peak memory 217260 kb
Host smart-84cc379c-d56a-49ea-8fae-883538115fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84336592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.84336592
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2086913983
Short name T832
Test name
Test status
Simulation time 20824464 ps
CPU time 1.01 seconds
Started Feb 21 12:52:28 PM PST 24
Finished Feb 21 12:52:30 PM PST 24
Peak memory 214872 kb
Host smart-70b674bd-6173-41f8-9a06-f5b81c9bccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086913983 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2086913983
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.528288988
Short name T263
Test name
Test status
Simulation time 80255570 ps
CPU time 0.82 seconds
Started Feb 21 12:52:35 PM PST 24
Finished Feb 21 12:52:36 PM PST 24
Peak memory 206340 kb
Host smart-36b79b0e-5efb-4758-adfa-041364ac137a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528288988 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.528288988
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3067912862
Short name T491
Test name
Test status
Simulation time 18283861 ps
CPU time 0.95 seconds
Started Feb 21 12:52:33 PM PST 24
Finished Feb 21 12:52:35 PM PST 24
Peak memory 214752 kb
Host smart-928365bd-4303-40dd-91fd-c12702278bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067912862 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3067912862
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3599649896
Short name T293
Test name
Test status
Simulation time 323301737 ps
CPU time 6.35 seconds
Started Feb 21 12:52:28 PM PST 24
Finished Feb 21 12:52:35 PM PST 24
Peak memory 215000 kb
Host smart-dea9243e-e589-4436-97b3-bb24f881527a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599649896 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3599649896
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2287582413
Short name T644
Test name
Test status
Simulation time 93046500447 ps
CPU time 1018.64 seconds
Started Feb 21 12:52:29 PM PST 24
Finished Feb 21 01:09:29 PM PST 24
Peak memory 221264 kb
Host smart-5776327a-c6a4-4024-8805-9f351dfe2e83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287582413 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2287582413
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.3864483422
Short name T146
Test name
Test status
Simulation time 19527693 ps
CPU time 1.03 seconds
Started Feb 21 12:54:15 PM PST 24
Finished Feb 21 12:54:16 PM PST 24
Peak memory 217380 kb
Host smart-82fd9634-8246-4bfe-94a8-326e64db701e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864483422 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3864483422
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1589652336
Short name T317
Test name
Test status
Simulation time 51617986 ps
CPU time 1.56 seconds
Started Feb 21 12:54:21 PM PST 24
Finished Feb 21 12:54:23 PM PST 24
Peak memory 217136 kb
Host smart-70d1596f-f5b0-4ccb-9ad2-8132865ab15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589652336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1589652336
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_genbits.4011066160
Short name T704
Test name
Test status
Simulation time 89127208 ps
CPU time 1.54 seconds
Started Feb 21 12:54:26 PM PST 24
Finished Feb 21 12:54:28 PM PST 24
Peak memory 217484 kb
Host smart-01ecfb0c-c147-4808-b976-27430de0c817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011066160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.4011066160
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.2905772714
Short name T577
Test name
Test status
Simulation time 19104078 ps
CPU time 1.02 seconds
Started Feb 21 12:54:17 PM PST 24
Finished Feb 21 12:54:18 PM PST 24
Peak memory 217148 kb
Host smart-2732d349-83c3-4608-b068-03c67bb9418c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905772714 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2905772714
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1961536539
Short name T43
Test name
Test status
Simulation time 540822710 ps
CPU time 5.42 seconds
Started Feb 21 12:54:18 PM PST 24
Finished Feb 21 12:54:24 PM PST 24
Peak memory 216180 kb
Host smart-00812b4a-d000-4209-a12c-0b3fc71042b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961536539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1961536539
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.438577607
Short name T6
Test name
Test status
Simulation time 18491211 ps
CPU time 0.97 seconds
Started Feb 21 12:54:35 PM PST 24
Finished Feb 21 12:54:37 PM PST 24
Peak memory 217224 kb
Host smart-1a832daa-2880-45e6-8c28-96f368c35e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438577607 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.438577607
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2333284562
Short name T547
Test name
Test status
Simulation time 52947166 ps
CPU time 1.56 seconds
Started Feb 21 12:54:15 PM PST 24
Finished Feb 21 12:54:17 PM PST 24
Peak memory 217400 kb
Host smart-6cf881d0-af58-4ba4-adab-90ddaf95d12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333284562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2333284562
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.2919143925
Short name T71
Test name
Test status
Simulation time 19761721 ps
CPU time 1.11 seconds
Started Feb 21 12:54:26 PM PST 24
Finished Feb 21 12:54:28 PM PST 24
Peak memory 222432 kb
Host smart-bc1513a8-67a6-4ec6-a9e3-32c3845c75df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919143925 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2919143925
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1372645173
Short name T531
Test name
Test status
Simulation time 71656124 ps
CPU time 1.12 seconds
Started Feb 21 12:54:26 PM PST 24
Finished Feb 21 12:54:27 PM PST 24
Peak memory 218472 kb
Host smart-ca294f07-3baf-4e2f-8ef0-6675820cece5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372645173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1372645173
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.1710443087
Short name T422
Test name
Test status
Simulation time 28092458 ps
CPU time 0.82 seconds
Started Feb 21 12:54:18 PM PST 24
Finished Feb 21 12:54:19 PM PST 24
Peak memory 217432 kb
Host smart-629d97f2-ce54-44b5-b4bd-737b17aab1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710443087 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1710443087
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/56.edn_err.1006526848
Short name T73
Test name
Test status
Simulation time 22752349 ps
CPU time 1.13 seconds
Started Feb 21 12:54:17 PM PST 24
Finished Feb 21 12:54:19 PM PST 24
Peak memory 228896 kb
Host smart-025405ed-77d6-4700-877f-1416fa239b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006526848 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1006526848
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.166682645
Short name T664
Test name
Test status
Simulation time 45035340 ps
CPU time 1.12 seconds
Started Feb 21 12:54:26 PM PST 24
Finished Feb 21 12:54:28 PM PST 24
Peak memory 215848 kb
Host smart-beca6032-2d83-475c-b116-7678656d3fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166682645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.166682645
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.1548008279
Short name T346
Test name
Test status
Simulation time 48358683 ps
CPU time 0.9 seconds
Started Feb 21 12:54:23 PM PST 24
Finished Feb 21 12:54:25 PM PST 24
Peak memory 217424 kb
Host smart-3400ae1a-c9da-4548-920d-65e6877865eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548008279 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1548008279
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.810586017
Short name T654
Test name
Test status
Simulation time 37369284 ps
CPU time 1.47 seconds
Started Feb 21 12:54:13 PM PST 24
Finished Feb 21 12:54:15 PM PST 24
Peak memory 217228 kb
Host smart-27d6f056-3445-4907-8eea-6308c92ed098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810586017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.810586017
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.1172885887
Short name T801
Test name
Test status
Simulation time 28447890 ps
CPU time 0.92 seconds
Started Feb 21 12:54:16 PM PST 24
Finished Feb 21 12:54:18 PM PST 24
Peak memory 222260 kb
Host smart-daa10de5-acd6-4485-ae39-13779fbc80fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172885887 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1172885887
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1450372864
Short name T726
Test name
Test status
Simulation time 98140134 ps
CPU time 1.16 seconds
Started Feb 21 12:54:23 PM PST 24
Finished Feb 21 12:54:26 PM PST 24
Peak memory 216192 kb
Host smart-540da9ef-bde6-45e8-abbc-2a2c39acc1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450372864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1450372864
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.3044082991
Short name T15
Test name
Test status
Simulation time 48419432 ps
CPU time 1.1 seconds
Started Feb 21 12:54:12 PM PST 24
Finished Feb 21 12:54:13 PM PST 24
Peak memory 223508 kb
Host smart-54b05508-6a14-4dfe-9f3b-17ba67f9a70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044082991 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3044082991
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2402923687
Short name T526
Test name
Test status
Simulation time 76873891 ps
CPU time 1.66 seconds
Started Feb 21 12:54:17 PM PST 24
Finished Feb 21 12:54:19 PM PST 24
Peak memory 218812 kb
Host smart-21177e7c-dddd-48c0-be36-35003f8acf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402923687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2402923687
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2328750909
Short name T771
Test name
Test status
Simulation time 26193881 ps
CPU time 1.21 seconds
Started Feb 21 12:52:39 PM PST 24
Finished Feb 21 12:52:41 PM PST 24
Peak memory 215128 kb
Host smart-283af25e-b935-4231-9a21-f8e74cc7bfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328750909 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2328750909
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2219872670
Short name T610
Test name
Test status
Simulation time 26377226 ps
CPU time 0.86 seconds
Started Feb 21 12:52:41 PM PST 24
Finished Feb 21 12:52:43 PM PST 24
Peak memory 206324 kb
Host smart-bd3fd309-e755-498f-a8b0-233765854767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219872670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2219872670
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.951996045
Short name T98
Test name
Test status
Simulation time 35068362 ps
CPU time 0.89 seconds
Started Feb 21 12:52:43 PM PST 24
Finished Feb 21 12:52:44 PM PST 24
Peak memory 215140 kb
Host smart-02421032-af28-4e73-ab80-156c5300b31b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951996045 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.951996045
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_err.1927446228
Short name T660
Test name
Test status
Simulation time 29622400 ps
CPU time 1.19 seconds
Started Feb 21 12:52:37 PM PST 24
Finished Feb 21 12:52:38 PM PST 24
Peak memory 218520 kb
Host smart-a1092a82-3d9f-429f-9ed6-6e568a284472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927446228 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1927446228
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.4225043083
Short name T417
Test name
Test status
Simulation time 71651646 ps
CPU time 1.06 seconds
Started Feb 21 12:52:40 PM PST 24
Finished Feb 21 12:52:42 PM PST 24
Peak memory 214760 kb
Host smart-42ad8311-1e09-469a-8485-86355cca2e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225043083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.4225043083
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1502809768
Short name T529
Test name
Test status
Simulation time 22520410 ps
CPU time 1.22 seconds
Started Feb 21 12:52:39 PM PST 24
Finished Feb 21 12:52:41 PM PST 24
Peak memory 222684 kb
Host smart-31d134f8-799b-457f-9160-eeee34a38678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502809768 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1502809768
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.3289635212
Short name T349
Test name
Test status
Simulation time 61954224 ps
CPU time 0.91 seconds
Started Feb 21 12:52:35 PM PST 24
Finished Feb 21 12:52:36 PM PST 24
Peak memory 214724 kb
Host smart-ec4352e0-6623-4338-98b8-d2fd9b03e3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289635212 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3289635212
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3809552810
Short name T302
Test name
Test status
Simulation time 210127995 ps
CPU time 2.44 seconds
Started Feb 21 12:52:39 PM PST 24
Finished Feb 21 12:52:41 PM PST 24
Peak memory 215816 kb
Host smart-40b30756-a53a-467a-80ba-71511dbec35d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809552810 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3809552810
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3207635458
Short name T798
Test name
Test status
Simulation time 29224899686 ps
CPU time 381.94 seconds
Started Feb 21 12:52:45 PM PST 24
Finished Feb 21 12:59:07 PM PST 24
Peak memory 217824 kb
Host smart-c5a63eba-c2d2-496b-9c6f-adbf370184b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207635458 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3207635458
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.181023573
Short name T744
Test name
Test status
Simulation time 21182292 ps
CPU time 0.97 seconds
Started Feb 21 12:54:15 PM PST 24
Finished Feb 21 12:54:16 PM PST 24
Peak memory 217140 kb
Host smart-fef86ea0-5257-40c0-9f4a-3b79227b0eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181023573 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.181023573
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2549266614
Short name T616
Test name
Test status
Simulation time 192139781 ps
CPU time 1.19 seconds
Started Feb 21 12:54:17 PM PST 24
Finished Feb 21 12:54:19 PM PST 24
Peak memory 217332 kb
Host smart-a1c39f1b-2819-4ad9-94ec-af197c3de53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549266614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2549266614
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.2791020039
Short name T354
Test name
Test status
Simulation time 29114705 ps
CPU time 1.4 seconds
Started Feb 21 12:54:16 PM PST 24
Finished Feb 21 12:54:18 PM PST 24
Peak memory 231684 kb
Host smart-32a43fdc-d51d-4734-9584-941398883031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791020039 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2791020039
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.143025343
Short name T719
Test name
Test status
Simulation time 36859657 ps
CPU time 1.27 seconds
Started Feb 21 12:54:26 PM PST 24
Finished Feb 21 12:54:27 PM PST 24
Peak memory 215832 kb
Host smart-b418edcd-f3fb-47d0-bef3-07fd23b3bd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143025343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.143025343
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.480862685
Short name T7
Test name
Test status
Simulation time 35548148 ps
CPU time 0.88 seconds
Started Feb 21 12:54:13 PM PST 24
Finished Feb 21 12:54:15 PM PST 24
Peak memory 216108 kb
Host smart-ede9bc10-4df8-4ba6-b26e-4fecea46cc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480862685 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.480862685
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3894764126
Short name T794
Test name
Test status
Simulation time 91822762 ps
CPU time 1.15 seconds
Started Feb 21 12:54:29 PM PST 24
Finished Feb 21 12:54:31 PM PST 24
Peak memory 218060 kb
Host smart-e4a0f13d-83c0-48d9-9619-62d7a25904e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894764126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3894764126
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.3996869614
Short name T586
Test name
Test status
Simulation time 31446293 ps
CPU time 0.83 seconds
Started Feb 21 12:54:24 PM PST 24
Finished Feb 21 12:54:26 PM PST 24
Peak memory 217240 kb
Host smart-790b6957-d900-40c8-9b51-09b9575e0769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996869614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3996869614
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.485036774
Short name T278
Test name
Test status
Simulation time 68467349 ps
CPU time 1.34 seconds
Started Feb 21 12:54:31 PM PST 24
Finished Feb 21 12:54:33 PM PST 24
Peak memory 215996 kb
Host smart-8612c7e6-21db-46b6-9be6-e272677205a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485036774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.485036774
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.3757965697
Short name T72
Test name
Test status
Simulation time 25199254 ps
CPU time 1.09 seconds
Started Feb 21 12:54:18 PM PST 24
Finished Feb 21 12:54:19 PM PST 24
Peak memory 229276 kb
Host smart-2399e7d6-343b-4861-befe-9bc802f9bb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757965697 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3757965697
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.934153506
Short name T277
Test name
Test status
Simulation time 68287908 ps
CPU time 2.46 seconds
Started Feb 21 12:54:17 PM PST 24
Finished Feb 21 12:54:20 PM PST 24
Peak memory 217464 kb
Host smart-cd35d528-925b-4406-ab62-72118aa2f02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934153506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.934153506
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.114249916
Short name T8
Test name
Test status
Simulation time 25769069 ps
CPU time 1.17 seconds
Started Feb 21 12:54:37 PM PST 24
Finished Feb 21 12:54:41 PM PST 24
Peak memory 218840 kb
Host smart-687799eb-85b9-4df3-b43e-2cb3d430fc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114249916 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.114249916
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1227791514
Short name T481
Test name
Test status
Simulation time 83596936 ps
CPU time 1.12 seconds
Started Feb 21 12:54:39 PM PST 24
Finished Feb 21 12:54:42 PM PST 24
Peak memory 216192 kb
Host smart-65e0dcf9-e0af-4bc3-8e18-d18baaafb8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227791514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1227791514
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.3375643089
Short name T605
Test name
Test status
Simulation time 29956857 ps
CPU time 0.95 seconds
Started Feb 21 12:54:35 PM PST 24
Finished Feb 21 12:54:36 PM PST 24
Peak memory 217740 kb
Host smart-a80d16ce-d637-437d-b655-0a582d977396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375643089 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3375643089
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3904610109
Short name T530
Test name
Test status
Simulation time 43209788 ps
CPU time 1.56 seconds
Started Feb 21 12:54:34 PM PST 24
Finished Feb 21 12:54:36 PM PST 24
Peak memory 217100 kb
Host smart-4e75ac25-61da-4021-804c-2f0c44d3582b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904610109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3904610109
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.2514778287
Short name T527
Test name
Test status
Simulation time 19515394 ps
CPU time 1.27 seconds
Started Feb 21 12:54:35 PM PST 24
Finished Feb 21 12:54:37 PM PST 24
Peak memory 222788 kb
Host smart-464e491d-7d70-4f25-ab2e-203fce90243a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514778287 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2514778287
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2949319138
Short name T770
Test name
Test status
Simulation time 47429264 ps
CPU time 1.59 seconds
Started Feb 21 12:54:35 PM PST 24
Finished Feb 21 12:54:37 PM PST 24
Peak memory 218472 kb
Host smart-88e61aba-3073-499f-b2d5-ca8f7e0a4865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949319138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2949319138
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.1117603121
Short name T95
Test name
Test status
Simulation time 29359268 ps
CPU time 1.12 seconds
Started Feb 21 12:54:36 PM PST 24
Finished Feb 21 12:54:38 PM PST 24
Peak memory 222732 kb
Host smart-725cf89d-c1cc-44f7-bbf4-a3498c40f37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117603121 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1117603121
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2112976371
Short name T429
Test name
Test status
Simulation time 71272829 ps
CPU time 1.22 seconds
Started Feb 21 12:54:38 PM PST 24
Finished Feb 21 12:54:41 PM PST 24
Peak memory 217372 kb
Host smart-57f7c615-dd6d-47cc-a3d5-dbf9c5aff132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112976371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2112976371
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.473227017
Short name T94
Test name
Test status
Simulation time 25500506 ps
CPU time 0.91 seconds
Started Feb 21 12:54:27 PM PST 24
Finished Feb 21 12:54:29 PM PST 24
Peak memory 217464 kb
Host smart-d33a35e0-e61e-4fdf-9db8-56d03e230074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473227017 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.473227017
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.4138198773
Short name T761
Test name
Test status
Simulation time 38166554 ps
CPU time 1.4 seconds
Started Feb 21 12:54:38 PM PST 24
Finished Feb 21 12:54:41 PM PST 24
Peak memory 216128 kb
Host smart-48a9722f-7d37-4a0b-9fa1-999b73295e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138198773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.4138198773
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1221910311
Short name T57
Test name
Test status
Simulation time 154288362 ps
CPU time 1.34 seconds
Started Feb 21 12:52:40 PM PST 24
Finished Feb 21 12:52:42 PM PST 24
Peak memory 215132 kb
Host smart-b0f91f1e-19dd-496c-acc8-280826007197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221910311 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1221910311
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3375908247
Short name T631
Test name
Test status
Simulation time 67968941 ps
CPU time 0.95 seconds
Started Feb 21 12:52:40 PM PST 24
Finished Feb 21 12:52:42 PM PST 24
Peak memory 206332 kb
Host smart-6980c4ec-55a9-40ee-b5b9-479195fbdf93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375908247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3375908247
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3074639851
Short name T494
Test name
Test status
Simulation time 11320116 ps
CPU time 0.86 seconds
Started Feb 21 12:52:40 PM PST 24
Finished Feb 21 12:52:41 PM PST 24
Peak memory 206888 kb
Host smart-8c6c6a22-a21a-4ac9-b06d-c401b062a55f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074639851 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3074639851
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_err.3651814996
Short name T96
Test name
Test status
Simulation time 58877574 ps
CPU time 0.82 seconds
Started Feb 21 12:52:40 PM PST 24
Finished Feb 21 12:52:41 PM PST 24
Peak memory 216988 kb
Host smart-778bf6c1-6817-4945-b26c-6de79e9ec4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651814996 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3651814996
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.4089127890
Short name T195
Test name
Test status
Simulation time 45520869 ps
CPU time 1.28 seconds
Started Feb 21 12:52:41 PM PST 24
Finished Feb 21 12:52:42 PM PST 24
Peak memory 218784 kb
Host smart-e8601fb5-eb9a-4878-915e-500665b04b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089127890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.4089127890
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3528635158
Short name T700
Test name
Test status
Simulation time 20238901 ps
CPU time 0.97 seconds
Started Feb 21 12:52:40 PM PST 24
Finished Feb 21 12:52:42 PM PST 24
Peak memory 215208 kb
Host smart-9cdc1538-b2e5-4954-a8f1-c5e2c44fb713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528635158 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3528635158
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.546843145
Short name T115
Test name
Test status
Simulation time 25933994 ps
CPU time 0.88 seconds
Started Feb 21 12:52:40 PM PST 24
Finished Feb 21 12:52:41 PM PST 24
Peak memory 206436 kb
Host smart-fd06b204-e16a-47c4-bb3f-cdf7c8afdfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546843145 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.546843145
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.3580952271
Short name T314
Test name
Test status
Simulation time 19070649 ps
CPU time 1.03 seconds
Started Feb 21 12:52:41 PM PST 24
Finished Feb 21 12:52:43 PM PST 24
Peak memory 214724 kb
Host smart-c5977a01-245e-4252-819e-3ab2e10df7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580952271 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3580952271
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2528638451
Short name T355
Test name
Test status
Simulation time 191345206 ps
CPU time 4 seconds
Started Feb 21 12:52:40 PM PST 24
Finished Feb 21 12:52:44 PM PST 24
Peak memory 216028 kb
Host smart-b78827cf-4cff-4a4a-902c-7e59e34638d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528638451 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2528638451
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2601269347
Short name T703
Test name
Test status
Simulation time 141119913040 ps
CPU time 1567.77 seconds
Started Feb 21 12:52:40 PM PST 24
Finished Feb 21 01:18:49 PM PST 24
Peak memory 224024 kb
Host smart-fc2305c7-6c81-4f05-8dd7-72c7eaa1d024
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601269347 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2601269347
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.1319464016
Short name T56
Test name
Test status
Simulation time 55819935 ps
CPU time 1.09 seconds
Started Feb 21 12:54:36 PM PST 24
Finished Feb 21 12:54:38 PM PST 24
Peak memory 229196 kb
Host smart-01333a1b-da96-4b45-b9f9-3fbec487667a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319464016 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1319464016
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1644048162
Short name T684
Test name
Test status
Simulation time 27549439 ps
CPU time 1.17 seconds
Started Feb 21 12:54:30 PM PST 24
Finished Feb 21 12:54:32 PM PST 24
Peak memory 218040 kb
Host smart-c414ff18-1ee2-4cc6-9d6f-e4eb64fb980c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644048162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1644048162
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.1240445684
Short name T824
Test name
Test status
Simulation time 28025925 ps
CPU time 1.01 seconds
Started Feb 21 12:54:31 PM PST 24
Finished Feb 21 12:54:32 PM PST 24
Peak memory 222332 kb
Host smart-c470e64c-8cd8-4231-bba8-b851d2e4c24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240445684 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1240445684
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/72.edn_err.3449198187
Short name T101
Test name
Test status
Simulation time 67118682 ps
CPU time 0.8 seconds
Started Feb 21 12:54:32 PM PST 24
Finished Feb 21 12:54:34 PM PST 24
Peak memory 217108 kb
Host smart-40df08f7-ff8f-48f0-a3b7-68d932814366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449198187 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3449198187
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/73.edn_err.1025771034
Short name T649
Test name
Test status
Simulation time 30433237 ps
CPU time 1.12 seconds
Started Feb 21 12:54:38 PM PST 24
Finished Feb 21 12:54:41 PM PST 24
Peak memory 215016 kb
Host smart-1c1199e7-a06b-4a20-b155-ea2f3eb5e937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025771034 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1025771034
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.58790329
Short name T749
Test name
Test status
Simulation time 43299433 ps
CPU time 1.4 seconds
Started Feb 21 12:54:31 PM PST 24
Finished Feb 21 12:54:32 PM PST 24
Peak memory 217144 kb
Host smart-088e353a-a3c3-46eb-9c83-f015f4aa5c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58790329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.58790329
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.3908784592
Short name T67
Test name
Test status
Simulation time 25270111 ps
CPU time 1.12 seconds
Started Feb 21 12:54:34 PM PST 24
Finished Feb 21 12:54:36 PM PST 24
Peak memory 219312 kb
Host smart-f2fc773c-db34-445d-b71a-341c4b298f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908784592 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3908784592
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3112703416
Short name T810
Test name
Test status
Simulation time 243113212 ps
CPU time 3.62 seconds
Started Feb 21 12:54:34 PM PST 24
Finished Feb 21 12:54:38 PM PST 24
Peak memory 217148 kb
Host smart-6a675d34-47e8-47b1-94e7-bcd6a09639c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112703416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3112703416
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.3023881853
Short name T442
Test name
Test status
Simulation time 18251007 ps
CPU time 1.02 seconds
Started Feb 21 12:54:39 PM PST 24
Finished Feb 21 12:54:42 PM PST 24
Peak memory 217508 kb
Host smart-ec170afc-8532-4202-8ff6-6a881845552b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023881853 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3023881853
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3566781867
Short name T516
Test name
Test status
Simulation time 38489095 ps
CPU time 1.44 seconds
Started Feb 21 12:54:40 PM PST 24
Finished Feb 21 12:54:43 PM PST 24
Peak memory 215600 kb
Host smart-4c1bcc78-4ee5-4f1d-a87e-9fec0db4655e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566781867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3566781867
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.556080362
Short name T602
Test name
Test status
Simulation time 30519851 ps
CPU time 0.98 seconds
Started Feb 21 12:54:33 PM PST 24
Finished Feb 21 12:54:34 PM PST 24
Peak memory 222416 kb
Host smart-133a9bff-d033-42fa-bfd2-055274d72411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556080362 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.556080362
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.863925825
Short name T211
Test name
Test status
Simulation time 28788204 ps
CPU time 1.15 seconds
Started Feb 21 12:54:37 PM PST 24
Finished Feb 21 12:54:39 PM PST 24
Peak memory 215968 kb
Host smart-606fb6fc-236c-4a37-82aa-c98f6c34b612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863925825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.863925825
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.74028560
Short name T9
Test name
Test status
Simulation time 49899146 ps
CPU time 1.26 seconds
Started Feb 21 12:54:34 PM PST 24
Finished Feb 21 12:54:36 PM PST 24
Peak memory 223516 kb
Host smart-f5edaafc-dd9e-4b62-b74b-98d4cd302919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74028560 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.74028560
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.373560680
Short name T325
Test name
Test status
Simulation time 47499201 ps
CPU time 1.63 seconds
Started Feb 21 12:54:38 PM PST 24
Finished Feb 21 12:54:41 PM PST 24
Peak memory 216164 kb
Host smart-d317d414-f5ab-4cd7-af8c-aa423ae9e1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373560680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.373560680
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.2789802827
Short name T665
Test name
Test status
Simulation time 45481970 ps
CPU time 1.35 seconds
Started Feb 21 12:54:39 PM PST 24
Finished Feb 21 12:54:41 PM PST 24
Peak memory 218784 kb
Host smart-763fa2b1-cd78-42c7-adb4-69b6c2fe5c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789802827 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2789802827
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.193314413
Short name T49
Test name
Test status
Simulation time 122311690 ps
CPU time 1.64 seconds
Started Feb 21 12:54:40 PM PST 24
Finished Feb 21 12:54:43 PM PST 24
Peak memory 215912 kb
Host smart-606a475b-5c93-437b-8c00-046e3ab9775e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193314413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.193314413
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.3926802326
Short name T390
Test name
Test status
Simulation time 25277789 ps
CPU time 1.18 seconds
Started Feb 21 12:54:37 PM PST 24
Finished Feb 21 12:54:41 PM PST 24
Peak memory 217460 kb
Host smart-30a4aa3f-bd0b-4f68-adde-045bff74efea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926802326 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3926802326
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2764470930
Short name T336
Test name
Test status
Simulation time 54258673 ps
CPU time 1.01 seconds
Started Feb 21 12:54:35 PM PST 24
Finished Feb 21 12:54:38 PM PST 24
Peak memory 215948 kb
Host smart-e128f000-0acd-4e77-bfc1-f4f027455c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764470930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2764470930
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.339988291
Short name T138
Test name
Test status
Simulation time 25903261 ps
CPU time 1.18 seconds
Started Feb 21 12:52:38 PM PST 24
Finished Feb 21 12:52:39 PM PST 24
Peak memory 215100 kb
Host smart-f4aefe1d-d492-4315-930a-534c19707cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339988291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.339988291
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.53377011
Short name T334
Test name
Test status
Simulation time 28987740 ps
CPU time 0.77 seconds
Started Feb 21 12:52:42 PM PST 24
Finished Feb 21 12:52:43 PM PST 24
Peak memory 205008 kb
Host smart-ab79973f-9775-493a-826d-ff1506ff73b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53377011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.53377011
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.1180122032
Short name T86
Test name
Test status
Simulation time 118034224 ps
CPU time 0.84 seconds
Started Feb 21 12:52:41 PM PST 24
Finished Feb 21 12:52:42 PM PST 24
Peak memory 215156 kb
Host smart-ee2bf063-3f40-42df-9add-d73a6d407aab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180122032 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1180122032
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1858086881
Short name T396
Test name
Test status
Simulation time 33652146 ps
CPU time 1.26 seconds
Started Feb 21 12:52:42 PM PST 24
Finished Feb 21 12:52:43 PM PST 24
Peak memory 216004 kb
Host smart-1a3db671-6518-421f-bf4c-405a19933687
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858086881 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1858086881
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1042420869
Short name T566
Test name
Test status
Simulation time 19100663 ps
CPU time 1.02 seconds
Started Feb 21 12:52:45 PM PST 24
Finished Feb 21 12:52:46 PM PST 24
Peak memory 217376 kb
Host smart-8fb19f4c-6463-4740-b1b7-9a0e6e912759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042420869 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1042420869
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.390952379
Short name T240
Test name
Test status
Simulation time 38021077 ps
CPU time 1.32 seconds
Started Feb 21 12:52:38 PM PST 24
Finished Feb 21 12:52:40 PM PST 24
Peak memory 218564 kb
Host smart-22bf3316-0db6-4621-bcc3-3cb107c9e933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390952379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.390952379
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2249162283
Short name T715
Test name
Test status
Simulation time 27987935 ps
CPU time 1.04 seconds
Started Feb 21 12:52:45 PM PST 24
Finished Feb 21 12:52:46 PM PST 24
Peak memory 222580 kb
Host smart-80cc1a29-d27c-407a-b864-12b684d7a018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249162283 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2249162283
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.459696007
Short name T559
Test name
Test status
Simulation time 17417922 ps
CPU time 0.95 seconds
Started Feb 21 12:52:38 PM PST 24
Finished Feb 21 12:52:39 PM PST 24
Peak memory 206528 kb
Host smart-58624adb-88cc-49c2-98f9-6806896be545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459696007 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.459696007
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1684212813
Short name T682
Test name
Test status
Simulation time 14935976 ps
CPU time 0.95 seconds
Started Feb 21 12:52:41 PM PST 24
Finished Feb 21 12:52:42 PM PST 24
Peak memory 214776 kb
Host smart-8abdc670-f965-454e-887d-fe48afb7e7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684212813 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1684212813
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1284532910
Short name T564
Test name
Test status
Simulation time 966620277 ps
CPU time 3.37 seconds
Started Feb 21 12:52:38 PM PST 24
Finished Feb 21 12:52:41 PM PST 24
Peak memory 214784 kb
Host smart-e6fbb2dc-9102-4964-81eb-99dd5d0cc722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284532910 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1284532910
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2838071661
Short name T178
Test name
Test status
Simulation time 100508521319 ps
CPU time 969.74 seconds
Started Feb 21 12:52:39 PM PST 24
Finished Feb 21 01:08:50 PM PST 24
Peak memory 221180 kb
Host smart-bad88664-3a05-41eb-9b87-7de77e8deb12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838071661 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2838071661
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.894406202
Short name T246
Test name
Test status
Simulation time 19480542 ps
CPU time 1.02 seconds
Started Feb 21 12:54:36 PM PST 24
Finished Feb 21 12:54:38 PM PST 24
Peak memory 217168 kb
Host smart-ecd399c5-b175-44dc-9836-5e5f19c08f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894406202 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.894406202
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1371794851
Short name T297
Test name
Test status
Simulation time 397624777 ps
CPU time 4.32 seconds
Started Feb 21 12:54:37 PM PST 24
Finished Feb 21 12:54:42 PM PST 24
Peak memory 216116 kb
Host smart-e49ba384-25d8-4d72-85cc-ad7f182389ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371794851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1371794851
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.1120112213
Short name T82
Test name
Test status
Simulation time 31134995 ps
CPU time 1.35 seconds
Started Feb 21 12:54:39 PM PST 24
Finished Feb 21 12:54:41 PM PST 24
Peak memory 223724 kb
Host smart-2f3adef1-b940-4e99-9ef0-312bb3b19771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120112213 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1120112213
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.4116066640
Short name T275
Test name
Test status
Simulation time 4567316458 ps
CPU time 92.73 seconds
Started Feb 21 12:54:25 PM PST 24
Finished Feb 21 12:55:59 PM PST 24
Peak memory 218632 kb
Host smart-f3c3e562-bb90-4dab-87dc-db19dc4276db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116066640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.4116066640
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.2336568621
Short name T451
Test name
Test status
Simulation time 19281054 ps
CPU time 1.18 seconds
Started Feb 21 12:54:34 PM PST 24
Finished Feb 21 12:54:36 PM PST 24
Peak memory 222580 kb
Host smart-19d85914-3613-4da2-8b10-488e7523e8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336568621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2336568621
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3106620363
Short name T738
Test name
Test status
Simulation time 148608243 ps
CPU time 1.15 seconds
Started Feb 21 12:54:28 PM PST 24
Finished Feb 21 12:54:30 PM PST 24
Peak memory 218884 kb
Host smart-600a8567-55c1-4a6e-bc7f-93b0cd9e3716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106620363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3106620363
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.704531639
Short name T750
Test name
Test status
Simulation time 21586158 ps
CPU time 0.88 seconds
Started Feb 21 12:54:28 PM PST 24
Finished Feb 21 12:54:30 PM PST 24
Peak memory 217380 kb
Host smart-3bbd8e5d-2747-4402-943a-bd613f47a1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704531639 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.704531639
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2775594283
Short name T280
Test name
Test status
Simulation time 32887419 ps
CPU time 1.19 seconds
Started Feb 21 12:54:33 PM PST 24
Finished Feb 21 12:54:34 PM PST 24
Peak memory 215960 kb
Host smart-d7b0e83c-44bc-493a-8de9-239efbde276d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775594283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2775594283
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.3179934018
Short name T612
Test name
Test status
Simulation time 32123646 ps
CPU time 0.95 seconds
Started Feb 21 12:54:37 PM PST 24
Finished Feb 21 12:54:40 PM PST 24
Peak memory 222280 kb
Host smart-e2b86caf-0b16-42ca-95b5-50bb73c50277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179934018 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3179934018
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.348316313
Short name T497
Test name
Test status
Simulation time 61076512 ps
CPU time 1.07 seconds
Started Feb 21 12:54:39 PM PST 24
Finished Feb 21 12:54:42 PM PST 24
Peak memory 216144 kb
Host smart-76223121-4fd8-4b56-8342-fecfb7165f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348316313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.348316313
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.380395860
Short name T621
Test name
Test status
Simulation time 18719589 ps
CPU time 0.97 seconds
Started Feb 21 12:54:34 PM PST 24
Finished Feb 21 12:54:36 PM PST 24
Peak memory 217268 kb
Host smart-3b394c0f-4816-4d50-9b92-874be6e70808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380395860 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.380395860
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.912419531
Short name T802
Test name
Test status
Simulation time 485597188 ps
CPU time 2.34 seconds
Started Feb 21 12:54:34 PM PST 24
Finished Feb 21 12:54:37 PM PST 24
Peak memory 217704 kb
Host smart-968d4db6-a34b-49e6-b7bb-d5a59ab491be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912419531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.912419531
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.575801307
Short name T65
Test name
Test status
Simulation time 33560862 ps
CPU time 1.11 seconds
Started Feb 21 12:54:32 PM PST 24
Finished Feb 21 12:54:34 PM PST 24
Peak memory 218644 kb
Host smart-e60f56e0-903d-4244-939e-3912f5fdb262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575801307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.575801307
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.215664872
Short name T805
Test name
Test status
Simulation time 28995835 ps
CPU time 1.25 seconds
Started Feb 21 12:54:37 PM PST 24
Finished Feb 21 12:54:40 PM PST 24
Peak memory 217372 kb
Host smart-4c608406-d758-4797-a9fc-5459c7b75359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215664872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.215664872
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1651969868
Short name T55
Test name
Test status
Simulation time 48139345 ps
CPU time 1.06 seconds
Started Feb 21 12:54:38 PM PST 24
Finished Feb 21 12:54:41 PM PST 24
Peak memory 229224 kb
Host smart-f129711c-2998-427b-8890-95ba9e8fef69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651969868 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1651969868
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3364194693
Short name T431
Test name
Test status
Simulation time 95354244 ps
CPU time 1.12 seconds
Started Feb 21 12:54:36 PM PST 24
Finished Feb 21 12:54:38 PM PST 24
Peak memory 214752 kb
Host smart-90c8e295-dc21-4ca2-8f02-bfdef1f00b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364194693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3364194693
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.2679452227
Short name T404
Test name
Test status
Simulation time 18364080 ps
CPU time 1 seconds
Started Feb 21 12:54:30 PM PST 24
Finished Feb 21 12:54:32 PM PST 24
Peak memory 217396 kb
Host smart-c4dd447e-eb3b-49c9-9a92-bdb119ef9b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679452227 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2679452227
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1048448271
Short name T326
Test name
Test status
Simulation time 169257050 ps
CPU time 2.32 seconds
Started Feb 21 12:54:39 PM PST 24
Finished Feb 21 12:54:42 PM PST 24
Peak memory 217280 kb
Host smart-3e147c43-0fdc-48a9-9c1a-0d5ea0bae6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048448271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1048448271
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.22041617
Short name T753
Test name
Test status
Simulation time 34113773 ps
CPU time 0.95 seconds
Started Feb 21 12:54:37 PM PST 24
Finished Feb 21 12:54:40 PM PST 24
Peak memory 230524 kb
Host smart-3cbd64c9-e9ed-45a0-b986-0e38406d4818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22041617 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.22041617
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3840091265
Short name T673
Test name
Test status
Simulation time 131555442 ps
CPU time 2.84 seconds
Started Feb 21 12:54:37 PM PST 24
Finished Feb 21 12:54:42 PM PST 24
Peak memory 216176 kb
Host smart-e3c97870-4390-41de-b9c9-c694d4a92c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840091265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3840091265
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3222143183
Short name T264
Test name
Test status
Simulation time 39637129 ps
CPU time 1.08 seconds
Started Feb 21 12:52:40 PM PST 24
Finished Feb 21 12:52:41 PM PST 24
Peak memory 215124 kb
Host smart-04482284-04f4-4cf9-a137-48c2e280fad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222143183 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3222143183
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.3152685768
Short name T311
Test name
Test status
Simulation time 23794076 ps
CPU time 1.12 seconds
Started Feb 21 12:52:40 PM PST 24
Finished Feb 21 12:52:42 PM PST 24
Peak memory 205992 kb
Host smart-af70ca4a-2512-49d9-ab4b-75e1c2fab369
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152685768 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3152685768
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1483923486
Short name T466
Test name
Test status
Simulation time 52511706 ps
CPU time 1.13 seconds
Started Feb 21 12:52:43 PM PST 24
Finished Feb 21 12:52:45 PM PST 24
Peak memory 215796 kb
Host smart-ff0078f2-db0c-4242-b28f-678f6b7cc189
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483923486 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1483923486
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.884012155
Short name T405
Test name
Test status
Simulation time 37054047 ps
CPU time 0.89 seconds
Started Feb 21 12:52:43 PM PST 24
Finished Feb 21 12:52:45 PM PST 24
Peak memory 217580 kb
Host smart-c0cddf52-86a7-4bc0-a83c-31e813f30edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884012155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.884012155
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.962643120
Short name T712
Test name
Test status
Simulation time 69646747 ps
CPU time 1.09 seconds
Started Feb 21 12:52:40 PM PST 24
Finished Feb 21 12:52:41 PM PST 24
Peak memory 218336 kb
Host smart-27e236ca-f68e-4dcf-95ce-dc1a436a6e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962643120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.962643120
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3158904154
Short name T244
Test name
Test status
Simulation time 38012029 ps
CPU time 0.85 seconds
Started Feb 21 12:52:41 PM PST 24
Finished Feb 21 12:52:42 PM PST 24
Peak memory 214856 kb
Host smart-1230a8c4-ba7e-44a0-bfd4-cca3d6ca58e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158904154 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3158904154
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1705711346
Short name T273
Test name
Test status
Simulation time 17932452 ps
CPU time 0.98 seconds
Started Feb 21 12:52:40 PM PST 24
Finished Feb 21 12:52:42 PM PST 24
Peak memory 206600 kb
Host smart-75aaeba5-aedf-4536-b2e0-e1a7ae4374da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705711346 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1705711346
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3403476033
Short name T360
Test name
Test status
Simulation time 29615519 ps
CPU time 0.91 seconds
Started Feb 21 12:52:42 PM PST 24
Finished Feb 21 12:52:43 PM PST 24
Peak memory 214752 kb
Host smart-c10b81f9-7125-44da-87da-536a13d6a48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403476033 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3403476033
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1026698238
Short name T652
Test name
Test status
Simulation time 278219433 ps
CPU time 2.9 seconds
Started Feb 21 12:52:40 PM PST 24
Finished Feb 21 12:52:43 PM PST 24
Peak memory 214828 kb
Host smart-ff31f305-01c2-4f1f-8a5c-adb515267ad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026698238 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1026698238
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/90.edn_err.465977231
Short name T323
Test name
Test status
Simulation time 22776696 ps
CPU time 0.91 seconds
Started Feb 21 12:54:46 PM PST 24
Finished Feb 21 12:54:47 PM PST 24
Peak memory 217176 kb
Host smart-17878747-4f95-4e40-af35-5bb7a7876491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465977231 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.465977231
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1430752100
Short name T364
Test name
Test status
Simulation time 55424150 ps
CPU time 1.04 seconds
Started Feb 21 12:54:38 PM PST 24
Finished Feb 21 12:54:41 PM PST 24
Peak memory 216080 kb
Host smart-18df1ec9-e2c7-4159-bcea-94f01b023911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430752100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1430752100
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.1649244492
Short name T39
Test name
Test status
Simulation time 35840570 ps
CPU time 1.14 seconds
Started Feb 21 12:54:34 PM PST 24
Finished Feb 21 12:54:36 PM PST 24
Peak memory 222488 kb
Host smart-fffdaff8-a684-490a-b7f8-9725ef24e84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649244492 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.1649244492
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2655347944
Short name T759
Test name
Test status
Simulation time 111605405 ps
CPU time 1.69 seconds
Started Feb 21 12:54:51 PM PST 24
Finished Feb 21 12:54:53 PM PST 24
Peak memory 218596 kb
Host smart-f16b4f05-576f-4066-9569-568ed8ddbbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655347944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2655347944
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.4095619392
Short name T383
Test name
Test status
Simulation time 24465578 ps
CPU time 0.95 seconds
Started Feb 21 12:54:42 PM PST 24
Finished Feb 21 12:54:44 PM PST 24
Peak memory 218712 kb
Host smart-654b2a25-3d94-4725-aec6-06e2b16a8976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095619392 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.4095619392
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2977114748
Short name T188
Test name
Test status
Simulation time 150918523 ps
CPU time 2.56 seconds
Started Feb 21 12:54:40 PM PST 24
Finished Feb 21 12:54:44 PM PST 24
Peak memory 216312 kb
Host smart-54a6c8a7-bbce-4572-a9bb-6df69ef5ae22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977114748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2977114748
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.79732652
Short name T106
Test name
Test status
Simulation time 25165246 ps
CPU time 0.86 seconds
Started Feb 21 12:54:40 PM PST 24
Finished Feb 21 12:54:42 PM PST 24
Peak memory 217092 kb
Host smart-8c364a91-899a-442f-86f2-17e3282af2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79732652 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.79732652
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.4836543
Short name T318
Test name
Test status
Simulation time 67934959 ps
CPU time 1.39 seconds
Started Feb 21 12:54:36 PM PST 24
Finished Feb 21 12:54:39 PM PST 24
Peak memory 217252 kb
Host smart-b8a8316e-d3a9-4c32-86d3-f1f42bd64e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4836543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.4836543
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.756113919
Short name T795
Test name
Test status
Simulation time 66904692 ps
CPU time 0.85 seconds
Started Feb 21 12:54:46 PM PST 24
Finished Feb 21 12:54:47 PM PST 24
Peak memory 218832 kb
Host smart-aa0182df-73c1-4749-b411-14ab5e85f70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756113919 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.756113919
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3174300586
Short name T321
Test name
Test status
Simulation time 202729793 ps
CPU time 3.11 seconds
Started Feb 21 12:54:43 PM PST 24
Finished Feb 21 12:54:47 PM PST 24
Peak memory 218008 kb
Host smart-042e63dd-c3bb-4c1f-bd7f-38b21c65c014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174300586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3174300586
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.2198738186
Short name T157
Test name
Test status
Simulation time 29545659 ps
CPU time 1.21 seconds
Started Feb 21 12:54:48 PM PST 24
Finished Feb 21 12:54:50 PM PST 24
Peak memory 218524 kb
Host smart-f496a50b-b5e1-44db-b11f-630ee847e96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198738186 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2198738186
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.951056540
Short name T367
Test name
Test status
Simulation time 29814127 ps
CPU time 1.3 seconds
Started Feb 21 12:54:52 PM PST 24
Finished Feb 21 12:54:54 PM PST 24
Peak memory 218392 kb
Host smart-fea22ba0-60ab-4b26-a1f2-22643c1cd13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951056540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.951056540
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.583060580
Short name T841
Test name
Test status
Simulation time 33644960 ps
CPU time 1.04 seconds
Started Feb 21 12:54:54 PM PST 24
Finished Feb 21 12:54:56 PM PST 24
Peak memory 222504 kb
Host smart-5fc2f82b-cb37-4c16-a048-3159405ba969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583060580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.583060580
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.234130658
Short name T377
Test name
Test status
Simulation time 49129400 ps
CPU time 1.58 seconds
Started Feb 21 12:54:53 PM PST 24
Finished Feb 21 12:54:55 PM PST 24
Peak memory 218592 kb
Host smart-c55a8c17-5b30-4814-856c-a16472603feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234130658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.234130658
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.1807924839
Short name T432
Test name
Test status
Simulation time 44798621 ps
CPU time 1.11 seconds
Started Feb 21 12:54:47 PM PST 24
Finished Feb 21 12:54:48 PM PST 24
Peak memory 218744 kb
Host smart-f5735a1b-5edf-46ac-a120-acb80f718510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807924839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1807924839
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2019444424
Short name T486
Test name
Test status
Simulation time 42262023 ps
CPU time 1.79 seconds
Started Feb 21 12:54:54 PM PST 24
Finished Feb 21 12:54:57 PM PST 24
Peak memory 216060 kb
Host smart-32b3e9ea-bbd1-4159-9f13-e58157851036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019444424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2019444424
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1414584932
Short name T107
Test name
Test status
Simulation time 29063853 ps
CPU time 0.95 seconds
Started Feb 21 12:54:51 PM PST 24
Finished Feb 21 12:54:53 PM PST 24
Peak memory 222244 kb
Host smart-4125f808-3691-4ed4-ab22-38ee35c4d9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414584932 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1414584932
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.444077255
Short name T254
Test name
Test status
Simulation time 92153866 ps
CPU time 1.13 seconds
Started Feb 21 12:54:52 PM PST 24
Finished Feb 21 12:54:54 PM PST 24
Peak memory 215996 kb
Host smart-51c8db45-0155-47fb-a789-219b15621b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444077255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.444077255
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.1483806965
Short name T650
Test name
Test status
Simulation time 20700757 ps
CPU time 1.22 seconds
Started Feb 21 12:54:54 PM PST 24
Finished Feb 21 12:54:56 PM PST 24
Peak memory 218888 kb
Host smart-7bde7946-5691-48f4-a351-7b50ea992657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483806965 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1483806965
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1898220053
Short name T252
Test name
Test status
Simulation time 238801254 ps
CPU time 1.12 seconds
Started Feb 21 12:54:48 PM PST 24
Finished Feb 21 12:54:50 PM PST 24
Peak memory 216204 kb
Host smart-c588147f-bbe7-4d55-a467-e0d374437b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898220053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1898220053
Directory /workspace/99.edn_genbits/latest
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