ASSERT | PROPERTIES | SEQUENCES | |
Total | 428 | 0 | 10 |
Category 0 | 428 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 428 | 0 | 10 |
Severity 0 | 428 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 428 | 100.00 |
Uncovered | 15 | 3.50 |
Success | 413 | 96.50 |
Failure | 0 | 0.00 |
Incomplete | 9 | 2.10 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep.DataOStableWhenPending_A | 0 | 0 | 239957160 | 221266468 | 0 | 807 | |
tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep.DataOStableWhenPending_A | 0 | 0 | 239957160 | 362994 | 0 | 807 | |
tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep.DataOStableWhenPending_A | 0 | 0 | 239957160 | 262865 | 0 | 807 | |
tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep.DataOStableWhenPending_A | 0 | 0 | 239957160 | 240626 | 0 | 807 | |
tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep.DataOStableWhenPending_A | 0 | 0 | 239957160 | 211661 | 0 | 807 | |
tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep.DataOStableWhenPending_A | 0 | 0 | 239957160 | 201000 | 0 | 807 | |
tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep.DataOStableWhenPending_A | 0 | 0 | 239957160 | 164498 | 0 | 807 | |
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb.RoundRobin_A | 0 | 0 | 239957160 | 0 | 0 | 807 | |
tb.dut.u_edn_core.u_prim_packer_fifo_cs.DataOStableWhenPending_A | 0 | 0 | 239957160 | 119672 | 0 | 807 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 240444175 | 353 | 353 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 240444175 | 98 | 98 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 240444175 | 99 | 99 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 240444175 | 67 | 67 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 240444175 | 12 | 12 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 240444175 | 56 | 56 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 240444175 | 63 | 63 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 240444175 | 2115 | 2115 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 240444175 | 3631 | 3631 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 240444175 | 58849 | 58849 | 907 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 240444175 | 353 | 353 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 240444175 | 98 | 98 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 240444175 | 99 | 99 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 240444175 | 67 | 67 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 240444175 | 12 | 12 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 240444175 | 56 | 56 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 240444175 | 63 | 63 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 240444175 | 2115 | 2115 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 240444175 | 3631 | 3631 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 240444175 | 58849 | 58849 | 907 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |