Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_sw_cmd_sts_cg

Group : tb.dut.u_edn_cov_if::edn_sw_cmd_sts_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
87.50	87.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_sw_cmd_sts_cg	87.50	1	100	1	64	64

---

Group Instance : edn_sw_cmd_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.50	1	100	1	64	64

---

Summary for Group Instance edn_sw_cmd_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	1	7	87.50

Variables for Group Instance edn_sw_cmd_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_cmd_ack_cg	2	0	2	100.00	100	1	1	0
cp_cmd_rdy_cg	2	0	2	100.00	100	1	1	0
cp_cmd_reg_rdy_cg	2	0	2	100.00	100	1	1	0
cp_cmd_sts_cg	2	1	1	50.00	100	1	1	0

Summary for Variable cp_cmd_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_cmd_ack_cg

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

no_ack

26596

1

T17

19

T8

11

T22

19

ack

21432

1

T17

7

T8

5

T22

7

---

Summary for Variable cp_cmd_rdy_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_cmd_rdy_cg

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

not_ready

25782

1

T17

18

T8

11

T22

18

ready

22246

1

T17

8

T8

5

T22

8

---

Summary for Variable cp_cmd_reg_rdy_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_cmd_reg_rdy_cg

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

not_ready

500

1

T8

1

T31

1

T40

1

ready

47528

1

T17

26

T8

15

T22

26

---

Summary for Variable cp_cmd_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for cp_cmd_sts_cg

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
error	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

success

48028

1

T17

26

T8

16

T22

26