Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	591077	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4641359

1

T1

49

T2

58

T3

39

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1395053	1			T1	5		T2	5		T3	40
values[0x0]	1774634	1			T1	30		T2	31		T3	21
values[0x1]	2062749	1			T1	27		T2	33		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	295560	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4936876

1

T1

50

T2

62

T3

54

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19583	1			T2	1		T29	1		T31	1
valid_sources[0x01]	20116	1			T22	1		T29	3		T31	1
valid_sources[0x02]	20070	1			T31	1		T24	3		T25	18
valid_sources[0x03]	20521	1			T22	3		T31	2		T67	1
valid_sources[0x04]	20931	1			T18	6		T27	2		T31	2
valid_sources[0x05]	21487	1			T3	2		T17	1		T29	2
valid_sources[0x06]	19346	1			T4	2		T31	1		T26	1
valid_sources[0x07]	21390	1			T33	2		T147	1		T41	4
valid_sources[0x08]	18235	1			T3	1		T4	1		T22	5
valid_sources[0x09]	21450	1			T22	2		T12	4		T31	1
valid_sources[0x0a]	22230	1			T24	2		T33	1		T243	1
valid_sources[0x0b]	20756	1			T3	1		T17	2		T22	3
valid_sources[0x0c]	20032	1			T22	2		T29	2		T13	16
valid_sources[0x0d]	23010	1			T22	2		T181	4		T31	2
valid_sources[0x0e]	20323	1			T3	1		T67	1		T26	1
valid_sources[0x0f]	19619	1			T3	1		T31	2		T24	2
valid_sources[0x10]	19855	1			T17	7		T18	2		T29	1
valid_sources[0x11]	20454	1			T18	2		T31	1		T33	1
valid_sources[0x12]	22403	1			T31	1		T24	1		T33	3
valid_sources[0x13]	20590	1			T2	1		T31	3		T67	1
valid_sources[0x14]	22524	1			T31	1		T24	2		T33	2
valid_sources[0x15]	22048	1			T2	1		T146	1		T26	1
valid_sources[0x16]	20526	1			T3	1		T22	2		T180	48
valid_sources[0x17]	21096	1			T22	1		T31	1		T5	11
valid_sources[0x18]	22074	1			T3	1		T22	1		T24	1
valid_sources[0x19]	21789	1			T2	1		T22	4		T31	2
valid_sources[0x1a]	19962	1			T22	3		T18	2		T27	2
valid_sources[0x1b]	20244	1			T33	1		T70	89		T39	3
valid_sources[0x1c]	19408	1			T3	1		T29	1		T33	1
valid_sources[0x1d]	20106	1			T4	4		T13	1		T24	1
valid_sources[0x1e]	24187	1			T2	1		T22	3		T5	8
valid_sources[0x1f]	19838	1			T22	1		T67	1		T6	1
valid_sources[0x20]	23918	1			T17	1		T22	3		T29	1
valid_sources[0x21]	18667	1			T4	2		T22	3		T29	1
valid_sources[0x22]	19520	1			T3	2		T24	1		T33	3
valid_sources[0x23]	20441	1			T3	1		T31	6		T67	1
valid_sources[0x24]	20269	1			T31	1		T67	1		T33	2
valid_sources[0x25]	20490	1			T29	1		T31	1		T33	3
valid_sources[0x26]	20901	1			T22	2		T67	1		T6	1
valid_sources[0x27]	21485	1			T2	3		T29	1		T27	1
valid_sources[0x28]	20673	1			T18	2		T24	1		T33	1
valid_sources[0x29]	21050	1			T31	1		T67	1		T24	1
valid_sources[0x2a]	19797	1			T2	1		T31	3		T26	1
valid_sources[0x2b]	19928	1			T3	1		T4	1		T18	3
valid_sources[0x2c]	20032	1			T67	1		T24	1		T33	1
valid_sources[0x2d]	22430	1			T22	4		T29	1		T27	1
valid_sources[0x2e]	18982	1			T3	2		T17	4		T4	1
valid_sources[0x2f]	18655	1			T2	3		T18	3		T27	1
valid_sources[0x30]	21329	1			T2	3		T31	1		T24	2
valid_sources[0x31]	21703	1			T2	2		T3	1		T25	7
valid_sources[0x32]	21187	1			T22	6		T146	9		T31	1
valid_sources[0x33]	19158	1			T18	1		T146	2		T31	1
valid_sources[0x34]	18678	1			T2	1		T22	3		T67	1
valid_sources[0x35]	22517	1			T2	1		T3	1		T29	3
valid_sources[0x36]	21990	1			T22	3		T33	1		T6	1
valid_sources[0x37]	19922	1			T2	1		T17	2		T18	3
valid_sources[0x38]	20583	1			T3	1		T22	3		T33	3
valid_sources[0x39]	23033	1			T17	1		T22	1		T24	1
valid_sources[0x3a]	18779	1			T2	1		T22	1		T33	2
valid_sources[0x3b]	20467	1			T22	1		T29	1		T27	1
valid_sources[0x3c]	21396	1			T18	1		T29	1		T31	3
valid_sources[0x3d]	19939	1			T2	2		T31	1		T33	2
valid_sources[0x3e]	20407	1			T3	1		T27	1		T13	20
valid_sources[0x3f]	20254	1			T2	1		T4	2		T22	1
valid_sources[0x40]	21060	1			T22	3		T29	2		T33	3
valid_sources[0x41]	19181	1			T22	1		T12	3		T18	1
valid_sources[0x42]	19612	1			T22	2		T13	1		T31	1
valid_sources[0x43]	20785	1			T22	1		T31	1		T24	1
valid_sources[0x44]	19264	1			T2	1		T4	1		T18	4
valid_sources[0x45]	18997	1			T29	1		T27	1		T67	3
valid_sources[0x46]	20397	1			T2	1		T17	1		T18	2
valid_sources[0x47]	20690	1			T22	1		T31	1		T67	1
valid_sources[0x48]	20749	1			T2	1		T22	5		T18	1
valid_sources[0x49]	21775	1			T18	4		T29	1		T31	2
valid_sources[0x4a]	21328	1			T22	3		T67	1		T24	1
valid_sources[0x4b]	19759	1			T3	1		T22	1		T27	2
valid_sources[0x4c]	19876	1			T22	3		T27	1		T146	6
valid_sources[0x4d]	19349	1			T2	1		T22	3		T12	1
valid_sources[0x4e]	20169	1			T22	2		T18	3		T29	1
valid_sources[0x4f]	19870	1			T22	1		T12	2		T27	1
valid_sources[0x50]	20581	1			T3	1		T24	2		T33	2
valid_sources[0x51]	19831	1			T22	1		T12	1		T18	1
valid_sources[0x52]	21020	1			T2	1		T29	1		T27	1
valid_sources[0x53]	23341	1			T2	1		T3	1		T17	2
valid_sources[0x54]	20721	1			T22	1		T67	1		T26	2
valid_sources[0x55]	20584	1			T4	3		T22	5		T31	1
valid_sources[0x56]	20290	1			T17	4		T24	1		T33	3
valid_sources[0x57]	20182	1			T22	5		T31	1		T24	1
valid_sources[0x58]	19194	1			T22	1		T18	1		T29	1
valid_sources[0x59]	19592	1			T12	1		T24	1		T33	1
valid_sources[0x5a]	23192	1			T26	2		T24	1		T33	1
valid_sources[0x5b]	21101	1			T22	3		T67	1		T33	2
valid_sources[0x5c]	21689	1			T18	4		T27	1		T146	2
valid_sources[0x5d]	20576	1			T22	2		T12	8		T67	3
valid_sources[0x5e]	18817	1			T22	5		T18	2		T29	1
valid_sources[0x5f]	20350	1			T2	1		T29	1		T67	1
valid_sources[0x60]	19669	1			T2	1		T3	2		T17	2
valid_sources[0x61]	22212	1			T3	1		T24	3		T33	2
valid_sources[0x62]	19084	1			T2	1		T3	1		T22	2
valid_sources[0x63]	19815	1			T4	1		T29	2		T33	2
valid_sources[0x64]	20637	1			T3	1		T24	1		T33	1
valid_sources[0x65]	21127	1			T18	5		T31	1		T24	5
valid_sources[0x66]	20868	1			T31	1		T24	1		T33	1
valid_sources[0x67]	19353	1			T2	1		T22	3		T27	1
valid_sources[0x68]	18909	1			T2	1		T3	1		T18	2
valid_sources[0x69]	19822	1			T2	1		T24	1		T6	3
valid_sources[0x6a]	21216	1			T4	1		T27	1		T31	3
valid_sources[0x6b]	17594	1			T29	1		T181	11		T31	1
valid_sources[0x6c]	20406	1			T17	1		T12	1		T18	5
valid_sources[0x6d]	19885	1			T3	27		T22	2		T26	1
valid_sources[0x6e]	21456	1			T12	6		T18	8		T29	2
valid_sources[0x6f]	20260	1			T3	2		T27	1		T13	15
valid_sources[0x70]	20579	1			T3	1		T22	2		T18	1
valid_sources[0x71]	18420	1			T2	1		T17	1		T4	1
valid_sources[0x72]	22280	1			T2	1		T28	36		T31	1
valid_sources[0x73]	20283	1			T8	91		T22	2		T31	1
valid_sources[0x74]	19684	1			T18	2		T29	2		T27	1
valid_sources[0x75]	20401	1			T22	5		T27	1		T25	2
valid_sources[0x76]	19427	1			T31	3		T24	1		T6	1
valid_sources[0x77]	21695	1			T2	1		T24	2		T6	1
valid_sources[0x78]	21444	1			T4	6		T22	1		T31	1
valid_sources[0x79]	19615	1			T2	1		T22	3		T12	3
valid_sources[0x7a]	22612	1			T12	1		T24	1		T33	2
valid_sources[0x7b]	19388	1			T146	5		T31	1		T24	2
valid_sources[0x7c]	22199	1			T22	7		T29	2		T31	2
valid_sources[0x7d]	21830	1			T3	1		T146	1		T33	3
valid_sources[0x7e]	19548	1			T2	1		T17	1		T22	1
valid_sources[0x7f]	19918	1			T22	1		T27	1		T31	1
valid_sources[0x80]	21775	1			T22	1		T146	5		T24	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1170064

1

T3

10

T17

3

T4

2

values[0x0]

all_enables

biggest_size

1737306

1

T1

26

T2

29

T3

18

values[0x1]

all_enables

biggest_size

1733989

1

T1

23

T2

29

T3

11