Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
67.19	67.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	67.19	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
67.19	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	21	31	59.62

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	21	31	59.62	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2515	1			T17	2		T8	1		T22	3
non_zero_bins[1]	1793	1			T17	1		T8	1		T18	2
zero	8275	1			T1	1		T3	6		T17	1

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	475	1			T25	1		T41	2		T42	2
uni	3518	1			T17	1		T22	1		T28	1
gen	3767	1			T3	3		T17	1		T4	1
res	791	1			T3	1		T17	1		T8	1
ins	4032	1			T1	1		T3	2		T17	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8530

1

T1

1

T3

3

T17

1

mubi_true

4053

1

T3

3

T17

3

T8

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

50

1

T3

1

T12

1

T13

1

pass

12533

1

T1

1

T3

5

T17

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	21	31	59.62	21
Automatically Generated Cross Bins	52	21	31	59.62	21
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	116	1			T42	1		T19	1		T20	4
upd	non_zero_bins[0]	pass	mubi_true	109	1			T25	1		T41	1		T21	5
upd	non_zero_bins[1]	pass	mubi_false	71	1			T41	1		T19	1		T20	2
upd	non_zero_bins[1]	pass	mubi_true	80	1			T42	1		T19	2		T20	1
upd	zero	pass	mubi_false	47	1			T20	1		T242	1		T141	1
upd	zero	pass	mubi_true	52	1			T19	1		T20	1		T21	1
uni	zero	fail	mubi_false	11	1			T122	1		T123	1		T124	1
uni	zero	pass	mubi_false	2566	1			T17	1		T22	1		T18	1
uni	zero	pass	mubi_true	941	1			T28	1		T180	1		T146	1
gen	non_zero_bins[0]	pass	mubi_false	446	1			T22	1		T30	1		T6	15
gen	non_zero_bins[0]	pass	mubi_true	455	1			T17	1		T31	2		T67	1
gen	non_zero_bins[1]	pass	mubi_false	322	1			T40	2		T5	1		T50	1
gen	non_zero_bins[1]	pass	mubi_true	335	1			T8	1		T18	1		T25	1
gen	zero	fail	mubi_false	25	1			T12	1		T13	1		T73	1
gen	zero	pass	mubi_false	1785	1			T3	1		T4	1		T28	1
gen	zero	pass	mubi_true	399	1			T3	2		T23	1		T12	2
res	non_zero_bins[0]	pass	mubi_false	175	1			T52	1		T19	1		T71	1
res	non_zero_bins[0]	pass	mubi_true	190	1			T22	1		T31	2		T40	2
res	non_zero_bins[1]	pass	mubi_false	121	1			T5	2		T243	1		T70	1
res	non_zero_bins[1]	pass	mubi_true	135	1			T17	1		T18	1		T33	2
res	zero	fail	mubi_false	7	1			T3	1		T184	1		T188	1
res	zero	pass	mubi_false	96	1			T93	1		T21	2		T244	1
res	zero	pass	mubi_true	67	1			T8	1		T50	2		T245	2
ins	non_zero_bins[0]	pass	mubi_false	509	1			T29	1		T24	1		T25	1
ins	non_zero_bins[0]	pass	mubi_true	515	1			T17	1		T8	1		T22	1
ins	non_zero_bins[1]	pass	mubi_false	355	1			T29	1		T30	1		T33	1
ins	non_zero_bins[1]	pass	mubi_true	374	1			T67	1		T40	1		T24	1
ins	zero	fail	mubi_false	6	1			T107	1		T108	1		T246	1
ins	zero	fail	mubi_true	1	1			T106	1		-	-		-	-
ins	zero	pass	mubi_false	1872	1			T1	1		T3	1		T4	1
ins	zero	pass	mubi_true	400	1			T3	1		T12	1		T30	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded