Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.41	100.00	89.63			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.41	100.00	89.63			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.41	100.00	89.63			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.41	100.00	89.63			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.41	100.00	89.63			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.41	100.00	89.63			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.41	100.00	89.63			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T17,T4
DataWait	75	Covered	T3,T17,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T119,T121,T156
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T17,T4
DataWait->AckPls	80	Covered	T3,T17,T4
DataWait->Disabled	107	Covered	T70,T75,T157
DataWait->Error	99	Covered	T51,T11,T158
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T15,T16
EndPointClear->Disabled	107	Covered	T41,T42,T114
EndPointClear->Error	99	Covered	T2,T46,T87
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T17,T4
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T1,T4,T64

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T17,T4
Idle	-	1	0	-	Covered	T3,T17,T4
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T17,T4
DataWait	-	-	-	0	Covered	T3,T17,T4
AckPls	-	-	-	-	Covered	T3,T17,T4
Error	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	Covered	T4,T64,T27

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1272973898	869069	0	0
FpvSecCmErrorStEscalate_A	1272973898	873766	0	0
u_state_regs_A	1272938615	1271974029	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272973898	869069	0	0
T1	6209	2450	0	0
T2	10906	4396	0	0
T3	16891	0	0	0
T4	5586	2190	0	0
T8	47278	0	0	0
T9	0	4536	0	0
T10	0	2793	0	0
T12	13727	0	0	0
T17	18823	0	0	0
T22	11501	0	0	0
T23	9842	0	0	0
T27	0	2470	0	0
T28	11529	0	0	0
T51	0	4290	0	0
T64	0	6320	0	0
T65	0	1455	0	0
T66	0	2400	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272973898	873766	0	0
T1	6209	2457	0	0
T2	10906	4403	0	0
T3	16891	0	0	0
T4	5586	2197	0	0
T8	47278	0	0	0
T9	0	4543	0	0
T10	0	2800	0	0
T12	13727	0	0	0
T17	18823	0	0	0
T22	11501	0	0	0
T23	9842	0	0	0
T27	0	2477	0	0
T28	11529	0	0	0
T51	0	4297	0	0
T64	0	6327	0	0
T65	0	1462	0	0
T66	0	2407	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272938615	1271974029	0	0
T1	6049	4880	0	0
T2	10726	9655	0	0
T3	16891	16443	0	0
T4	5415	4218	0	0
T8	47278	46928	0	0
T12	13727	13188	0	0
T17	18823	18361	0	0
T22	11501	11130	0	0
T23	9842	9394	0	0
T28	11529	10864	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T22,T12,T26
DataWait	75	Covered	T22,T12,T26
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T22,T12,T26
DataWait->AckPls	80	Covered	T22,T12,T26
DataWait->Disabled	107	Covered	T109,T159,T110
DataWait->Error	99	Covered	T51,T82,T160
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T15,T16
EndPointClear->Disabled	107	Covered	T41,T42,T114
EndPointClear->Error	99	Covered	T2,T46,T87
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T22,T12,T26
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T1,T4,T64

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T22,T12,T26
Idle	-	1	0	-	Covered	T22,T12,T26
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T22,T12,T26
DataWait	-	-	-	0	Covered	T22,T12,T40
AckPls	-	-	-	-	Covered	T22,T12,T26
Error	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	181853414	124517	0	0
FpvSecCmErrorStEscalate_A	181853414	125188	0	0
u_state_regs_A	181853414	181715616	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181853414	124517	0	0
T1	887	350	0	0
T2	1558	628	0	0
T3	2413	0	0	0
T4	798	320	0	0
T8	6754	0	0	0
T9	0	648	0	0
T10	0	399	0	0
T12	1961	0	0	0
T17	2689	0	0	0
T22	1643	0	0	0
T23	1406	0	0	0
T27	0	360	0	0
T28	1647	0	0	0
T51	0	620	0	0
T64	0	910	0	0
T65	0	215	0	0
T66	0	350	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181853414	125188	0	0
T1	887	351	0	0
T2	1558	629	0	0
T3	2413	0	0	0
T4	798	321	0	0
T8	6754	0	0	0
T9	0	649	0	0
T10	0	400	0	0
T12	1961	0	0	0
T17	2689	0	0	0
T22	1643	0	0	0
T23	1406	0	0	0
T27	0	361	0	0
T28	1647	0	0	0
T51	0	621	0	0
T64	0	911	0	0
T65	0	216	0	0
T66	0	351	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181853414	181715616	0	0
T1	887	720	0	0
T2	1558	1405	0	0
T3	2413	2349	0	0
T4	798	627	0	0
T8	6754	6704	0	0
T12	1961	1884	0	0
T17	2689	2623	0	0
T22	1643	1590	0	0
T23	1406	1342	0	0
T28	1647	1552	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T22,T35
DataWait	75	Covered	T3,T22,T35
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T22,T35
DataWait->AckPls	80	Covered	T3,T22,T35
DataWait->Disabled	107	Covered	T100,T161
DataWait->Error	99	Covered	T11,T81,T105
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T15,T16
EndPointClear->Disabled	107	Covered	T41,T42,T114
EndPointClear->Error	99	Covered	T2,T46,T87
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T22,T35
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T1,T4,T64

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T22,T35
Idle	-	1	0	-	Covered	T3,T22,T35
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T22,T35
DataWait	-	-	-	0	Covered	T22,T33,T6
AckPls	-	-	-	-	Covered	T3,T22,T35
Error	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	181853414	124517	0	0
FpvSecCmErrorStEscalate_A	181853414	125188	0	0
u_state_regs_A	181853414	181715616	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181853414	124517	0	0
T1	887	350	0	0
T2	1558	628	0	0
T3	2413	0	0	0
T4	798	320	0	0
T8	6754	0	0	0
T9	0	648	0	0
T10	0	399	0	0
T12	1961	0	0	0
T17	2689	0	0	0
T22	1643	0	0	0
T23	1406	0	0	0
T27	0	360	0	0
T28	1647	0	0	0
T51	0	620	0	0
T64	0	910	0	0
T65	0	215	0	0
T66	0	350	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181853414	125188	0	0
T1	887	351	0	0
T2	1558	629	0	0
T3	2413	0	0	0
T4	798	321	0	0
T8	6754	0	0	0
T9	0	649	0	0
T10	0	400	0	0
T12	1961	0	0	0
T17	2689	0	0	0
T22	1643	0	0	0
T23	1406	0	0	0
T27	0	361	0	0
T28	1647	0	0	0
T51	0	621	0	0
T64	0	911	0	0
T65	0	216	0	0
T66	0	351	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181853414	181715616	0	0
T1	887	720	0	0
T2	1558	1405	0	0
T3	2413	2349	0	0
T4	798	627	0	0
T8	6754	6704	0	0
T12	1961	1884	0	0
T17	2689	2623	0	0
T22	1643	1590	0	0
T23	1406	1342	0	0
T28	1647	1552	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T12,T40,T25
DataWait	75	Covered	T1,T12,T27
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T12,T40,T25
DataWait->AckPls	80	Covered	T12,T40,T25
DataWait->Disabled	107	Covered	T162,T63,T163
DataWait->Error	99	Covered	T1,T27,T164
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T15,T16
EndPointClear->Disabled	107	Covered	T41,T42,T114
EndPointClear->Error	99	Covered	T2,T46,T87
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T12,T27
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T64,T65

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T12,T40,T25
Idle	-	1	0	-	Covered	T1,T12,T27
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T12,T40,T25
DataWait	-	-	-	0	Covered	T1,T27,T40
AckPls	-	-	-	-	Covered	T12,T40,T25
Error	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	181853414	124517	0	0
FpvSecCmErrorStEscalate_A	181853414	125188	0	0
u_state_regs_A	181853414	181715616	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181853414	124517	0	0
T1	887	350	0	0
T2	1558	628	0	0
T3	2413	0	0	0
T4	798	320	0	0
T8	6754	0	0	0
T9	0	648	0	0
T10	0	399	0	0
T12	1961	0	0	0
T17	2689	0	0	0
T22	1643	0	0	0
T23	1406	0	0	0
T27	0	360	0	0
T28	1647	0	0	0
T51	0	620	0	0
T64	0	910	0	0
T65	0	215	0	0
T66	0	350	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181853414	125188	0	0
T1	887	351	0	0
T2	1558	629	0	0
T3	2413	0	0	0
T4	798	321	0	0
T8	6754	0	0	0
T9	0	649	0	0
T10	0	400	0	0
T12	1961	0	0	0
T17	2689	0	0	0
T22	1643	0	0	0
T23	1406	0	0	0
T27	0	361	0	0
T28	1647	0	0	0
T51	0	621	0	0
T64	0	911	0	0
T65	0	216	0	0
T66	0	351	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181853414	181715616	0	0
T1	887	720	0	0
T2	1558	1405	0	0
T3	2413	2349	0	0
T4	798	627	0	0
T8	6754	6704	0	0
T12	1961	1884	0	0
T17	2689	2623	0	0
T22	1643	1590	0	0
T23	1406	1342	0	0
T28	1647	1552	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T17,T8
DataWait	75	Covered	T3,T17,T8
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T119
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T17,T8
DataWait->AckPls	80	Covered	T3,T17,T8
DataWait->Disabled	107	Covered	T76,T92,T165
DataWait->Error	99	Covered	T155,T47,T101
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T15,T16
EndPointClear->Disabled	107	Covered	T41,T42,T114
EndPointClear->Error	99	Covered	T2,T46,T166
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T17,T8
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T1,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T17,T8
Idle	-	1	0	-	Covered	T3,T17,T8
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T17,T8
DataWait	-	-	-	0	Covered	T3,T17,T8
AckPls	-	-	-	-	Covered	T3,T17,T8
Error	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	Covered	T4,T64,T27

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	181853414	121967	0	0
FpvSecCmErrorStEscalate_A	181853414	122638	0	0
u_state_regs_A	181818131	181680333	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181853414	121967	0	0
T1	887	350	0	0
T2	1558	628	0	0
T3	2413	0	0	0
T4	798	270	0	0
T8	6754	0	0	0
T9	0	648	0	0
T10	0	399	0	0
T12	1961	0	0	0
T17	2689	0	0	0
T22	1643	0	0	0
T23	1406	0	0	0
T27	0	310	0	0
T28	1647	0	0	0
T51	0	570	0	0
T64	0	860	0	0
T65	0	165	0	0
T66	0	300	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181853414	122638	0	0
T1	887	351	0	0
T2	1558	629	0	0
T3	2413	0	0	0
T4	798	271	0	0
T8	6754	0	0	0
T9	0	649	0	0
T10	0	400	0	0
T12	1961	0	0	0
T17	2689	0	0	0
T22	1643	0	0	0
T23	1406	0	0	0
T27	0	311	0	0
T28	1647	0	0	0
T51	0	571	0	0
T64	0	861	0	0
T65	0	166	0	0
T66	0	301	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181818131	181680333	0	0
T1	727	560	0	0
T2	1378	1225	0	0
T3	2413	2349	0	0
T4	627	456	0	0
T8	6754	6704	0	0
T12	1961	1884	0	0
T17	2689	2623	0	0
T22	1643	1590	0	0
T23	1406	1342	0	0
T28	1647	1552	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T4,T22,T23
DataWait	75	Covered	T4,T22,T23
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T156
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T4,T22,T23
DataWait->AckPls	80	Covered	T4,T22,T23
DataWait->Disabled	107	Covered	T70,T75,T157
DataWait->Error	99	Covered	T158,T98,T167
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T15,T16
EndPointClear->Disabled	107	Covered	T41,T42,T114
EndPointClear->Error	99	Covered	T2,T46,T87
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T4,T22,T23
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T1,T4,T64

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T4,T22,T23
Idle	-	1	0	-	Covered	T4,T22,T23
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T4,T22,T23
DataWait	-	-	-	0	Covered	T4,T22,T23
AckPls	-	-	-	-	Covered	T4,T22,T23
Error	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	181853414	124517	0	0
FpvSecCmErrorStEscalate_A	181853414	125188	0	0
u_state_regs_A	181853414	181715616	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181853414	124517	0	0
T1	887	350	0	0
T2	1558	628	0	0
T3	2413	0	0	0
T4	798	320	0	0
T8	6754	0	0	0
T9	0	648	0	0
T10	0	399	0	0
T12	1961	0	0	0
T17	2689	0	0	0
T22	1643	0	0	0
T23	1406	0	0	0
T27	0	360	0	0
T28	1647	0	0	0
T51	0	620	0	0
T64	0	910	0	0
T65	0	215	0	0
T66	0	350	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181853414	125188	0	0
T1	887	351	0	0
T2	1558	629	0	0
T3	2413	0	0	0
T4	798	321	0	0
T8	6754	0	0	0
T9	0	649	0	0
T10	0	400	0	0
T12	1961	0	0	0
T17	2689	0	0	0
T22	1643	0	0	0
T23	1406	0	0	0
T27	0	361	0	0
T28	1647	0	0	0
T51	0	621	0	0
T64	0	911	0	0
T65	0	216	0	0
T66	0	351	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181853414	181715616	0	0
T1	887	720	0	0
T2	1558	1405	0	0
T3	2413	2349	0	0
T4	798	627	0	0
T8	6754	6704	0	0
T12	1961	1884	0	0
T17	2689	2623	0	0
T22	1643	1590	0	0
T23	1406	1342	0	0
T28	1647	1552	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T22,T24,T25
DataWait	75	Covered	T22,T24,T25
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T168
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T22,T24,T25
DataWait->AckPls	80	Covered	T22,T24,T25
DataWait->Disabled	107	Covered	T169,T170,T171
DataWait->Error	99	Covered	T172,T173
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T15,T16
EndPointClear->Disabled	107	Covered	T41,T42,T114
EndPointClear->Error	99	Covered	T2,T46,T87
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T22,T24,T25
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T1,T4,T64

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T22,T24,T25
Idle	-	1	0	-	Covered	T22,T24,T25
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T22,T24,T25
DataWait	-	-	-	0	Covered	T22,T24,T25
AckPls	-	-	-	-	Covered	T22,T24,T25
Error	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	181853414	124517	0	0
FpvSecCmErrorStEscalate_A	181853414	125188	0	0
u_state_regs_A	181853414	181715616	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181853414	124517	0	0
T1	887	350	0	0
T2	1558	628	0	0
T3	2413	0	0	0
T4	798	320	0	0
T8	6754	0	0	0
T9	0	648	0	0
T10	0	399	0	0
T12	1961	0	0	0
T17	2689	0	0	0
T22	1643	0	0	0
T23	1406	0	0	0
T27	0	360	0	0
T28	1647	0	0	0
T51	0	620	0	0
T64	0	910	0	0
T65	0	215	0	0
T66	0	350	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181853414	125188	0	0
T1	887	351	0	0
T2	1558	629	0	0
T3	2413	0	0	0
T4	798	321	0	0
T8	6754	0	0	0
T9	0	649	0	0
T10	0	400	0	0
T12	1961	0	0	0
T17	2689	0	0	0
T22	1643	0	0	0
T23	1406	0	0	0
T27	0	361	0	0
T28	1647	0	0	0
T51	0	621	0	0
T64	0	911	0	0
T65	0	216	0	0
T66	0	351	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181853414	181715616	0	0
T1	887	720	0	0
T2	1558	1405	0	0
T3	2413	2349	0	0
T4	798	627	0	0
T8	6754	6704	0	0
T12	1961	1884	0	0
T17	2689	2623	0	0
T22	1643	1590	0	0
T23	1406	1342	0	0
T28	1647	1552	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T22,T13,T25
DataWait	75	Covered	T22,T13,T25
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T121,T174
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T22,T13,T25
DataWait->AckPls	80	Covered	T22,T13,T25
DataWait->Disabled	107	Covered	T175,T176,T177
DataWait->Error	99	Covered	T83,T178,T179
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T15,T16
EndPointClear->Disabled	107	Covered	T41,T42,T114
EndPointClear->Error	99	Covered	T2,T46,T87
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T22,T13,T25
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T1,T4,T64

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T22,T13,T25
Idle	-	1	0	-	Covered	T22,T13,T25
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T22,T13,T25
DataWait	-	-	-	0	Covered	T22,T13,T25
AckPls	-	-	-	-	Covered	T22,T13,T25
Error	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	181853414	124517	0	0
FpvSecCmErrorStEscalate_A	181853414	125188	0	0
u_state_regs_A	181853414	181715616	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181853414	124517	0	0
T1	887	350	0	0
T2	1558	628	0	0
T3	2413	0	0	0
T4	798	320	0	0
T8	6754	0	0	0
T9	0	648	0	0
T10	0	399	0	0
T12	1961	0	0	0
T17	2689	0	0	0
T22	1643	0	0	0
T23	1406	0	0	0
T27	0	360	0	0
T28	1647	0	0	0
T51	0	620	0	0
T64	0	910	0	0
T65	0	215	0	0
T66	0	350	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181853414	125188	0	0
T1	887	351	0	0
T2	1558	629	0	0
T3	2413	0	0	0
T4	798	321	0	0
T8	6754	0	0	0
T9	0	649	0	0
T10	0	400	0	0
T12	1961	0	0	0
T17	2689	0	0	0
T22	1643	0	0	0
T23	1406	0	0	0
T27	0	361	0	0
T28	1647	0	0	0
T51	0	621	0	0
T64	0	911	0	0
T65	0	216	0	0
T66	0	351	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181853414	181715616	0	0
T1	887	720	0	0
T2	1558	1405	0	0
T3	2413	2349	0	0
T4	798	627	0	0
T8	6754	6704	0	0
T12	1961	1884	0	0
T17	2689	2623	0	0
T22	1643	1590	0	0
T23	1406	1342	0	0
T28	1647	1552	0	0