Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.85 98.27 93.56 96.84 81.50 96.87 96.58 93.35


Total test records in report: 970
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T787 /workspace/coverage/default/205.edn_genbits.1219321308 Feb 28 06:02:41 PM PST 24 Feb 28 06:02:43 PM PST 24 369209960 ps
T788 /workspace/coverage/default/46.edn_alert_test.2592506016 Feb 28 06:01:58 PM PST 24 Feb 28 06:01:59 PM PST 24 10623980 ps
T789 /workspace/coverage/default/3.edn_alert.531783049 Feb 28 06:00:02 PM PST 24 Feb 28 06:00:04 PM PST 24 112347050 ps
T790 /workspace/coverage/default/34.edn_alert.1343559413 Feb 28 06:01:27 PM PST 24 Feb 28 06:01:28 PM PST 24 24967955 ps
T791 /workspace/coverage/default/9.edn_stress_all.4217079552 Feb 28 06:00:25 PM PST 24 Feb 28 06:00:29 PM PST 24 683137059 ps
T792 /workspace/coverage/default/36.edn_err.1006721723 Feb 28 06:01:36 PM PST 24 Feb 28 06:01:37 PM PST 24 18607263 ps
T793 /workspace/coverage/default/29.edn_genbits.959035770 Feb 28 06:01:18 PM PST 24 Feb 28 06:01:20 PM PST 24 39072542 ps
T794 /workspace/coverage/default/293.edn_genbits.3366322940 Feb 28 06:02:58 PM PST 24 Feb 28 06:03:00 PM PST 24 209205942 ps
T795 /workspace/coverage/default/292.edn_genbits.2647525147 Feb 28 06:03:01 PM PST 24 Feb 28 06:03:03 PM PST 24 60699110 ps
T796 /workspace/coverage/default/71.edn_err.1288712944 Feb 28 06:02:08 PM PST 24 Feb 28 06:02:09 PM PST 24 23319257 ps
T797 /workspace/coverage/default/20.edn_disable_auto_req_mode.3526213852 Feb 28 06:00:59 PM PST 24 Feb 28 06:01:00 PM PST 24 27899875 ps
T798 /workspace/coverage/default/6.edn_genbits.908725181 Feb 28 06:00:17 PM PST 24 Feb 28 06:00:19 PM PST 24 62399467 ps
T799 /workspace/coverage/default/23.edn_stress_all.1353537922 Feb 28 06:01:04 PM PST 24 Feb 28 06:01:06 PM PST 24 218979651 ps
T800 /workspace/coverage/default/41.edn_smoke.3416134992 Feb 28 06:01:43 PM PST 24 Feb 28 06:01:44 PM PST 24 41400511 ps
T801 /workspace/coverage/default/226.edn_genbits.2067758881 Feb 28 06:02:46 PM PST 24 Feb 28 06:02:47 PM PST 24 44166077 ps
T802 /workspace/coverage/default/194.edn_genbits.3768160614 Feb 28 06:02:38 PM PST 24 Feb 28 06:02:41 PM PST 24 109630298 ps
T803 /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1028586313 Feb 28 06:02:05 PM PST 24 Feb 28 06:07:54 PM PST 24 21504777809 ps
T804 /workspace/coverage/default/48.edn_alert.2119540480 Feb 28 06:01:57 PM PST 24 Feb 28 06:01:58 PM PST 24 25794479 ps
T805 /workspace/coverage/default/54.edn_genbits.180888828 Feb 28 06:02:02 PM PST 24 Feb 28 06:02:03 PM PST 24 116825915 ps
T141 /workspace/coverage/default/1.edn_intr.425844477 Feb 28 05:59:53 PM PST 24 Feb 28 05:59:53 PM PST 24 35914856 ps
T806 /workspace/coverage/default/37.edn_disable.4079060764 Feb 28 06:01:36 PM PST 24 Feb 28 06:01:37 PM PST 24 41742707 ps
T807 /workspace/coverage/default/18.edn_intr.1869682097 Feb 28 06:00:48 PM PST 24 Feb 28 06:00:49 PM PST 24 35968653 ps
T142 /workspace/coverage/default/37.edn_intr.543767291 Feb 28 06:01:40 PM PST 24 Feb 28 06:01:41 PM PST 24 22962204 ps
T808 /workspace/coverage/default/18.edn_genbits.719874663 Feb 28 06:00:50 PM PST 24 Feb 28 06:00:51 PM PST 24 70226397 ps
T809 /workspace/coverage/default/43.edn_genbits.1932836083 Feb 28 06:01:48 PM PST 24 Feb 28 06:01:49 PM PST 24 32759000 ps
T810 /workspace/coverage/default/49.edn_alert_test.705793490 Feb 28 06:02:02 PM PST 24 Feb 28 06:02:03 PM PST 24 28276535 ps
T811 /workspace/coverage/default/3.edn_disable.2587207779 Feb 28 06:00:07 PM PST 24 Feb 28 06:00:08 PM PST 24 75531242 ps
T812 /workspace/coverage/default/278.edn_genbits.3032750260 Feb 28 06:02:55 PM PST 24 Feb 28 06:02:57 PM PST 24 41801756 ps
T813 /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3752026009 Feb 28 06:01:10 PM PST 24 Feb 28 06:18:50 PM PST 24 45906136657 ps
T814 /workspace/coverage/default/172.edn_genbits.2761687113 Feb 28 06:02:38 PM PST 24 Feb 28 06:02:40 PM PST 24 53560531 ps
T815 /workspace/coverage/default/1.edn_genbits.2510592135 Feb 28 05:59:52 PM PST 24 Feb 28 05:59:55 PM PST 24 229483214 ps
T816 /workspace/coverage/default/39.edn_intr.4058876780 Feb 28 06:01:43 PM PST 24 Feb 28 06:01:45 PM PST 24 29349304 ps
T817 /workspace/coverage/default/41.edn_stress_all_with_rand_reset.4169159714 Feb 28 06:01:43 PM PST 24 Feb 28 06:23:31 PM PST 24 224954720454 ps
T818 /workspace/coverage/default/26.edn_disable.3697767788 Feb 28 06:01:10 PM PST 24 Feb 28 06:01:11 PM PST 24 43391557 ps
T262 /workspace/coverage/default/199.edn_genbits.3567889018 Feb 28 06:02:41 PM PST 24 Feb 28 06:02:42 PM PST 24 77691580 ps
T266 /workspace/coverage/default/16.edn_genbits.1613769189 Feb 28 06:00:46 PM PST 24 Feb 28 06:00:48 PM PST 24 44131634 ps
T819 /workspace/coverage/default/18.edn_alert_test.2270415825 Feb 28 06:00:53 PM PST 24 Feb 28 06:00:54 PM PST 24 19034928 ps
T820 /workspace/coverage/default/4.edn_smoke.94574233 Feb 28 06:00:06 PM PST 24 Feb 28 06:00:07 PM PST 24 16351096 ps
T821 /workspace/coverage/default/34.edn_err.1199839571 Feb 28 06:01:28 PM PST 24 Feb 28 06:01:29 PM PST 24 20691839 ps
T172 /workspace/coverage/default/34.edn_disable_auto_req_mode.2010830331 Feb 28 06:01:29 PM PST 24 Feb 28 06:01:31 PM PST 24 51648849 ps
T822 /workspace/coverage/default/251.edn_genbits.770376902 Feb 28 06:02:50 PM PST 24 Feb 28 06:02:52 PM PST 24 47471539 ps
T823 /workspace/coverage/default/268.edn_genbits.914405682 Feb 28 06:02:52 PM PST 24 Feb 28 06:02:53 PM PST 24 33914654 ps
T824 /workspace/coverage/default/107.edn_genbits.197665421 Feb 28 06:02:26 PM PST 24 Feb 28 06:02:28 PM PST 24 31697812 ps
T825 /workspace/coverage/default/82.edn_genbits.1605260240 Feb 28 06:02:16 PM PST 24 Feb 28 06:02:18 PM PST 24 47777997 ps
T826 /workspace/coverage/default/29.edn_err.2338675182 Feb 28 06:01:18 PM PST 24 Feb 28 06:01:19 PM PST 24 25640527 ps
T827 /workspace/coverage/default/37.edn_err.3340770017 Feb 28 06:01:39 PM PST 24 Feb 28 06:01:40 PM PST 24 36107435 ps
T828 /workspace/coverage/default/22.edn_alert_test.2944355467 Feb 28 06:01:03 PM PST 24 Feb 28 06:01:04 PM PST 24 14357083 ps
T829 /workspace/coverage/default/1.edn_err.3583610569 Feb 28 05:59:52 PM PST 24 Feb 28 05:59:53 PM PST 24 26442902 ps
T830 /workspace/coverage/default/47.edn_intr.532458540 Feb 28 06:01:59 PM PST 24 Feb 28 06:02:00 PM PST 24 28400999 ps
T831 /workspace/coverage/default/27.edn_disable_auto_req_mode.4070516060 Feb 28 06:01:16 PM PST 24 Feb 28 06:01:17 PM PST 24 126699103 ps
T832 /workspace/coverage/default/20.edn_stress_all.3601789988 Feb 28 06:00:54 PM PST 24 Feb 28 06:00:57 PM PST 24 239500700 ps
T833 /workspace/coverage/default/2.edn_err.134345477 Feb 28 06:00:01 PM PST 24 Feb 28 06:00:02 PM PST 24 32727885 ps
T834 /workspace/coverage/default/42.edn_disable.2786154428 Feb 28 06:01:48 PM PST 24 Feb 28 06:01:49 PM PST 24 26651425 ps
T835 /workspace/coverage/default/40.edn_genbits.80657752 Feb 28 06:01:40 PM PST 24 Feb 28 06:01:41 PM PST 24 19961899 ps
T836 /workspace/coverage/default/17.edn_disable_auto_req_mode.2367437152 Feb 28 06:00:48 PM PST 24 Feb 28 06:00:49 PM PST 24 39430215 ps
T200 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2996687665 Feb 28 04:26:42 PM PST 24 Feb 28 04:26:43 PM PST 24 33644307 ps
T837 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3770218292 Feb 28 04:27:07 PM PST 24 Feb 28 04:27:12 PM PST 24 119932245 ps
T838 /workspace/coverage/cover_reg_top/15.edn_intr_test.520426610 Feb 28 04:27:09 PM PST 24 Feb 28 04:27:10 PM PST 24 53819380 ps
T201 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2215430735 Feb 28 04:27:00 PM PST 24 Feb 28 04:27:01 PM PST 24 26162941 ps
T226 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2372508589 Feb 28 04:37:08 PM PST 24 Feb 28 04:37:10 PM PST 24 254579537 ps
T202 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3541660716 Feb 28 04:26:43 PM PST 24 Feb 28 04:26:44 PM PST 24 79542244 ps
T839 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3427326467 Feb 28 04:26:52 PM PST 24 Feb 28 04:26:54 PM PST 24 95770130 ps
T225 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2355437600 Feb 28 04:26:44 PM PST 24 Feb 28 04:26:45 PM PST 24 190572514 ps
T203 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1816754292 Feb 28 04:27:12 PM PST 24 Feb 28 04:27:13 PM PST 24 34194016 ps
T222 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2031572924 Feb 28 04:27:11 PM PST 24 Feb 28 04:27:13 PM PST 24 23804149 ps
T204 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.370004407 Feb 28 04:27:08 PM PST 24 Feb 28 04:27:09 PM PST 24 97937684 ps
T840 /workspace/coverage/cover_reg_top/6.edn_intr_test.2191683764 Feb 28 04:26:55 PM PST 24 Feb 28 04:26:56 PM PST 24 58679116 ps
T205 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.353987850 Feb 28 04:26:45 PM PST 24 Feb 28 04:26:46 PM PST 24 46639941 ps
T841 /workspace/coverage/cover_reg_top/2.edn_intr_test.680179108 Feb 28 04:26:39 PM PST 24 Feb 28 04:26:41 PM PST 24 43931106 ps
T842 /workspace/coverage/cover_reg_top/31.edn_intr_test.784482166 Feb 28 04:27:18 PM PST 24 Feb 28 04:27:19 PM PST 24 41296477 ps
T206 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3652564152 Feb 28 04:26:44 PM PST 24 Feb 28 04:26:46 PM PST 24 16720624 ps
T843 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3294382378 Feb 28 04:26:39 PM PST 24 Feb 28 04:26:42 PM PST 24 89520932 ps
T227 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.643335923 Feb 28 04:26:58 PM PST 24 Feb 28 04:27:00 PM PST 24 138218174 ps
T228 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1301152224 Feb 28 04:26:53 PM PST 24 Feb 28 04:26:56 PM PST 24 139739880 ps
T844 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2750749006 Feb 28 04:26:58 PM PST 24 Feb 28 04:26:59 PM PST 24 62338121 ps
T845 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.277051353 Feb 28 04:26:44 PM PST 24 Feb 28 04:26:46 PM PST 24 48791466 ps
T846 /workspace/coverage/cover_reg_top/13.edn_intr_test.798601680 Feb 28 04:27:08 PM PST 24 Feb 28 04:27:09 PM PST 24 14184308 ps
T847 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2921008968 Feb 28 04:27:05 PM PST 24 Feb 28 04:27:06 PM PST 24 66203158 ps
T848 /workspace/coverage/cover_reg_top/12.edn_intr_test.3346735470 Feb 28 04:27:05 PM PST 24 Feb 28 04:27:06 PM PST 24 11993680 ps
T223 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3288225768 Feb 28 04:26:52 PM PST 24 Feb 28 04:26:53 PM PST 24 20497391 ps
T849 /workspace/coverage/cover_reg_top/30.edn_intr_test.2613056571 Feb 28 04:27:18 PM PST 24 Feb 28 04:27:19 PM PST 24 35870583 ps
T850 /workspace/coverage/cover_reg_top/8.edn_tl_errors.2338431445 Feb 28 04:26:54 PM PST 24 Feb 28 04:26:57 PM PST 24 93172137 ps
T851 /workspace/coverage/cover_reg_top/18.edn_intr_test.1908447246 Feb 28 04:27:14 PM PST 24 Feb 28 04:27:16 PM PST 24 17965678 ps
T852 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2853062254 Feb 28 04:27:11 PM PST 24 Feb 28 04:27:13 PM PST 24 368899735 ps
T207 /workspace/coverage/cover_reg_top/10.edn_csr_rw.691486241 Feb 28 04:27:04 PM PST 24 Feb 28 04:27:05 PM PST 24 190503430 ps
T853 /workspace/coverage/cover_reg_top/0.edn_tl_errors.35387619 Feb 28 04:26:31 PM PST 24 Feb 28 04:26:34 PM PST 24 50728958 ps
T854 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3289334571 Feb 28 04:27:14 PM PST 24 Feb 28 04:27:15 PM PST 24 21475694 ps
T855 /workspace/coverage/cover_reg_top/25.edn_intr_test.2072781473 Feb 28 04:27:18 PM PST 24 Feb 28 04:27:18 PM PST 24 10894864 ps
T856 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2760241566 Feb 28 04:27:17 PM PST 24 Feb 28 04:27:19 PM PST 24 88043952 ps
T857 /workspace/coverage/cover_reg_top/16.edn_csr_rw.4025844196 Feb 28 04:27:09 PM PST 24 Feb 28 04:27:10 PM PST 24 107562951 ps
T858 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3355476836 Feb 28 04:26:53 PM PST 24 Feb 28 04:26:56 PM PST 24 301746398 ps
T859 /workspace/coverage/cover_reg_top/4.edn_csr_rw.3421542159 Feb 28 04:26:47 PM PST 24 Feb 28 04:26:48 PM PST 24 12812513 ps
T224 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1120308564 Feb 28 04:27:05 PM PST 24 Feb 28 04:27:06 PM PST 24 46930424 ps
T860 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.4213006949 Feb 28 04:26:48 PM PST 24 Feb 28 04:26:50 PM PST 24 38692144 ps
T861 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.824217120 Feb 28 04:27:12 PM PST 24 Feb 28 04:27:13 PM PST 24 96803129 ps
T862 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1766383449 Feb 28 04:26:59 PM PST 24 Feb 28 04:27:00 PM PST 24 98424515 ps
T863 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.71067574 Feb 28 04:27:01 PM PST 24 Feb 28 04:27:02 PM PST 24 99298471 ps
T208 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2125290407 Feb 28 04:27:06 PM PST 24 Feb 28 04:27:08 PM PST 24 13191025 ps
T864 /workspace/coverage/cover_reg_top/43.edn_intr_test.1754480101 Feb 28 04:27:24 PM PST 24 Feb 28 04:27:25 PM PST 24 90550400 ps
T865 /workspace/coverage/cover_reg_top/48.edn_intr_test.2084211347 Feb 28 04:27:43 PM PST 24 Feb 28 04:27:44 PM PST 24 165482078 ps
T866 /workspace/coverage/cover_reg_top/29.edn_intr_test.2367433869 Feb 28 04:27:16 PM PST 24 Feb 28 04:27:17 PM PST 24 164654721 ps
T867 /workspace/coverage/cover_reg_top/47.edn_intr_test.656279681 Feb 28 04:27:23 PM PST 24 Feb 28 04:27:24 PM PST 24 11801732 ps
T868 /workspace/coverage/cover_reg_top/24.edn_intr_test.2227862774 Feb 28 04:27:18 PM PST 24 Feb 28 04:27:19 PM PST 24 13811253 ps
T869 /workspace/coverage/cover_reg_top/41.edn_intr_test.1817435615 Feb 28 04:27:24 PM PST 24 Feb 28 04:27:25 PM PST 24 41224832 ps
T870 /workspace/coverage/cover_reg_top/18.edn_tl_errors.829243050 Feb 28 04:27:14 PM PST 24 Feb 28 04:27:17 PM PST 24 61732777 ps
T209 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3795960592 Feb 28 04:27:18 PM PST 24 Feb 28 04:27:20 PM PST 24 37420642 ps
T871 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.177807796 Feb 28 04:27:43 PM PST 24 Feb 28 04:27:45 PM PST 24 316839089 ps
T872 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3131195445 Feb 28 04:27:08 PM PST 24 Feb 28 04:27:10 PM PST 24 151996801 ps
T210 /workspace/coverage/cover_reg_top/0.edn_csr_rw.1626915067 Feb 28 04:26:32 PM PST 24 Feb 28 04:26:34 PM PST 24 24134994 ps
T873 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3743792576 Feb 28 04:26:46 PM PST 24 Feb 28 04:26:48 PM PST 24 50869029 ps
T235 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.902127834 Feb 28 04:26:55 PM PST 24 Feb 28 04:26:57 PM PST 24 381023932 ps
T874 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1835833596 Feb 28 04:27:13 PM PST 24 Feb 28 04:27:14 PM PST 24 52945189 ps
T875 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.662613290 Feb 28 04:27:08 PM PST 24 Feb 28 04:27:11 PM PST 24 151199594 ps
T876 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1162985193 Feb 28 04:27:12 PM PST 24 Feb 28 04:27:14 PM PST 24 46453330 ps
T877 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.39746631 Feb 28 04:26:55 PM PST 24 Feb 28 04:26:57 PM PST 24 201742030 ps
T878 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3072389299 Feb 28 04:26:34 PM PST 24 Feb 28 04:26:39 PM PST 24 51839582 ps
T211 /workspace/coverage/cover_reg_top/7.edn_csr_rw.822425147 Feb 28 04:26:55 PM PST 24 Feb 28 04:26:56 PM PST 24 21369333 ps
T879 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1542925357 Feb 28 04:27:15 PM PST 24 Feb 28 04:27:16 PM PST 24 39632828 ps
T236 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.167728595 Feb 28 04:27:16 PM PST 24 Feb 28 04:27:18 PM PST 24 74684710 ps
T880 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3970883245 Feb 28 04:27:04 PM PST 24 Feb 28 04:27:09 PM PST 24 141517703 ps
T881 /workspace/coverage/cover_reg_top/33.edn_intr_test.3392321889 Feb 28 04:27:22 PM PST 24 Feb 28 04:27:23 PM PST 24 13619710 ps
T882 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3874473401 Feb 28 04:27:08 PM PST 24 Feb 28 04:27:10 PM PST 24 56202980 ps
T883 /workspace/coverage/cover_reg_top/0.edn_intr_test.3145769002 Feb 28 04:26:29 PM PST 24 Feb 28 04:26:32 PM PST 24 35427711 ps
T884 /workspace/coverage/cover_reg_top/5.edn_tl_errors.4086693184 Feb 28 04:26:45 PM PST 24 Feb 28 04:26:49 PM PST 24 201966243 ps
T885 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1255256040 Feb 28 04:27:13 PM PST 24 Feb 28 04:27:14 PM PST 24 27343164 ps
T886 /workspace/coverage/cover_reg_top/2.edn_tl_errors.3012994135 Feb 28 04:26:38 PM PST 24 Feb 28 04:26:41 PM PST 24 275483360 ps
T887 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1940432452 Feb 28 04:27:13 PM PST 24 Feb 28 04:27:14 PM PST 24 77264359 ps
T888 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1161322162 Feb 28 04:27:09 PM PST 24 Feb 28 04:27:10 PM PST 24 60318097 ps
T889 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3911308493 Feb 28 04:26:46 PM PST 24 Feb 28 04:26:47 PM PST 24 28190160 ps
T890 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3512029689 Feb 28 04:27:04 PM PST 24 Feb 28 04:27:05 PM PST 24 16518342 ps
T891 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3669443388 Feb 28 04:26:51 PM PST 24 Feb 28 04:26:53 PM PST 24 100784899 ps
T892 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3400689815 Feb 28 04:26:42 PM PST 24 Feb 28 04:26:44 PM PST 24 18351735 ps
T893 /workspace/coverage/cover_reg_top/34.edn_intr_test.3318411292 Feb 28 04:27:22 PM PST 24 Feb 28 04:27:23 PM PST 24 37429160 ps
T894 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1566676174 Feb 28 04:26:54 PM PST 24 Feb 28 04:26:55 PM PST 24 21727461 ps
T895 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.256644897 Feb 28 04:27:13 PM PST 24 Feb 28 04:27:15 PM PST 24 156948761 ps
T896 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1591902616 Feb 28 04:27:13 PM PST 24 Feb 28 04:27:16 PM PST 24 43592700 ps
T897 /workspace/coverage/cover_reg_top/21.edn_intr_test.1260335541 Feb 28 04:27:17 PM PST 24 Feb 28 04:27:19 PM PST 24 23377845 ps
T898 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2305736148 Feb 28 04:27:08 PM PST 24 Feb 28 04:27:11 PM PST 24 75639266 ps
T899 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2362704709 Feb 28 04:26:34 PM PST 24 Feb 28 04:26:36 PM PST 24 30692750 ps
T900 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1131026801 Feb 28 04:27:08 PM PST 24 Feb 28 04:27:11 PM PST 24 246876242 ps
T901 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2822256906 Feb 28 04:26:34 PM PST 24 Feb 28 04:26:36 PM PST 24 28188652 ps
T212 /workspace/coverage/cover_reg_top/18.edn_csr_rw.461313813 Feb 28 04:27:17 PM PST 24 Feb 28 04:27:18 PM PST 24 12677421 ps
T213 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1425102752 Feb 28 04:26:37 PM PST 24 Feb 28 04:26:38 PM PST 24 16365829 ps
T902 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3461633045 Feb 28 04:26:50 PM PST 24 Feb 28 04:26:51 PM PST 24 40969139 ps
T903 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1862122496 Feb 28 04:27:05 PM PST 24 Feb 28 04:27:07 PM PST 24 28963302 ps
T904 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3961706014 Feb 28 04:26:37 PM PST 24 Feb 28 04:26:39 PM PST 24 47921986 ps
T905 /workspace/coverage/cover_reg_top/27.edn_intr_test.2073792082 Feb 28 04:27:19 PM PST 24 Feb 28 04:27:20 PM PST 24 46323210 ps
T906 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.250946693 Feb 28 04:26:32 PM PST 24 Feb 28 04:26:34 PM PST 24 26699459 ps
T907 /workspace/coverage/cover_reg_top/16.edn_intr_test.937009605 Feb 28 04:27:07 PM PST 24 Feb 28 04:27:08 PM PST 24 14440580 ps
T214 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1215228994 Feb 28 04:26:36 PM PST 24 Feb 28 04:26:37 PM PST 24 41991384 ps
T908 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3938401883 Feb 28 04:26:30 PM PST 24 Feb 28 04:26:33 PM PST 24 76510911 ps
T909 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1925104363 Feb 28 04:27:07 PM PST 24 Feb 28 04:27:08 PM PST 24 52251266 ps
T910 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.40126591 Feb 28 04:27:14 PM PST 24 Feb 28 04:27:16 PM PST 24 88018992 ps
T911 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2764509448 Feb 28 04:26:53 PM PST 24 Feb 28 04:26:54 PM PST 24 163858011 ps
T912 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1814483893 Feb 28 04:27:02 PM PST 24 Feb 28 04:27:03 PM PST 24 19737179 ps
T913 /workspace/coverage/cover_reg_top/45.edn_intr_test.608330990 Feb 28 04:27:22 PM PST 24 Feb 28 04:27:23 PM PST 24 26683634 ps
T914 /workspace/coverage/cover_reg_top/36.edn_intr_test.4163261126 Feb 28 04:27:22 PM PST 24 Feb 28 04:27:23 PM PST 24 116194367 ps
T915 /workspace/coverage/cover_reg_top/17.edn_intr_test.98312772 Feb 28 04:27:15 PM PST 24 Feb 28 04:27:16 PM PST 24 13479666 ps
T916 /workspace/coverage/cover_reg_top/32.edn_intr_test.3775438579 Feb 28 04:27:17 PM PST 24 Feb 28 04:27:18 PM PST 24 32345496 ps
T917 /workspace/coverage/cover_reg_top/37.edn_intr_test.2382625342 Feb 28 04:27:23 PM PST 24 Feb 28 04:27:25 PM PST 24 27158343 ps
T918 /workspace/coverage/cover_reg_top/9.edn_intr_test.2476971720 Feb 28 04:26:59 PM PST 24 Feb 28 04:27:00 PM PST 24 25858312 ps
T919 /workspace/coverage/cover_reg_top/8.edn_csr_rw.3672649515 Feb 28 04:27:00 PM PST 24 Feb 28 04:27:01 PM PST 24 23600092 ps
T217 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2433447501 Feb 28 04:26:34 PM PST 24 Feb 28 04:26:37 PM PST 24 50166058 ps
T920 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1949812530 Feb 28 04:26:44 PM PST 24 Feb 28 04:26:47 PM PST 24 79848918 ps
T215 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2159478810 Feb 28 04:27:09 PM PST 24 Feb 28 04:27:10 PM PST 24 15063037 ps
T921 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2053613048 Feb 28 04:26:33 PM PST 24 Feb 28 04:26:35 PM PST 24 80811767 ps
T922 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1840454715 Feb 28 04:27:08 PM PST 24 Feb 28 04:27:09 PM PST 24 48381124 ps
T923 /workspace/coverage/cover_reg_top/3.edn_intr_test.3364868418 Feb 28 04:26:44 PM PST 24 Feb 28 04:26:45 PM PST 24 23475312 ps
T924 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3934377249 Feb 28 04:27:15 PM PST 24 Feb 28 04:27:16 PM PST 24 63551961 ps
T925 /workspace/coverage/cover_reg_top/40.edn_intr_test.11456736 Feb 28 04:27:21 PM PST 24 Feb 28 04:27:22 PM PST 24 30563743 ps
T926 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1697685876 Feb 28 04:26:37 PM PST 24 Feb 28 04:26:39 PM PST 24 15939373 ps
T927 /workspace/coverage/cover_reg_top/42.edn_intr_test.3968728347 Feb 28 04:27:20 PM PST 24 Feb 28 04:27:21 PM PST 24 16788602 ps
T216 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2797886300 Feb 28 04:26:33 PM PST 24 Feb 28 04:26:35 PM PST 24 50941266 ps
T219 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2616032820 Feb 28 04:26:59 PM PST 24 Feb 28 04:27:00 PM PST 24 12318997 ps
T928 /workspace/coverage/cover_reg_top/38.edn_intr_test.2455559786 Feb 28 04:27:22 PM PST 24 Feb 28 04:27:23 PM PST 24 38003172 ps
T929 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2391019217 Feb 28 04:26:46 PM PST 24 Feb 28 04:26:48 PM PST 24 211114416 ps
T218 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.589754464 Feb 28 04:26:46 PM PST 24 Feb 28 04:26:48 PM PST 24 20540301 ps
T930 /workspace/coverage/cover_reg_top/4.edn_intr_test.52385866 Feb 28 04:26:46 PM PST 24 Feb 28 04:26:47 PM PST 24 21314171 ps
T931 /workspace/coverage/cover_reg_top/49.edn_intr_test.1829892335 Feb 28 04:27:20 PM PST 24 Feb 28 04:27:21 PM PST 24 15413066 ps
T932 /workspace/coverage/cover_reg_top/14.edn_intr_test.4213888078 Feb 28 04:27:10 PM PST 24 Feb 28 04:27:11 PM PST 24 69229692 ps
T933 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1239304879 Feb 28 04:27:08 PM PST 24 Feb 28 04:27:11 PM PST 24 76264076 ps
T934 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.954548457 Feb 28 04:26:35 PM PST 24 Feb 28 04:26:37 PM PST 24 134500381 ps
T935 /workspace/coverage/cover_reg_top/23.edn_intr_test.4240613136 Feb 28 04:27:17 PM PST 24 Feb 28 04:27:18 PM PST 24 19335293 ps
T936 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3497689752 Feb 28 04:27:14 PM PST 24 Feb 28 04:27:15 PM PST 24 27854787 ps
T937 /workspace/coverage/cover_reg_top/19.edn_intr_test.3549940721 Feb 28 04:27:15 PM PST 24 Feb 28 04:27:16 PM PST 24 56256808 ps
T938 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2106407287 Feb 28 04:26:38 PM PST 24 Feb 28 04:26:43 PM PST 24 923172036 ps
T939 /workspace/coverage/cover_reg_top/11.edn_intr_test.4104454314 Feb 28 04:27:05 PM PST 24 Feb 28 04:27:06 PM PST 24 20625270 ps
T940 /workspace/coverage/cover_reg_top/1.edn_intr_test.2022909611 Feb 28 04:26:34 PM PST 24 Feb 28 04:26:37 PM PST 24 22547741 ps
T941 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1844090141 Feb 28 04:26:57 PM PST 24 Feb 28 04:26:59 PM PST 24 161981757 ps
T220 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.826559393 Feb 28 04:26:34 PM PST 24 Feb 28 04:26:39 PM PST 24 257612706 ps
T942 /workspace/coverage/cover_reg_top/28.edn_intr_test.3108014592 Feb 28 04:27:18 PM PST 24 Feb 28 04:27:19 PM PST 24 14166334 ps
T943 /workspace/coverage/cover_reg_top/5.edn_csr_rw.3621487757 Feb 28 04:26:51 PM PST 24 Feb 28 04:26:53 PM PST 24 17203705 ps
T944 /workspace/coverage/cover_reg_top/35.edn_intr_test.2202802562 Feb 28 04:27:21 PM PST 24 Feb 28 04:27:22 PM PST 24 46754357 ps
T945 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1348003381 Feb 28 04:26:58 PM PST 24 Feb 28 04:27:02 PM PST 24 108214209 ps
T946 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1369718040 Feb 28 04:26:42 PM PST 24 Feb 28 04:26:44 PM PST 24 291102256 ps
T947 /workspace/coverage/cover_reg_top/8.edn_intr_test.4089900102 Feb 28 04:26:55 PM PST 24 Feb 28 04:26:56 PM PST 24 15476694 ps
T948 /workspace/coverage/cover_reg_top/10.edn_intr_test.3489430129 Feb 28 04:27:04 PM PST 24 Feb 28 04:27:05 PM PST 24 11849043 ps
T949 /workspace/coverage/cover_reg_top/20.edn_intr_test.3614866864 Feb 28 04:27:18 PM PST 24 Feb 28 04:27:19 PM PST 24 16616649 ps
T950 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3761139188 Feb 28 04:26:44 PM PST 24 Feb 28 04:26:46 PM PST 24 43038323 ps
T951 /workspace/coverage/cover_reg_top/22.edn_intr_test.2547750570 Feb 28 04:27:18 PM PST 24 Feb 28 04:27:19 PM PST 24 90749972 ps
T952 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1975463036 Feb 28 04:27:01 PM PST 24 Feb 28 04:27:02 PM PST 24 45876829 ps
T953 /workspace/coverage/cover_reg_top/7.edn_intr_test.3880291119 Feb 28 04:26:55 PM PST 24 Feb 28 04:26:56 PM PST 24 28372254 ps
T954 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.701737713 Feb 28 04:26:50 PM PST 24 Feb 28 04:26:51 PM PST 24 85660732 ps
T955 /workspace/coverage/cover_reg_top/26.edn_intr_test.4007249345 Feb 28 04:27:17 PM PST 24 Feb 28 04:27:18 PM PST 24 30024998 ps
T956 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2321375034 Feb 28 04:27:09 PM PST 24 Feb 28 04:27:10 PM PST 24 104627128 ps
T957 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.4247756062 Feb 28 04:27:03 PM PST 24 Feb 28 04:27:04 PM PST 24 70127425 ps
T958 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.908063092 Feb 28 04:27:03 PM PST 24 Feb 28 04:27:05 PM PST 24 132544972 ps
T959 /workspace/coverage/cover_reg_top/6.edn_csr_rw.3695631466 Feb 28 04:26:50 PM PST 24 Feb 28 04:26:51 PM PST 24 15125378 ps
T960 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2850798684 Feb 28 04:27:00 PM PST 24 Feb 28 04:27:03 PM PST 24 96488163 ps
T961 /workspace/coverage/cover_reg_top/46.edn_intr_test.16651127 Feb 28 04:27:24 PM PST 24 Feb 28 04:27:25 PM PST 24 56816679 ps
T962 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2116620784 Feb 28 04:26:45 PM PST 24 Feb 28 04:26:47 PM PST 24 99876818 ps
T221 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.4028480279 Feb 28 04:26:31 PM PST 24 Feb 28 04:26:33 PM PST 24 63342883 ps
T963 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.826702922 Feb 28 04:26:44 PM PST 24 Feb 28 04:26:46 PM PST 24 159726054 ps
T964 /workspace/coverage/cover_reg_top/5.edn_intr_test.3395649712 Feb 28 04:26:53 PM PST 24 Feb 28 04:26:54 PM PST 24 22994878 ps
T965 /workspace/coverage/cover_reg_top/13.edn_csr_rw.2605244535 Feb 28 04:27:09 PM PST 24 Feb 28 04:27:10 PM PST 24 108730046 ps
T966 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3593169138 Feb 28 04:26:32 PM PST 24 Feb 28 04:26:36 PM PST 24 233242309 ps
T967 /workspace/coverage/cover_reg_top/44.edn_intr_test.376219050 Feb 28 04:27:25 PM PST 24 Feb 28 04:27:26 PM PST 24 24992263 ps
T968 /workspace/coverage/cover_reg_top/39.edn_intr_test.3097650667 Feb 28 04:27:24 PM PST 24 Feb 28 04:27:25 PM PST 24 12446445 ps
T969 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2917666526 Feb 28 04:26:55 PM PST 24 Feb 28 04:26:56 PM PST 24 17812936 ps
T970 /workspace/coverage/cover_reg_top/13.edn_tl_errors.4133017538 Feb 28 04:27:09 PM PST 24 Feb 28 04:27:11 PM PST 24 94631481 ps

Test location /workspace/coverage/default/7.edn_genbits.736782605
Short name T1
Test name
Test status
Simulation time 116012233 ps
CPU time 1.46 seconds
Started Feb 28 06:00:13 PM PST 24
Finished Feb 28 06:00:14 PM PST 24
Peak memory 217448 kb
Host smart-dd2b9562-0f7f-455f-9f6f-b1a96d8eb5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736782605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.736782605
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.898288606
Short name T25
Test name
Test status
Simulation time 131237387850 ps
CPU time 1157.45 seconds
Started Feb 28 06:02:05 PM PST 24
Finished Feb 28 06:21:23 PM PST 24
Peak memory 221664 kb
Host smart-e5c8f26a-2859-4a16-873d-78e0403c1948
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898288606 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.898288606
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/105.edn_genbits.1690606130
Short name T33
Test name
Test status
Simulation time 161528375 ps
CPU time 3.23 seconds
Started Feb 28 06:02:25 PM PST 24
Finished Feb 28 06:02:28 PM PST 24
Peak memory 219088 kb
Host smart-4c0125bc-e6b3-4975-a5b5-b2fd851a4497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690606130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1690606130
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.1106571764
Short name T4
Test name
Test status
Simulation time 18960005 ps
CPU time 1.11 seconds
Started Feb 28 06:02:10 PM PST 24
Finished Feb 28 06:02:13 PM PST 24
Peak memory 222392 kb
Host smart-cc5c2bfc-88de-4f53-8bb9-ba302aadd022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106571764 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1106571764
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3334792347
Short name T19
Test name
Test status
Simulation time 371951288 ps
CPU time 3.52 seconds
Started Feb 28 06:00:08 PM PST 24
Finished Feb 28 06:00:12 PM PST 24
Peak memory 233652 kb
Host smart-7f15f7e7-a92c-46c8-b7ab-2464a5f02146
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334792347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3334792347
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/33.edn_alert.3133859978
Short name T17
Test name
Test status
Simulation time 94617571 ps
CPU time 1.34 seconds
Started Feb 28 06:01:27 PM PST 24
Finished Feb 28 06:01:29 PM PST 24
Peak memory 215012 kb
Host smart-11c210a9-fe9c-4822-a9d0-25bc1dd6f33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133859978 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3133859978
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable.2162848200
Short name T605
Test name
Test status
Simulation time 31066142 ps
CPU time 0.85 seconds
Started Feb 28 06:00:38 PM PST 24
Finished Feb 28 06:00:39 PM PST 24
Peak memory 215216 kb
Host smart-0c27027d-2e45-45be-ad19-f74ea5936835
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162848200 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2162848200
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/0.edn_regwen.2102691572
Short name T45
Test name
Test status
Simulation time 47323975 ps
CPU time 0.9 seconds
Started Feb 28 05:59:45 PM PST 24
Finished Feb 28 05:59:46 PM PST 24
Peak memory 206496 kb
Host smart-7682f7a3-36ff-4331-9a15-1431c1ea3e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102691572 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2102691572
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.630832097
Short name T39
Test name
Test status
Simulation time 30408996 ps
CPU time 0.96 seconds
Started Feb 28 06:01:19 PM PST 24
Finished Feb 28 06:01:20 PM PST 24
Peak memory 216888 kb
Host smart-36b438f4-cb09-4d43-a7e3-48e6c9151ea3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630832097 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.630832097
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_alert.3694632880
Short name T128
Test name
Test status
Simulation time 49946051 ps
CPU time 1.17 seconds
Started Feb 28 06:01:54 PM PST 24
Finished Feb 28 06:01:55 PM PST 24
Peak memory 215040 kb
Host smart-2353cf49-f26c-4e84-a116-7eaec793649f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694632880 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3694632880
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/14.edn_intr.1308734853
Short name T137
Test name
Test status
Simulation time 34776649 ps
CPU time 0.88 seconds
Started Feb 28 06:00:41 PM PST 24
Finished Feb 28 06:00:42 PM PST 24
Peak memory 214940 kb
Host smart-28863d7d-c594-4e65-ae99-419e2c21dae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308734853 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1308734853
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2372508589
Short name T226
Test name
Test status
Simulation time 254579537 ps
CPU time 1.96 seconds
Started Feb 28 04:37:08 PM PST 24
Finished Feb 28 04:37:10 PM PST 24
Peak memory 205644 kb
Host smart-12c7b4af-66a6-4996-b8ac-8f2ab74fa800
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372508589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2372508589
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2996687665
Short name T200
Test name
Test status
Simulation time 33644307 ps
CPU time 0.82 seconds
Started Feb 28 04:26:42 PM PST 24
Finished Feb 28 04:26:43 PM PST 24
Peak memory 205844 kb
Host smart-64d2c825-76a1-429b-8d27-53f0fea84000
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996687665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2996687665
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1717093819
Short name T83
Test name
Test status
Simulation time 92011249 ps
CPU time 1.04 seconds
Started Feb 28 06:01:07 PM PST 24
Finished Feb 28 06:01:08 PM PST 24
Peak memory 217224 kb
Host smart-1fa71624-f829-4462-81e4-8fb28f06b87f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717093819 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1717093819
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_alert.2201962732
Short name T179
Test name
Test status
Simulation time 103530474 ps
CPU time 1.28 seconds
Started Feb 28 06:00:54 PM PST 24
Finished Feb 28 06:00:56 PM PST 24
Peak memory 215016 kb
Host smart-1ed117cc-a85f-418e-8dc8-ed45fee3ec54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201962732 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2201962732
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert.1104753054
Short name T11
Test name
Test status
Simulation time 28303773 ps
CPU time 1.2 seconds
Started Feb 28 05:59:53 PM PST 24
Finished Feb 28 05:59:54 PM PST 24
Peak memory 215108 kb
Host smart-2671f3f0-16c5-4863-bcc6-daec0bf0b1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104753054 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1104753054
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable.35963342
Short name T169
Test name
Test status
Simulation time 37124562 ps
CPU time 0.88 seconds
Started Feb 28 06:00:30 PM PST 24
Finished Feb 28 06:00:31 PM PST 24
Peak memory 215080 kb
Host smart-e31c86d5-979e-48c5-b373-b5eed9d64dbc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35963342 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.35963342
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable.2170211361
Short name T158
Test name
Test status
Simulation time 11435785 ps
CPU time 0.85 seconds
Started Feb 28 06:01:05 PM PST 24
Finished Feb 28 06:01:07 PM PST 24
Peak memory 215104 kb
Host smart-269dc4ee-3e6d-4d1d-ba46-be100795480c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170211361 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2170211361
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1146614903
Short name T87
Test name
Test status
Simulation time 49169854 ps
CPU time 1.16 seconds
Started Feb 28 05:59:49 PM PST 24
Finished Feb 28 05:59:51 PM PST 24
Peak memory 215808 kb
Host smart-ecce2529-c4c1-401e-9fa1-f8fcdadeef36
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146614903 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1146614903
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.383832503
Short name T74
Test name
Test status
Simulation time 56700787 ps
CPU time 1.14 seconds
Started Feb 28 06:00:27 PM PST 24
Finished Feb 28 06:00:29 PM PST 24
Peak memory 215804 kb
Host smart-7c4e82b3-884a-4d8c-8084-7fce5c3ac4e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383832503 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.383832503
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_disable.4269068121
Short name T166
Test name
Test status
Simulation time 122017460 ps
CPU time 0.84 seconds
Started Feb 28 06:00:58 PM PST 24
Finished Feb 28 06:00:59 PM PST 24
Peak memory 215068 kb
Host smart-4370cd9a-c9b5-4aa6-bb41-6acd02ae0c64
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269068121 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.4269068121
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/1.edn_intr.425844477
Short name T141
Test name
Test status
Simulation time 35914856 ps
CPU time 0.84 seconds
Started Feb 28 05:59:53 PM PST 24
Finished Feb 28 05:59:53 PM PST 24
Peak memory 215016 kb
Host smart-82f8e7b1-1ad9-4bed-b03e-feaf4d121d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425844477 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.425844477
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_disable.3196161629
Short name T97
Test name
Test status
Simulation time 22134540 ps
CPU time 0.89 seconds
Started Feb 28 05:59:55 PM PST 24
Finished Feb 28 05:59:56 PM PST 24
Peak memory 214844 kb
Host smart-feb6f5d1-585a-4c0d-b564-26fe02039500
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196161629 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3196161629
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/10.edn_alert.4078803568
Short name T635
Test name
Test status
Simulation time 106809756 ps
CPU time 1.18 seconds
Started Feb 28 06:00:31 PM PST 24
Finished Feb 28 06:00:33 PM PST 24
Peak memory 215032 kb
Host smart-873debbb-0e78-4fe3-9475-341ee9a2ac73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078803568 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.4078803568
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3720254225
Short name T26
Test name
Test status
Simulation time 55391704624 ps
CPU time 768.45 seconds
Started Feb 28 06:00:47 PM PST 24
Finished Feb 28 06:13:36 PM PST 24
Peak memory 219268 kb
Host smart-6bed3f16-4089-4b08-8506-b5041750e7e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720254225 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3720254225
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_disable.2160460493
Short name T173
Test name
Test status
Simulation time 38003672 ps
CPU time 0.85 seconds
Started Feb 28 06:01:00 PM PST 24
Finished Feb 28 06:01:01 PM PST 24
Peak memory 215244 kb
Host smart-53786825-5d6f-4af4-bcad-462115d97bc0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160460493 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2160460493
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/198.edn_genbits.105652142
Short name T186
Test name
Test status
Simulation time 70340836 ps
CPU time 1.1 seconds
Started Feb 28 06:02:42 PM PST 24
Finished Feb 28 06:02:43 PM PST 24
Peak memory 216120 kb
Host smart-8e247a10-a28b-4f7c-ba5b-6b52a49e4abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105652142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.105652142
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_disable.4278867460
Short name T171
Test name
Test status
Simulation time 14042443 ps
CPU time 0.91 seconds
Started Feb 28 06:01:52 PM PST 24
Finished Feb 28 06:01:53 PM PST 24
Peak memory 215308 kb
Host smart-aa982620-b5e9-436b-be97-dbccf5c044a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278867460 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.4278867460
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.1163033670
Short name T6
Test name
Test status
Simulation time 29960644 ps
CPU time 1.26 seconds
Started Feb 28 06:00:49 PM PST 24
Finished Feb 28 06:00:50 PM PST 24
Peak memory 218440 kb
Host smart-c1dc0d99-7649-4d18-9ca3-9f2616b46621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163033670 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1163033670
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2940201699
Short name T286
Test name
Test status
Simulation time 57120573 ps
CPU time 1.82 seconds
Started Feb 28 06:02:04 PM PST 24
Finished Feb 28 06:02:07 PM PST 24
Peak memory 218296 kb
Host smart-34865a2f-ce0f-47ae-ba52-73b377cab9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940201699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2940201699
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1964081725
Short name T77
Test name
Test status
Simulation time 55340942 ps
CPU time 1.18 seconds
Started Feb 28 06:00:44 PM PST 24
Finished Feb 28 06:00:45 PM PST 24
Peak memory 215796 kb
Host smart-0b5342f2-c9ae-453b-90d7-7383309fe9ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964081725 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1964081725
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.3017902966
Short name T681
Test name
Test status
Simulation time 60740304 ps
CPU time 1.13 seconds
Started Feb 28 06:00:46 PM PST 24
Finished Feb 28 06:00:48 PM PST 24
Peak memory 215808 kb
Host smart-17c2a9c4-6f19-4fea-ad97-b000aa201f4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017902966 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.3017902966
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_disable.3697767788
Short name T818
Test name
Test status
Simulation time 43391557 ps
CPU time 0.82 seconds
Started Feb 28 06:01:10 PM PST 24
Finished Feb 28 06:01:11 PM PST 24
Peak memory 215116 kb
Host smart-94b2878a-231a-44ae-8947-5d8a2762c1ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697767788 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3697767788
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable.508183210
Short name T56
Test name
Test status
Simulation time 39167344 ps
CPU time 0.85 seconds
Started Feb 28 06:01:25 PM PST 24
Finished Feb 28 06:01:26 PM PST 24
Peak memory 215052 kb
Host smart-107ba700-d4a3-4121-93fa-c433efa4dd54
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508183210 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.508183210
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/11.edn_alert_test.10973993
Short name T297
Test name
Test status
Simulation time 51925014 ps
CPU time 0.93 seconds
Started Feb 28 06:00:32 PM PST 24
Finished Feb 28 06:00:33 PM PST 24
Peak memory 206228 kb
Host smart-69ed36d4-e810-4fbb-a642-53a135c4a154
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10973993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.10973993
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_regwen.3091860860
Short name T130
Test name
Test status
Simulation time 18733023 ps
CPU time 0.99 seconds
Started Feb 28 05:59:51 PM PST 24
Finished Feb 28 05:59:52 PM PST 24
Peak memory 206460 kb
Host smart-4a127cec-3004-4e49-b799-f71c09ec9a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091860860 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3091860860
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_stress_all.4060940308
Short name T253
Test name
Test status
Simulation time 239864179 ps
CPU time 4.61 seconds
Started Feb 28 05:59:52 PM PST 24
Finished Feb 28 05:59:57 PM PST 24
Peak memory 215684 kb
Host smart-404f696d-61a2-404c-a660-7edd59a20547
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060940308 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.4060940308
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/103.edn_genbits.3442533756
Short name T276
Test name
Test status
Simulation time 124324751 ps
CPU time 1.2 seconds
Started Feb 28 06:02:23 PM PST 24
Finished Feb 28 06:02:25 PM PST 24
Peak memory 218360 kb
Host smart-4e429c4b-293c-4caf-9ef8-e77219e9ddda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442533756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3442533756
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.3248533610
Short name T30
Test name
Test status
Simulation time 49745038 ps
CPU time 1.49 seconds
Started Feb 28 06:02:26 PM PST 24
Finished Feb 28 06:02:27 PM PST 24
Peak memory 217104 kb
Host smart-8bb2ad17-34d9-4673-afa0-3356b3fd85a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248533610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3248533610
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1913308646
Short name T230
Test name
Test status
Simulation time 61327228 ps
CPU time 1.14 seconds
Started Feb 28 06:00:45 PM PST 24
Finished Feb 28 06:00:47 PM PST 24
Peak memory 214980 kb
Host smart-a0906695-329f-4328-a9cd-be71945fd1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913308646 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1913308646
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.4059040414
Short name T311
Test name
Test status
Simulation time 118929148 ps
CPU time 1.22 seconds
Started Feb 28 06:02:37 PM PST 24
Finished Feb 28 06:02:39 PM PST 24
Peak memory 217372 kb
Host smart-40eafca1-9bda-403d-a021-39dd115bfdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059040414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.4059040414
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.4011493951
Short name T245
Test name
Test status
Simulation time 26308322 ps
CPU time 0.96 seconds
Started Feb 28 05:59:55 PM PST 24
Finished Feb 28 05:59:57 PM PST 24
Peak memory 206504 kb
Host smart-c5d50c79-0870-44d4-89d3-27319c67c7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011493951 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.4011493951
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/18.edn_intr.1869682097
Short name T807
Test name
Test status
Simulation time 35968653 ps
CPU time 0.86 seconds
Started Feb 28 06:00:48 PM PST 24
Finished Feb 28 06:00:49 PM PST 24
Peak memory 214944 kb
Host smart-4f78305c-190c-40b3-ab78-86e01d064528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869682097 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1869682097
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2797886300
Short name T216
Test name
Test status
Simulation time 50941266 ps
CPU time 1.17 seconds
Started Feb 28 04:26:33 PM PST 24
Finished Feb 28 04:26:35 PM PST 24
Peak memory 205840 kb
Host smart-8bf6b21c-685c-441e-a26b-1f51dbcd0c06
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797886300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2797886300
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/default/106.edn_genbits.3765530663
Short name T598
Test name
Test status
Simulation time 38933568 ps
CPU time 1.36 seconds
Started Feb 28 06:02:24 PM PST 24
Finished Feb 28 06:02:25 PM PST 24
Peak memory 218284 kb
Host smart-5baa7e3e-2cac-4042-882c-bdee9059bb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765530663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3765530663
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_genbits.3098140145
Short name T279
Test name
Test status
Simulation time 61963071 ps
CPU time 1.45 seconds
Started Feb 28 06:00:28 PM PST 24
Finished Feb 28 06:00:30 PM PST 24
Peak memory 217340 kb
Host smart-7f57e05d-a4a2-40fd-b882-c6103c4c87d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098140145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3098140145
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.1221272166
Short name T272
Test name
Test status
Simulation time 258065456 ps
CPU time 3.46 seconds
Started Feb 28 06:02:27 PM PST 24
Finished Feb 28 06:02:31 PM PST 24
Peak memory 216256 kb
Host smart-e37b6516-1f1c-4951-8dfe-5747bca4e718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221272166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1221272166
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.1728263749
Short name T264
Test name
Test status
Simulation time 101767143 ps
CPU time 1.51 seconds
Started Feb 28 06:02:28 PM PST 24
Finished Feb 28 06:02:30 PM PST 24
Peak memory 217400 kb
Host smart-4cdee523-22d6-449c-aa5d-2fa60072e5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728263749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1728263749
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_genbits.952329099
Short name T719
Test name
Test status
Simulation time 95630636 ps
CPU time 1.41 seconds
Started Feb 28 06:00:34 PM PST 24
Finished Feb 28 06:00:35 PM PST 24
Peak memory 217324 kb
Host smart-88da571e-630d-4b68-a289-c8cc1243613f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952329099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.952329099
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.339902467
Short name T270
Test name
Test status
Simulation time 45077092 ps
CPU time 1.95 seconds
Started Feb 28 06:02:33 PM PST 24
Finished Feb 28 06:02:36 PM PST 24
Peak memory 217208 kb
Host smart-2dccf131-3a31-4877-8314-d98953f1db48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339902467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.339902467
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_genbits.1613769189
Short name T266
Test name
Test status
Simulation time 44131634 ps
CPU time 1.62 seconds
Started Feb 28 06:00:46 PM PST 24
Finished Feb 28 06:00:48 PM PST 24
Peak memory 218384 kb
Host smart-6aea0e0f-0b6c-47cc-98b2-292bd2b68a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613769189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1613769189
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.4111724071
Short name T614
Test name
Test status
Simulation time 257376601090 ps
CPU time 2375 seconds
Started Feb 28 06:00:47 PM PST 24
Finished Feb 28 06:40:23 PM PST 24
Peak memory 227540 kb
Host smart-63fe581b-92a3-43c9-9d2a-134b70e750e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111724071 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.4111724071
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/199.edn_genbits.3567889018
Short name T262
Test name
Test status
Simulation time 77691580 ps
CPU time 1.31 seconds
Started Feb 28 06:02:41 PM PST 24
Finished Feb 28 06:02:42 PM PST 24
Peak memory 218440 kb
Host smart-450fe943-abdf-4893-860f-ccb87eeee209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567889018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3567889018
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.548657912
Short name T274
Test name
Test status
Simulation time 78188830 ps
CPU time 1.43 seconds
Started Feb 28 06:03:04 PM PST 24
Finished Feb 28 06:03:06 PM PST 24
Peak memory 217360 kb
Host smart-54dda9a9-0cd8-45bf-ad93-a0b3244c993f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548657912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.548657912
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_regwen.4259133042
Short name T242
Test name
Test status
Simulation time 15858087 ps
CPU time 0.99 seconds
Started Feb 28 06:00:00 PM PST 24
Finished Feb 28 06:00:01 PM PST 24
Peak memory 206492 kb
Host smart-a4f17bf0-cc25-4c46-9b78-4eec9858f81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259133042 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.4259133042
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/37.edn_alert.1673687295
Short name T41
Test name
Test status
Simulation time 121602811 ps
CPU time 1.16 seconds
Started Feb 28 06:01:34 PM PST 24
Finished Feb 28 06:01:35 PM PST 24
Peak memory 215072 kb
Host smart-1f8767ee-ecee-4c9e-9337-48da5079e362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673687295 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1673687295
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/8.edn_regwen.3665731563
Short name T250
Test name
Test status
Simulation time 61515322 ps
CPU time 0.91 seconds
Started Feb 28 06:00:23 PM PST 24
Finished Feb 28 06:00:24 PM PST 24
Peak memory 206536 kb
Host smart-2bd8262b-c2b2-47f6-8390-6d77d8012ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665731563 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3665731563
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_intr.1840037926
Short name T135
Test name
Test status
Simulation time 27239159 ps
CPU time 0.94 seconds
Started Feb 28 06:00:25 PM PST 24
Finished Feb 28 06:00:26 PM PST 24
Peak memory 215188 kb
Host smart-cc77ae6f-4dfb-4dcf-8b0a-ba8f067be59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840037926 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1840037926
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/111.edn_genbits.3351572834
Short name T401
Test name
Test status
Simulation time 46978481 ps
CPU time 1.52 seconds
Started Feb 28 06:02:25 PM PST 24
Finished Feb 28 06:02:27 PM PST 24
Peak memory 216304 kb
Host smart-15d53817-b60e-4dfd-a874-6d2d1453e47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351572834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3351572834
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_genbits.3772388936
Short name T645
Test name
Test status
Simulation time 162423338 ps
CPU time 1.75 seconds
Started Feb 28 06:02:12 PM PST 24
Finished Feb 28 06:02:15 PM PST 24
Peak memory 217392 kb
Host smart-466c5e3b-4c76-49c4-ab4b-eb7ea91dace8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772388936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3772388936
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1215228994
Short name T214
Test name
Test status
Simulation time 41991384 ps
CPU time 1.22 seconds
Started Feb 28 04:26:36 PM PST 24
Finished Feb 28 04:26:37 PM PST 24
Peak memory 205920 kb
Host smart-1324e943-88e1-44df-b034-bb47f4d3aa1a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215228994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1215228994
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3593169138
Short name T966
Test name
Test status
Simulation time 233242309 ps
CPU time 3.07 seconds
Started Feb 28 04:26:32 PM PST 24
Finished Feb 28 04:26:36 PM PST 24
Peak memory 205868 kb
Host smart-ddc6c0ff-64ea-4692-baa2-318ed1944a85
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593169138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3593169138
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.4028480279
Short name T221
Test name
Test status
Simulation time 63342883 ps
CPU time 0.93 seconds
Started Feb 28 04:26:31 PM PST 24
Finished Feb 28 04:26:33 PM PST 24
Peak memory 205788 kb
Host smart-a466f304-55d4-4e7e-8fbf-ba992928f0c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028480279 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.4028480279
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2822256906
Short name T901
Test name
Test status
Simulation time 28188652 ps
CPU time 1 seconds
Started Feb 28 04:26:34 PM PST 24
Finished Feb 28 04:26:36 PM PST 24
Peak memory 214072 kb
Host smart-727e29ad-816d-46c3-ad4f-4b345f876c4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822256906 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2822256906
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1626915067
Short name T210
Test name
Test status
Simulation time 24134994 ps
CPU time 0.8 seconds
Started Feb 28 04:26:32 PM PST 24
Finished Feb 28 04:26:34 PM PST 24
Peak memory 205760 kb
Host smart-dea92bcd-1b85-4a59-bac1-65a6e0b75a8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626915067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1626915067
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3145769002
Short name T883
Test name
Test status
Simulation time 35427711 ps
CPU time 0.76 seconds
Started Feb 28 04:26:29 PM PST 24
Finished Feb 28 04:26:32 PM PST 24
Peak memory 205680 kb
Host smart-c96397a9-9535-4ee9-b895-012ba55a850d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145769002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3145769002
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.250946693
Short name T906
Test name
Test status
Simulation time 26699459 ps
CPU time 1.21 seconds
Started Feb 28 04:26:32 PM PST 24
Finished Feb 28 04:26:34 PM PST 24
Peak memory 205860 kb
Host smart-fe04dd30-e79c-4f02-8cb7-1acc03a4114e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250946693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.250946693
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.35387619
Short name T853
Test name
Test status
Simulation time 50728958 ps
CPU time 1.85 seconds
Started Feb 28 04:26:31 PM PST 24
Finished Feb 28 04:26:34 PM PST 24
Peak memory 214024 kb
Host smart-2689465a-192c-4c96-b264-73d9cbd38d88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35387619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.35387619
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3938401883
Short name T908
Test name
Test status
Simulation time 76510911 ps
CPU time 2.21 seconds
Started Feb 28 04:26:30 PM PST 24
Finished Feb 28 04:26:33 PM PST 24
Peak memory 205960 kb
Host smart-fe0c456e-cdcd-44ef-9649-0351365ff5bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938401883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3938401883
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.826559393
Short name T220
Test name
Test status
Simulation time 257612706 ps
CPU time 3.36 seconds
Started Feb 28 04:26:34 PM PST 24
Finished Feb 28 04:26:39 PM PST 24
Peak memory 205820 kb
Host smart-3380fd8b-9f78-42b1-8deb-f1432ff4e2a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826559393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.826559393
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2362704709
Short name T899
Test name
Test status
Simulation time 30692750 ps
CPU time 0.89 seconds
Started Feb 28 04:26:34 PM PST 24
Finished Feb 28 04:26:36 PM PST 24
Peak memory 205760 kb
Host smart-72f91d3f-805c-41cc-a66c-cce35818a355
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362704709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2362704709
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3294382378
Short name T843
Test name
Test status
Simulation time 89520932 ps
CPU time 1.61 seconds
Started Feb 28 04:26:39 PM PST 24
Finished Feb 28 04:26:42 PM PST 24
Peak memory 214088 kb
Host smart-56923fa3-8766-4ac3-85f2-15f546701e6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294382378 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3294382378
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2433447501
Short name T217
Test name
Test status
Simulation time 50166058 ps
CPU time 0.77 seconds
Started Feb 28 04:26:34 PM PST 24
Finished Feb 28 04:26:37 PM PST 24
Peak memory 205784 kb
Host smart-b0deb435-c60c-4e82-b955-d320e59ec715
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433447501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2433447501
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2022909611
Short name T940
Test name
Test status
Simulation time 22547741 ps
CPU time 0.8 seconds
Started Feb 28 04:26:34 PM PST 24
Finished Feb 28 04:26:37 PM PST 24
Peak memory 205820 kb
Host smart-d0d5cfbe-3f4d-4c9f-ab1f-aa1e1be4c218
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022909611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2022909611
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.954548457
Short name T934
Test name
Test status
Simulation time 134500381 ps
CPU time 0.98 seconds
Started Feb 28 04:26:35 PM PST 24
Finished Feb 28 04:26:37 PM PST 24
Peak memory 205868 kb
Host smart-961894b2-0691-4794-ac8f-04d721244fac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954548457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.954548457
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3072389299
Short name T878
Test name
Test status
Simulation time 51839582 ps
CPU time 3.23 seconds
Started Feb 28 04:26:34 PM PST 24
Finished Feb 28 04:26:39 PM PST 24
Peak memory 214048 kb
Host smart-4d0d9493-535a-4a15-9d4b-021c94d81d01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072389299 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3072389299
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2053613048
Short name T921
Test name
Test status
Simulation time 80811767 ps
CPU time 1.43 seconds
Started Feb 28 04:26:33 PM PST 24
Finished Feb 28 04:26:35 PM PST 24
Peak memory 205820 kb
Host smart-c3405514-5b92-4c17-b309-9b1aabcaaca7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053613048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2053613048
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2921008968
Short name T847
Test name
Test status
Simulation time 66203158 ps
CPU time 1.18 seconds
Started Feb 28 04:27:05 PM PST 24
Finished Feb 28 04:27:06 PM PST 24
Peak memory 222416 kb
Host smart-b14b10d6-0b26-4f34-b94a-187738149e7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921008968 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2921008968
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.691486241
Short name T207
Test name
Test status
Simulation time 190503430 ps
CPU time 0.89 seconds
Started Feb 28 04:27:04 PM PST 24
Finished Feb 28 04:27:05 PM PST 24
Peak memory 205784 kb
Host smart-37419a5e-5c76-48cb-9818-26ffae8a5c5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691486241 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.691486241
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3489430129
Short name T948
Test name
Test status
Simulation time 11849043 ps
CPU time 0.84 seconds
Started Feb 28 04:27:04 PM PST 24
Finished Feb 28 04:27:05 PM PST 24
Peak memory 205720 kb
Host smart-ecb74c68-47d4-4b3a-9e92-7bae07d4ef2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489430129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3489430129
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1862122496
Short name T903
Test name
Test status
Simulation time 28963302 ps
CPU time 1.25 seconds
Started Feb 28 04:27:05 PM PST 24
Finished Feb 28 04:27:07 PM PST 24
Peak memory 205804 kb
Host smart-511ad92a-9c2d-4d05-a18d-442d769b9aa8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862122496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1862122496
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2850798684
Short name T960
Test name
Test status
Simulation time 96488163 ps
CPU time 3.18 seconds
Started Feb 28 04:27:00 PM PST 24
Finished Feb 28 04:27:03 PM PST 24
Peak memory 214232 kb
Host smart-423cdd90-fa72-4a59-926b-c324754b5306
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850798684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2850798684
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1766383449
Short name T862
Test name
Test status
Simulation time 98424515 ps
CPU time 1.58 seconds
Started Feb 28 04:26:59 PM PST 24
Finished Feb 28 04:27:00 PM PST 24
Peak memory 205848 kb
Host smart-97142857-51e0-45ac-bd2c-d2c1a2a4e9bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766383449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1766383449
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1161322162
Short name T888
Test name
Test status
Simulation time 60318097 ps
CPU time 1.45 seconds
Started Feb 28 04:27:09 PM PST 24
Finished Feb 28 04:27:10 PM PST 24
Peak memory 214160 kb
Host smart-9b02d93a-564d-4895-a409-b052dd22dcac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161322162 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1161322162
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1814483893
Short name T912
Test name
Test status
Simulation time 19737179 ps
CPU time 0.91 seconds
Started Feb 28 04:27:02 PM PST 24
Finished Feb 28 04:27:03 PM PST 24
Peak memory 205768 kb
Host smart-a5cfb163-2762-46b2-b749-2fb7f8bcc0df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814483893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1814483893
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.4104454314
Short name T939
Test name
Test status
Simulation time 20625270 ps
CPU time 0.8 seconds
Started Feb 28 04:27:05 PM PST 24
Finished Feb 28 04:27:06 PM PST 24
Peak memory 205676 kb
Host smart-eb3e1a64-4ee6-4221-b378-3ef8375216cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104454314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.4104454314
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3512029689
Short name T890
Test name
Test status
Simulation time 16518342 ps
CPU time 1.06 seconds
Started Feb 28 04:27:04 PM PST 24
Finished Feb 28 04:27:05 PM PST 24
Peak memory 205744 kb
Host smart-1d08bff1-c529-4947-9e02-467777422b78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512029689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3512029689
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3770218292
Short name T837
Test name
Test status
Simulation time 119932245 ps
CPU time 4.41 seconds
Started Feb 28 04:27:07 PM PST 24
Finished Feb 28 04:27:12 PM PST 24
Peak memory 214244 kb
Host smart-46d3962f-fcdf-488e-afcf-5e3f70325546
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770218292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3770218292
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.908063092
Short name T958
Test name
Test status
Simulation time 132544972 ps
CPU time 1.84 seconds
Started Feb 28 04:27:03 PM PST 24
Finished Feb 28 04:27:05 PM PST 24
Peak memory 205768 kb
Host smart-1625e263-4bbb-451f-812e-07b4640dbf64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908063092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.908063092
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1840454715
Short name T922
Test name
Test status
Simulation time 48381124 ps
CPU time 1.24 seconds
Started Feb 28 04:27:08 PM PST 24
Finished Feb 28 04:27:09 PM PST 24
Peak memory 214116 kb
Host smart-8fee28d7-0013-46bc-8265-8658a5b45ba0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840454715 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1840454715
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2125290407
Short name T208
Test name
Test status
Simulation time 13191025 ps
CPU time 0.93 seconds
Started Feb 28 04:27:06 PM PST 24
Finished Feb 28 04:27:08 PM PST 24
Peak memory 205908 kb
Host smart-5c690682-223b-4fec-b5cf-3b5c549187d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125290407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2125290407
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3346735470
Short name T848
Test name
Test status
Simulation time 11993680 ps
CPU time 0.84 seconds
Started Feb 28 04:27:05 PM PST 24
Finished Feb 28 04:27:06 PM PST 24
Peak memory 205728 kb
Host smart-c6c734b2-b94c-46e7-9589-3db2d1243dac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346735470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3346735470
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1120308564
Short name T224
Test name
Test status
Simulation time 46930424 ps
CPU time 1.1 seconds
Started Feb 28 04:27:05 PM PST 24
Finished Feb 28 04:27:06 PM PST 24
Peak memory 205864 kb
Host smart-7961a08e-66f6-484c-ad65-dee536c669ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120308564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1120308564
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3970883245
Short name T880
Test name
Test status
Simulation time 141517703 ps
CPU time 4.28 seconds
Started Feb 28 04:27:04 PM PST 24
Finished Feb 28 04:27:09 PM PST 24
Peak memory 214052 kb
Host smart-dd8e7c37-22a1-4656-ba3b-49c050af1093
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970883245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3970883245
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.4247756062
Short name T957
Test name
Test status
Simulation time 70127425 ps
CPU time 1.44 seconds
Started Feb 28 04:27:03 PM PST 24
Finished Feb 28 04:27:04 PM PST 24
Peak memory 205872 kb
Host smart-8ee40bf5-25d6-410e-999e-d61cad751fb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247756062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.4247756062
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1925104363
Short name T909
Test name
Test status
Simulation time 52251266 ps
CPU time 1.77 seconds
Started Feb 28 04:27:07 PM PST 24
Finished Feb 28 04:27:08 PM PST 24
Peak memory 214208 kb
Host smart-0d7b003f-5e9b-467a-ad39-ac40f6a401ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925104363 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1925104363
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2605244535
Short name T965
Test name
Test status
Simulation time 108730046 ps
CPU time 0.75 seconds
Started Feb 28 04:27:09 PM PST 24
Finished Feb 28 04:27:10 PM PST 24
Peak memory 205816 kb
Host smart-1fc28c9b-2f24-41c0-9292-3b846d3824db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605244535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2605244535
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.798601680
Short name T846
Test name
Test status
Simulation time 14184308 ps
CPU time 0.89 seconds
Started Feb 28 04:27:08 PM PST 24
Finished Feb 28 04:27:09 PM PST 24
Peak memory 205768 kb
Host smart-05b63919-2ff6-4000-a9d4-35cfbae24346
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798601680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.798601680
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1835833596
Short name T874
Test name
Test status
Simulation time 52945189 ps
CPU time 1.05 seconds
Started Feb 28 04:27:13 PM PST 24
Finished Feb 28 04:27:14 PM PST 24
Peak memory 205852 kb
Host smart-0c98c50e-3be9-4dd3-a829-874a7bf0349f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835833596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.1835833596
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.4133017538
Short name T970
Test name
Test status
Simulation time 94631481 ps
CPU time 1.86 seconds
Started Feb 28 04:27:09 PM PST 24
Finished Feb 28 04:27:11 PM PST 24
Peak memory 214240 kb
Host smart-b5c43f82-24f2-4d0e-bf03-bff34559cbfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133017538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.4133017538
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1239304879
Short name T933
Test name
Test status
Simulation time 76264076 ps
CPU time 2.22 seconds
Started Feb 28 04:27:08 PM PST 24
Finished Feb 28 04:27:11 PM PST 24
Peak memory 205792 kb
Host smart-f2b457bf-26a8-450f-8728-bedcb5f86637
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239304879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1239304879
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2853062254
Short name T852
Test name
Test status
Simulation time 368899735 ps
CPU time 1.51 seconds
Started Feb 28 04:27:11 PM PST 24
Finished Feb 28 04:27:13 PM PST 24
Peak memory 216940 kb
Host smart-b5fa031a-5425-488f-a720-9be1a5a93647
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853062254 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2853062254
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2159478810
Short name T215
Test name
Test status
Simulation time 15063037 ps
CPU time 0.91 seconds
Started Feb 28 04:27:09 PM PST 24
Finished Feb 28 04:27:10 PM PST 24
Peak memory 205872 kb
Host smart-30fb05be-0f17-4ed8-9e4f-43804b356d30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159478810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2159478810
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.4213888078
Short name T932
Test name
Test status
Simulation time 69229692 ps
CPU time 0.79 seconds
Started Feb 28 04:27:10 PM PST 24
Finished Feb 28 04:27:11 PM PST 24
Peak memory 205620 kb
Host smart-64fccd7e-720a-4d81-99f3-ac8e1c9c47a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213888078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.4213888078
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.370004407
Short name T204
Test name
Test status
Simulation time 97937684 ps
CPU time 1.02 seconds
Started Feb 28 04:27:08 PM PST 24
Finished Feb 28 04:27:09 PM PST 24
Peak memory 205852 kb
Host smart-941e2b80-8e69-4812-bd05-d6bbb6c6798e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370004407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.370004407
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3289334571
Short name T854
Test name
Test status
Simulation time 21475694 ps
CPU time 1.46 seconds
Started Feb 28 04:27:14 PM PST 24
Finished Feb 28 04:27:15 PM PST 24
Peak memory 214108 kb
Host smart-45b7122f-fc7c-422c-9301-ef09b3041ae5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289334571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3289334571
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.177807796
Short name T871
Test name
Test status
Simulation time 316839089 ps
CPU time 2.19 seconds
Started Feb 28 04:27:43 PM PST 24
Finished Feb 28 04:27:45 PM PST 24
Peak memory 205644 kb
Host smart-c7ab0b32-c68b-479a-9d47-da7da67d17bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177807796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.177807796
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2321375034
Short name T956
Test name
Test status
Simulation time 104627128 ps
CPU time 1.2 seconds
Started Feb 28 04:27:09 PM PST 24
Finished Feb 28 04:27:10 PM PST 24
Peak memory 215768 kb
Host smart-8bd974c6-8645-4071-a65c-4fbb79ce4520
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321375034 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2321375034
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1255256040
Short name T885
Test name
Test status
Simulation time 27343164 ps
CPU time 0.88 seconds
Started Feb 28 04:27:13 PM PST 24
Finished Feb 28 04:27:14 PM PST 24
Peak memory 205844 kb
Host smart-2e2eec2a-0d92-4d95-9b27-b5ddd0118007
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255256040 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1255256040
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.520426610
Short name T838
Test name
Test status
Simulation time 53819380 ps
CPU time 0.92 seconds
Started Feb 28 04:27:09 PM PST 24
Finished Feb 28 04:27:10 PM PST 24
Peak memory 205700 kb
Host smart-1174b680-4dcc-4d64-ab04-f8a9079360e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520426610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.520426610
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3874473401
Short name T882
Test name
Test status
Simulation time 56202980 ps
CPU time 1.26 seconds
Started Feb 28 04:27:08 PM PST 24
Finished Feb 28 04:27:10 PM PST 24
Peak memory 205828 kb
Host smart-467660cb-22a6-4692-aabc-56c29cac8430
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874473401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3874473401
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1131026801
Short name T900
Test name
Test status
Simulation time 246876242 ps
CPU time 2.54 seconds
Started Feb 28 04:27:08 PM PST 24
Finished Feb 28 04:27:11 PM PST 24
Peak memory 214168 kb
Host smart-7c294a5f-23c3-4744-b00f-a2e54b640cb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131026801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1131026801
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1940432452
Short name T887
Test name
Test status
Simulation time 77264359 ps
CPU time 1.45 seconds
Started Feb 28 04:27:13 PM PST 24
Finished Feb 28 04:27:14 PM PST 24
Peak memory 217836 kb
Host smart-e87dbdf8-a6f6-4a93-bd79-c0ad4827a3d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940432452 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1940432452
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.4025844196
Short name T857
Test name
Test status
Simulation time 107562951 ps
CPU time 0.9 seconds
Started Feb 28 04:27:09 PM PST 24
Finished Feb 28 04:27:10 PM PST 24
Peak memory 205772 kb
Host smart-6e9758a4-c23f-4919-b80b-99e7d38b447a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025844196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.4025844196
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.937009605
Short name T907
Test name
Test status
Simulation time 14440580 ps
CPU time 0.85 seconds
Started Feb 28 04:27:07 PM PST 24
Finished Feb 28 04:27:08 PM PST 24
Peak memory 205708 kb
Host smart-1123fbd4-a1c0-490b-a497-db0a67cea36e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937009605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.937009605
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1816754292
Short name T203
Test name
Test status
Simulation time 34194016 ps
CPU time 1.33 seconds
Started Feb 28 04:27:12 PM PST 24
Finished Feb 28 04:27:13 PM PST 24
Peak memory 205936 kb
Host smart-75576a2c-ce06-4242-88ba-c1dfcd8ade2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816754292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1816754292
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2305736148
Short name T898
Test name
Test status
Simulation time 75639266 ps
CPU time 2.63 seconds
Started Feb 28 04:27:08 PM PST 24
Finished Feb 28 04:27:11 PM PST 24
Peak memory 214188 kb
Host smart-bd712ad3-c4d6-4fc7-9898-59324fcb97fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305736148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2305736148
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.256644897
Short name T895
Test name
Test status
Simulation time 156948761 ps
CPU time 1.52 seconds
Started Feb 28 04:27:13 PM PST 24
Finished Feb 28 04:27:15 PM PST 24
Peak memory 205948 kb
Host smart-090cde35-c904-419c-aa3d-5b6998bdde3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256644897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.256644897
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.40126591
Short name T910
Test name
Test status
Simulation time 88018992 ps
CPU time 1.5 seconds
Started Feb 28 04:27:14 PM PST 24
Finished Feb 28 04:27:16 PM PST 24
Peak memory 214160 kb
Host smart-35149464-e955-4d43-a5e0-323ba399a3cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40126591 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.40126591
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1542925357
Short name T879
Test name
Test status
Simulation time 39632828 ps
CPU time 0.89 seconds
Started Feb 28 04:27:15 PM PST 24
Finished Feb 28 04:27:16 PM PST 24
Peak memory 205844 kb
Host smart-7ed42788-a85f-4415-8384-46863c47d413
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542925357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1542925357
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.98312772
Short name T915
Test name
Test status
Simulation time 13479666 ps
CPU time 0.85 seconds
Started Feb 28 04:27:15 PM PST 24
Finished Feb 28 04:27:16 PM PST 24
Peak memory 205796 kb
Host smart-b5895767-1fd2-443c-935f-0d1a80e4bb20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98312772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.98312772
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2031572924
Short name T222
Test name
Test status
Simulation time 23804149 ps
CPU time 1.1 seconds
Started Feb 28 04:27:11 PM PST 24
Finished Feb 28 04:27:13 PM PST 24
Peak memory 205936 kb
Host smart-f45c4ac1-b5ec-46cf-a8b2-b639266e835a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031572924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2031572924
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3131195445
Short name T872
Test name
Test status
Simulation time 151996801 ps
CPU time 2.39 seconds
Started Feb 28 04:27:08 PM PST 24
Finished Feb 28 04:27:10 PM PST 24
Peak memory 214636 kb
Host smart-9b545604-cfc9-41df-98e8-ea2cb98e35e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131195445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3131195445
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.662613290
Short name T875
Test name
Test status
Simulation time 151199594 ps
CPU time 3.12 seconds
Started Feb 28 04:27:08 PM PST 24
Finished Feb 28 04:27:11 PM PST 24
Peak memory 205796 kb
Host smart-4e6d710b-974b-46eb-8693-404527137638
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662613290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.662613290
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.824217120
Short name T861
Test name
Test status
Simulation time 96803129 ps
CPU time 1.2 seconds
Started Feb 28 04:27:12 PM PST 24
Finished Feb 28 04:27:13 PM PST 24
Peak memory 214188 kb
Host smart-f271250e-e965-48f2-a097-b147c88e7efe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824217120 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.824217120
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.461313813
Short name T212
Test name
Test status
Simulation time 12677421 ps
CPU time 0.86 seconds
Started Feb 28 04:27:17 PM PST 24
Finished Feb 28 04:27:18 PM PST 24
Peak memory 205804 kb
Host smart-974bb899-32b7-4773-92aa-f9afa14c134c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461313813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.461313813
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1908447246
Short name T851
Test name
Test status
Simulation time 17965678 ps
CPU time 0.94 seconds
Started Feb 28 04:27:14 PM PST 24
Finished Feb 28 04:27:16 PM PST 24
Peak memory 205732 kb
Host smart-544d09e7-3571-4e7b-9a3e-20b5c5f45873
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908447246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1908447246
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3934377249
Short name T924
Test name
Test status
Simulation time 63551961 ps
CPU time 1.17 seconds
Started Feb 28 04:27:15 PM PST 24
Finished Feb 28 04:27:16 PM PST 24
Peak memory 205864 kb
Host smart-3597267a-cf48-4329-a100-ca99df4c1e59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934377249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3934377249
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.829243050
Short name T870
Test name
Test status
Simulation time 61732777 ps
CPU time 2.49 seconds
Started Feb 28 04:27:14 PM PST 24
Finished Feb 28 04:27:17 PM PST 24
Peak memory 214220 kb
Host smart-0affd879-dc8c-479d-9e57-d0fadc08af22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829243050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.829243050
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.167728595
Short name T236
Test name
Test status
Simulation time 74684710 ps
CPU time 2.35 seconds
Started Feb 28 04:27:16 PM PST 24
Finished Feb 28 04:27:18 PM PST 24
Peak memory 205772 kb
Host smart-9f0d5237-b95b-467d-8563-3c0031a7f6e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167728595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.167728595
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2760241566
Short name T856
Test name
Test status
Simulation time 88043952 ps
CPU time 1.62 seconds
Started Feb 28 04:27:17 PM PST 24
Finished Feb 28 04:27:19 PM PST 24
Peak memory 214136 kb
Host smart-7f55df23-9a2b-466e-bc71-df23cf25e8fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760241566 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2760241566
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3497689752
Short name T936
Test name
Test status
Simulation time 27854787 ps
CPU time 0.79 seconds
Started Feb 28 04:27:14 PM PST 24
Finished Feb 28 04:27:15 PM PST 24
Peak memory 205780 kb
Host smart-43db8b71-95e0-45da-b078-34f985d0a075
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497689752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3497689752
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3549940721
Short name T937
Test name
Test status
Simulation time 56256808 ps
CPU time 0.86 seconds
Started Feb 28 04:27:15 PM PST 24
Finished Feb 28 04:27:16 PM PST 24
Peak memory 205828 kb
Host smart-185249c3-a852-44d0-83ea-1cccf80c3457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549940721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3549940721
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3795960592
Short name T209
Test name
Test status
Simulation time 37420642 ps
CPU time 1.4 seconds
Started Feb 28 04:27:18 PM PST 24
Finished Feb 28 04:27:20 PM PST 24
Peak memory 205744 kb
Host smart-430b0346-cccc-44e1-8a50-b572440e6d42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795960592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3795960592
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1591902616
Short name T896
Test name
Test status
Simulation time 43592700 ps
CPU time 2.62 seconds
Started Feb 28 04:27:13 PM PST 24
Finished Feb 28 04:27:16 PM PST 24
Peak memory 214076 kb
Host smart-04a08077-7947-43f7-9aac-c1331c7b9909
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591902616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1591902616
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1162985193
Short name T876
Test name
Test status
Simulation time 46453330 ps
CPU time 1.56 seconds
Started Feb 28 04:27:12 PM PST 24
Finished Feb 28 04:27:14 PM PST 24
Peak memory 205864 kb
Host smart-ddbf2773-ec01-456f-b677-bba6b337b658
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162985193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1162985193
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3761139188
Short name T950
Test name
Test status
Simulation time 43038323 ps
CPU time 0.95 seconds
Started Feb 28 04:26:44 PM PST 24
Finished Feb 28 04:26:46 PM PST 24
Peak memory 205880 kb
Host smart-1f6bfdfd-c37a-461b-90f6-4d86571c329a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761139188 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3761139188
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2106407287
Short name T938
Test name
Test status
Simulation time 923172036 ps
CPU time 3.56 seconds
Started Feb 28 04:26:38 PM PST 24
Finished Feb 28 04:26:43 PM PST 24
Peak memory 205848 kb
Host smart-48e5d7ef-7ff8-45d8-b986-7331b4623f31
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106407287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2106407287
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1697685876
Short name T926
Test name
Test status
Simulation time 15939373 ps
CPU time 0.93 seconds
Started Feb 28 04:26:37 PM PST 24
Finished Feb 28 04:26:39 PM PST 24
Peak memory 205860 kb
Host smart-babc9d76-2ae0-49c7-8b09-0055b7f67940
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697685876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1697685876
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3400689815
Short name T892
Test name
Test status
Simulation time 18351735 ps
CPU time 1.01 seconds
Started Feb 28 04:26:42 PM PST 24
Finished Feb 28 04:26:44 PM PST 24
Peak memory 214072 kb
Host smart-3a14c48c-1805-4036-a153-664481d64c11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400689815 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3400689815
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1425102752
Short name T213
Test name
Test status
Simulation time 16365829 ps
CPU time 0.86 seconds
Started Feb 28 04:26:37 PM PST 24
Finished Feb 28 04:26:38 PM PST 24
Peak memory 205820 kb
Host smart-d9383375-6c39-4ad4-8ac7-009349127795
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425102752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1425102752
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.680179108
Short name T841
Test name
Test status
Simulation time 43931106 ps
CPU time 0.94 seconds
Started Feb 28 04:26:39 PM PST 24
Finished Feb 28 04:26:41 PM PST 24
Peak memory 205872 kb
Host smart-8a4187f9-f619-4ac6-b739-a0a67b94b6bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680179108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.680179108
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3541660716
Short name T202
Test name
Test status
Simulation time 79542244 ps
CPU time 1 seconds
Started Feb 28 04:26:43 PM PST 24
Finished Feb 28 04:26:44 PM PST 24
Peak memory 205936 kb
Host smart-2f215c52-123c-40c0-af47-5a20a32a38b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541660716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3541660716
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3012994135
Short name T886
Test name
Test status
Simulation time 275483360 ps
CPU time 2.54 seconds
Started Feb 28 04:26:38 PM PST 24
Finished Feb 28 04:26:41 PM PST 24
Peak memory 214100 kb
Host smart-799842e9-bddc-45c2-9a52-e6ea369851ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012994135 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3012994135
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3961706014
Short name T904
Test name
Test status
Simulation time 47921986 ps
CPU time 1.66 seconds
Started Feb 28 04:26:37 PM PST 24
Finished Feb 28 04:26:39 PM PST 24
Peak memory 205880 kb
Host smart-126bfda4-2f79-474e-a0d1-82dd30a09c84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961706014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3961706014
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3614866864
Short name T949
Test name
Test status
Simulation time 16616649 ps
CPU time 0.8 seconds
Started Feb 28 04:27:18 PM PST 24
Finished Feb 28 04:27:19 PM PST 24
Peak memory 205800 kb
Host smart-c7118c3b-5d2e-409c-a4a5-01bf507d1cd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614866864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3614866864
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1260335541
Short name T897
Test name
Test status
Simulation time 23377845 ps
CPU time 0.83 seconds
Started Feb 28 04:27:17 PM PST 24
Finished Feb 28 04:27:19 PM PST 24
Peak memory 205624 kb
Host smart-19296734-fbc5-449a-b38e-165a82b0218f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260335541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1260335541
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2547750570
Short name T951
Test name
Test status
Simulation time 90749972 ps
CPU time 0.82 seconds
Started Feb 28 04:27:18 PM PST 24
Finished Feb 28 04:27:19 PM PST 24
Peak memory 205692 kb
Host smart-291b3bb3-80c6-485b-8aaf-a8ae88385df0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547750570 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2547750570
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.4240613136
Short name T935
Test name
Test status
Simulation time 19335293 ps
CPU time 0.79 seconds
Started Feb 28 04:27:17 PM PST 24
Finished Feb 28 04:27:18 PM PST 24
Peak memory 205784 kb
Host smart-89788b5c-51ed-4f39-83cc-918b1b807091
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240613136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.4240613136
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2227862774
Short name T868
Test name
Test status
Simulation time 13811253 ps
CPU time 0.86 seconds
Started Feb 28 04:27:18 PM PST 24
Finished Feb 28 04:27:19 PM PST 24
Peak memory 205868 kb
Host smart-daf9470c-5e97-46d4-bb17-02e4c3ef05dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227862774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2227862774
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2072781473
Short name T855
Test name
Test status
Simulation time 10894864 ps
CPU time 0.82 seconds
Started Feb 28 04:27:18 PM PST 24
Finished Feb 28 04:27:18 PM PST 24
Peak memory 205696 kb
Host smart-a3c54895-f877-4212-b49e-f334d11c4b2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072781473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2072781473
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.4007249345
Short name T955
Test name
Test status
Simulation time 30024998 ps
CPU time 0.77 seconds
Started Feb 28 04:27:17 PM PST 24
Finished Feb 28 04:27:18 PM PST 24
Peak memory 205688 kb
Host smart-f5488314-562e-4764-98cc-99612827a3bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007249345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.4007249345
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2073792082
Short name T905
Test name
Test status
Simulation time 46323210 ps
CPU time 0.86 seconds
Started Feb 28 04:27:19 PM PST 24
Finished Feb 28 04:27:20 PM PST 24
Peak memory 205676 kb
Host smart-14b6e255-e164-4dcc-a55f-f2d5b8b4a667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073792082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2073792082
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3108014592
Short name T942
Test name
Test status
Simulation time 14166334 ps
CPU time 0.83 seconds
Started Feb 28 04:27:18 PM PST 24
Finished Feb 28 04:27:19 PM PST 24
Peak memory 205748 kb
Host smart-e0af7416-36f6-422d-bccd-5207df804138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108014592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3108014592
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2367433869
Short name T866
Test name
Test status
Simulation time 164654721 ps
CPU time 0.88 seconds
Started Feb 28 04:27:16 PM PST 24
Finished Feb 28 04:27:17 PM PST 24
Peak memory 205776 kb
Host smart-a413f97d-dade-47f1-a376-b56c46a388ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367433869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2367433869
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3652564152
Short name T206
Test name
Test status
Simulation time 16720624 ps
CPU time 1.01 seconds
Started Feb 28 04:26:44 PM PST 24
Finished Feb 28 04:26:46 PM PST 24
Peak memory 205856 kb
Host smart-4b4bd118-0bd6-4900-9251-43c57509392e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652564152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3652564152
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.826702922
Short name T963
Test name
Test status
Simulation time 159726054 ps
CPU time 1.97 seconds
Started Feb 28 04:26:44 PM PST 24
Finished Feb 28 04:26:46 PM PST 24
Peak memory 205736 kb
Host smart-6ffd9c65-a8ab-4fb1-b9ea-257f629fdc77
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826702922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.826702922
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2355437600
Short name T225
Test name
Test status
Simulation time 190572514 ps
CPU time 0.97 seconds
Started Feb 28 04:26:44 PM PST 24
Finished Feb 28 04:26:45 PM PST 24
Peak memory 205904 kb
Host smart-5bfa94e8-552e-4446-8e17-2948da7bb229
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355437600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2355437600
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.277051353
Short name T845
Test name
Test status
Simulation time 48791466 ps
CPU time 1.7 seconds
Started Feb 28 04:26:44 PM PST 24
Finished Feb 28 04:26:46 PM PST 24
Peak memory 214024 kb
Host smart-6bfb25a5-58e9-468f-bf09-7b6bc0b17f82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277051353 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.277051353
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3364868418
Short name T923
Test name
Test status
Simulation time 23475312 ps
CPU time 0.78 seconds
Started Feb 28 04:26:44 PM PST 24
Finished Feb 28 04:26:45 PM PST 24
Peak memory 205880 kb
Host smart-91942725-01db-4c99-aeb6-f7f0f55f7115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364868418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3364868418
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.353987850
Short name T205
Test name
Test status
Simulation time 46639941 ps
CPU time 1.05 seconds
Started Feb 28 04:26:45 PM PST 24
Finished Feb 28 04:26:46 PM PST 24
Peak memory 205812 kb
Host smart-32d39852-be89-44c6-b694-47256bb9c58b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353987850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.353987850
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1369718040
Short name T946
Test name
Test status
Simulation time 291102256 ps
CPU time 2.3 seconds
Started Feb 28 04:26:42 PM PST 24
Finished Feb 28 04:26:44 PM PST 24
Peak memory 214176 kb
Host smart-3e823eca-1027-409b-8723-8c8a58eb3619
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369718040 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1369718040
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1949812530
Short name T920
Test name
Test status
Simulation time 79848918 ps
CPU time 2.22 seconds
Started Feb 28 04:26:44 PM PST 24
Finished Feb 28 04:26:47 PM PST 24
Peak memory 205896 kb
Host smart-718ed2e8-cae0-4284-a944-ecf911fdb9d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949812530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1949812530
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2613056571
Short name T849
Test name
Test status
Simulation time 35870583 ps
CPU time 0.78 seconds
Started Feb 28 04:27:18 PM PST 24
Finished Feb 28 04:27:19 PM PST 24
Peak memory 205752 kb
Host smart-c1cbf3bc-7221-4e3a-9d91-0b3dacac47c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613056571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2613056571
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.784482166
Short name T842
Test name
Test status
Simulation time 41296477 ps
CPU time 0.79 seconds
Started Feb 28 04:27:18 PM PST 24
Finished Feb 28 04:27:19 PM PST 24
Peak memory 205620 kb
Host smart-ff4136bd-b75e-45ee-a64d-682908475f46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784482166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.784482166
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3775438579
Short name T916
Test name
Test status
Simulation time 32345496 ps
CPU time 0.74 seconds
Started Feb 28 04:27:17 PM PST 24
Finished Feb 28 04:27:18 PM PST 24
Peak memory 205728 kb
Host smart-94143acb-8b18-4a22-8187-7846e6f43d01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775438579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3775438579
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3392321889
Short name T881
Test name
Test status
Simulation time 13619710 ps
CPU time 0.85 seconds
Started Feb 28 04:27:22 PM PST 24
Finished Feb 28 04:27:23 PM PST 24
Peak memory 205848 kb
Host smart-cba5c61e-0874-4ff8-a4e3-95cd637a48e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392321889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3392321889
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3318411292
Short name T893
Test name
Test status
Simulation time 37429160 ps
CPU time 0.79 seconds
Started Feb 28 04:27:22 PM PST 24
Finished Feb 28 04:27:23 PM PST 24
Peak memory 205632 kb
Host smart-046a7ab9-34f6-4aa6-abe4-ef6b9ccdb9b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318411292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3318411292
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2202802562
Short name T944
Test name
Test status
Simulation time 46754357 ps
CPU time 0.93 seconds
Started Feb 28 04:27:21 PM PST 24
Finished Feb 28 04:27:22 PM PST 24
Peak memory 205676 kb
Host smart-502c2524-b9e4-480f-99b9-443fe02fab8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202802562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2202802562
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.4163261126
Short name T914
Test name
Test status
Simulation time 116194367 ps
CPU time 0.83 seconds
Started Feb 28 04:27:22 PM PST 24
Finished Feb 28 04:27:23 PM PST 24
Peak memory 205792 kb
Host smart-10eb657e-5596-42f1-af9b-a6f1b41f8ba0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163261126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.4163261126
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2382625342
Short name T917
Test name
Test status
Simulation time 27158343 ps
CPU time 0.82 seconds
Started Feb 28 04:27:23 PM PST 24
Finished Feb 28 04:27:25 PM PST 24
Peak memory 205664 kb
Host smart-43fa6345-ea70-4030-90d7-554da3e9c063
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382625342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2382625342
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2455559786
Short name T928
Test name
Test status
Simulation time 38003172 ps
CPU time 0.89 seconds
Started Feb 28 04:27:22 PM PST 24
Finished Feb 28 04:27:23 PM PST 24
Peak memory 205876 kb
Host smart-9c51aa3d-5a68-4de1-b3c2-0d04c7543948
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455559786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2455559786
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3097650667
Short name T968
Test name
Test status
Simulation time 12446445 ps
CPU time 0.83 seconds
Started Feb 28 04:27:24 PM PST 24
Finished Feb 28 04:27:25 PM PST 24
Peak memory 205696 kb
Host smart-3e5fcc4b-a40e-4fe0-bc56-a7089d898e75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097650667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3097650667
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.589754464
Short name T218
Test name
Test status
Simulation time 20540301 ps
CPU time 1.26 seconds
Started Feb 28 04:26:46 PM PST 24
Finished Feb 28 04:26:48 PM PST 24
Peak memory 205872 kb
Host smart-d9fc390c-f716-4b29-8560-722c89a9435d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589754464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.589754464
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3743792576
Short name T873
Test name
Test status
Simulation time 50869029 ps
CPU time 1.94 seconds
Started Feb 28 04:26:46 PM PST 24
Finished Feb 28 04:26:48 PM PST 24
Peak memory 205776 kb
Host smart-dd6a547b-a166-4a59-841e-c9142f4a3834
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743792576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3743792576
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3911308493
Short name T889
Test name
Test status
Simulation time 28190160 ps
CPU time 0.88 seconds
Started Feb 28 04:26:46 PM PST 24
Finished Feb 28 04:26:47 PM PST 24
Peak memory 205804 kb
Host smart-99b739e5-840d-41b7-acfd-9cf85938b3a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911308493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3911308493
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2116620784
Short name T962
Test name
Test status
Simulation time 99876818 ps
CPU time 1.31 seconds
Started Feb 28 04:26:45 PM PST 24
Finished Feb 28 04:26:47 PM PST 24
Peak memory 214068 kb
Host smart-59d86b52-379c-4d8e-b68b-a770857ac188
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116620784 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2116620784
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3421542159
Short name T859
Test name
Test status
Simulation time 12812513 ps
CPU time 0.85 seconds
Started Feb 28 04:26:47 PM PST 24
Finished Feb 28 04:26:48 PM PST 24
Peak memory 205792 kb
Host smart-7ca66db5-1ada-40d4-82a0-102314b380b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421542159 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3421542159
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.52385866
Short name T930
Test name
Test status
Simulation time 21314171 ps
CPU time 0.77 seconds
Started Feb 28 04:26:46 PM PST 24
Finished Feb 28 04:26:47 PM PST 24
Peak memory 205784 kb
Host smart-f18d9a3a-c1b6-4b9f-84df-ade7574d9556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52385866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.52385866
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.4213006949
Short name T860
Test name
Test status
Simulation time 38692144 ps
CPU time 1 seconds
Started Feb 28 04:26:48 PM PST 24
Finished Feb 28 04:26:50 PM PST 24
Peak memory 205776 kb
Host smart-7cb81de6-4403-4f3f-919a-b8470d74220a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213006949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.4213006949
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2391019217
Short name T929
Test name
Test status
Simulation time 211114416 ps
CPU time 2.14 seconds
Started Feb 28 04:26:46 PM PST 24
Finished Feb 28 04:26:48 PM PST 24
Peak memory 214044 kb
Host smart-598127db-5fe3-415b-82d5-9c34199adadd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391019217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2391019217
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.701737713
Short name T954
Test name
Test status
Simulation time 85660732 ps
CPU time 1.42 seconds
Started Feb 28 04:26:50 PM PST 24
Finished Feb 28 04:26:51 PM PST 24
Peak memory 205848 kb
Host smart-1707ed86-6408-465e-8b62-504fc3efeed6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701737713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.701737713
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.11456736
Short name T925
Test name
Test status
Simulation time 30563743 ps
CPU time 0.77 seconds
Started Feb 28 04:27:21 PM PST 24
Finished Feb 28 04:27:22 PM PST 24
Peak memory 205636 kb
Host smart-85ea1cc6-2726-425e-9f97-286327698b7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11456736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.11456736
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1817435615
Short name T869
Test name
Test status
Simulation time 41224832 ps
CPU time 0.79 seconds
Started Feb 28 04:27:24 PM PST 24
Finished Feb 28 04:27:25 PM PST 24
Peak memory 205624 kb
Host smart-8b08ee8a-ea42-47c6-be08-4110bef914c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817435615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1817435615
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3968728347
Short name T927
Test name
Test status
Simulation time 16788602 ps
CPU time 0.89 seconds
Started Feb 28 04:27:20 PM PST 24
Finished Feb 28 04:27:21 PM PST 24
Peak memory 205736 kb
Host smart-2eed95b2-2a7b-4b74-93ac-63c4717e8511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968728347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3968728347
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1754480101
Short name T864
Test name
Test status
Simulation time 90550400 ps
CPU time 0.75 seconds
Started Feb 28 04:27:24 PM PST 24
Finished Feb 28 04:27:25 PM PST 24
Peak memory 205624 kb
Host smart-c126f28e-7093-4e10-8ed5-f619d7703a43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754480101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1754480101
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.376219050
Short name T967
Test name
Test status
Simulation time 24992263 ps
CPU time 0.8 seconds
Started Feb 28 04:27:25 PM PST 24
Finished Feb 28 04:27:26 PM PST 24
Peak memory 205804 kb
Host smart-d1b26ea2-d1ec-421e-a457-bf1f68375348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376219050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.376219050
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.608330990
Short name T913
Test name
Test status
Simulation time 26683634 ps
CPU time 0.89 seconds
Started Feb 28 04:27:22 PM PST 24
Finished Feb 28 04:27:23 PM PST 24
Peak memory 205700 kb
Host smart-5a377cd8-1366-4149-b068-c8568896a316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608330990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.608330990
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.16651127
Short name T961
Test name
Test status
Simulation time 56816679 ps
CPU time 0.85 seconds
Started Feb 28 04:27:24 PM PST 24
Finished Feb 28 04:27:25 PM PST 24
Peak memory 205804 kb
Host smart-c9d4d9d9-d941-4625-b8e4-e24aebf57d15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16651127 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.16651127
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.656279681
Short name T867
Test name
Test status
Simulation time 11801732 ps
CPU time 0.83 seconds
Started Feb 28 04:27:23 PM PST 24
Finished Feb 28 04:27:24 PM PST 24
Peak memory 205796 kb
Host smart-c279e716-1abd-4351-85a3-43da5806a8a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656279681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.656279681
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2084211347
Short name T865
Test name
Test status
Simulation time 165482078 ps
CPU time 0.73 seconds
Started Feb 28 04:27:43 PM PST 24
Finished Feb 28 04:27:44 PM PST 24
Peak memory 205472 kb
Host smart-e0034d9c-334d-42f9-a399-b6921071ce74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084211347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2084211347
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1829892335
Short name T931
Test name
Test status
Simulation time 15413066 ps
CPU time 0.84 seconds
Started Feb 28 04:27:20 PM PST 24
Finished Feb 28 04:27:21 PM PST 24
Peak memory 205744 kb
Host smart-68b85274-3457-4cdf-851f-013a17f94961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829892335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1829892335
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3427326467
Short name T839
Test name
Test status
Simulation time 95770130 ps
CPU time 1.2 seconds
Started Feb 28 04:26:52 PM PST 24
Finished Feb 28 04:26:54 PM PST 24
Peak memory 216292 kb
Host smart-214060ed-d82b-45d7-b5df-838135260b9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427326467 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3427326467
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3621487757
Short name T943
Test name
Test status
Simulation time 17203705 ps
CPU time 1.02 seconds
Started Feb 28 04:26:51 PM PST 24
Finished Feb 28 04:26:53 PM PST 24
Peak memory 205868 kb
Host smart-0acc0a0f-e23b-415e-8a57-60281dc07309
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621487757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3621487757
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3395649712
Short name T964
Test name
Test status
Simulation time 22994878 ps
CPU time 0.78 seconds
Started Feb 28 04:26:53 PM PST 24
Finished Feb 28 04:26:54 PM PST 24
Peak memory 205856 kb
Host smart-dccf577e-f79b-437a-9166-6939fd94d903
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395649712 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3395649712
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3288225768
Short name T223
Test name
Test status
Simulation time 20497391 ps
CPU time 1.01 seconds
Started Feb 28 04:26:52 PM PST 24
Finished Feb 28 04:26:53 PM PST 24
Peak memory 205756 kb
Host smart-6ec785ca-a8cd-49f7-822a-dc2e6e47e7e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288225768 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3288225768
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.4086693184
Short name T884
Test name
Test status
Simulation time 201966243 ps
CPU time 3.51 seconds
Started Feb 28 04:26:45 PM PST 24
Finished Feb 28 04:26:49 PM PST 24
Peak memory 214084 kb
Host smart-03b6110b-599d-431c-9314-ce1e54566ac7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086693184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.4086693184
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3355476836
Short name T858
Test name
Test status
Simulation time 301746398 ps
CPU time 2.18 seconds
Started Feb 28 04:26:53 PM PST 24
Finished Feb 28 04:26:56 PM PST 24
Peak memory 205944 kb
Host smart-ac33f761-ce84-42a7-9b70-1a459aa30f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355476836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3355476836
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2764509448
Short name T911
Test name
Test status
Simulation time 163858011 ps
CPU time 1.28 seconds
Started Feb 28 04:26:53 PM PST 24
Finished Feb 28 04:26:54 PM PST 24
Peak memory 214120 kb
Host smart-0d3ee115-cac2-4889-bea9-83c590ad169f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764509448 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2764509448
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3695631466
Short name T959
Test name
Test status
Simulation time 15125378 ps
CPU time 0.85 seconds
Started Feb 28 04:26:50 PM PST 24
Finished Feb 28 04:26:51 PM PST 24
Peak memory 205748 kb
Host smart-592ae831-a1b2-46c3-b186-065d1bb20181
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695631466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3695631466
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.2191683764
Short name T840
Test name
Test status
Simulation time 58679116 ps
CPU time 0.85 seconds
Started Feb 28 04:26:55 PM PST 24
Finished Feb 28 04:26:56 PM PST 24
Peak memory 205772 kb
Host smart-fb4c617a-d0b2-42fd-8e9b-9209a2c521ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191683764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2191683764
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1566676174
Short name T894
Test name
Test status
Simulation time 21727461 ps
CPU time 1.2 seconds
Started Feb 28 04:26:54 PM PST 24
Finished Feb 28 04:26:55 PM PST 24
Peak memory 205844 kb
Host smart-75428074-8142-45f6-9396-32ef94c61416
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566676174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1566676174
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3669443388
Short name T891
Test name
Test status
Simulation time 100784899 ps
CPU time 1.78 seconds
Started Feb 28 04:26:51 PM PST 24
Finished Feb 28 04:26:53 PM PST 24
Peak memory 214052 kb
Host smart-44db3bd5-71d9-4709-b16a-ef127f6068fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669443388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3669443388
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1301152224
Short name T228
Test name
Test status
Simulation time 139739880 ps
CPU time 3.08 seconds
Started Feb 28 04:26:53 PM PST 24
Finished Feb 28 04:26:56 PM PST 24
Peak memory 205824 kb
Host smart-ecbf1972-0ac1-47bf-b8ee-386446b8cf2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301152224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1301152224
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2917666526
Short name T969
Test name
Test status
Simulation time 17812936 ps
CPU time 1.09 seconds
Started Feb 28 04:26:55 PM PST 24
Finished Feb 28 04:26:56 PM PST 24
Peak memory 214188 kb
Host smart-f54f8d5a-8479-4c48-ad9e-5ba9b6ca9819
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917666526 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2917666526
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.822425147
Short name T211
Test name
Test status
Simulation time 21369333 ps
CPU time 0.86 seconds
Started Feb 28 04:26:55 PM PST 24
Finished Feb 28 04:26:56 PM PST 24
Peak memory 205748 kb
Host smart-5e2e0f2c-be0c-40a9-ae19-6339afaf0351
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822425147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.822425147
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3880291119
Short name T953
Test name
Test status
Simulation time 28372254 ps
CPU time 0.75 seconds
Started Feb 28 04:26:55 PM PST 24
Finished Feb 28 04:26:56 PM PST 24
Peak memory 205668 kb
Host smart-f070e655-76ae-4701-9346-39d2ecb4fe94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880291119 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3880291119
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.39746631
Short name T877
Test name
Test status
Simulation time 201742030 ps
CPU time 1.1 seconds
Started Feb 28 04:26:55 PM PST 24
Finished Feb 28 04:26:57 PM PST 24
Peak memory 205820 kb
Host smart-5e8daacf-1b43-4d84-860e-dda6e82b0313
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39746631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outs
tanding.39746631
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3461633045
Short name T902
Test name
Test status
Simulation time 40969139 ps
CPU time 1.43 seconds
Started Feb 28 04:26:50 PM PST 24
Finished Feb 28 04:26:51 PM PST 24
Peak memory 214036 kb
Host smart-71dd6611-4f33-46b7-a95b-9407fada3109
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461633045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3461633045
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1844090141
Short name T941
Test name
Test status
Simulation time 161981757 ps
CPU time 2.23 seconds
Started Feb 28 04:26:57 PM PST 24
Finished Feb 28 04:26:59 PM PST 24
Peak memory 205872 kb
Host smart-daa20b40-b5e6-4079-8462-4f7e80884419
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844090141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1844090141
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2750749006
Short name T844
Test name
Test status
Simulation time 62338121 ps
CPU time 0.9 seconds
Started Feb 28 04:26:58 PM PST 24
Finished Feb 28 04:26:59 PM PST 24
Peak memory 205892 kb
Host smart-0094723f-228d-4e82-a5ed-a671f7bee342
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750749006 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2750749006
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3672649515
Short name T919
Test name
Test status
Simulation time 23600092 ps
CPU time 0.83 seconds
Started Feb 28 04:27:00 PM PST 24
Finished Feb 28 04:27:01 PM PST 24
Peak memory 205836 kb
Host smart-745f64e5-d5ba-4a91-8bdd-f760699c2227
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672649515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3672649515
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.4089900102
Short name T947
Test name
Test status
Simulation time 15476694 ps
CPU time 0.85 seconds
Started Feb 28 04:26:55 PM PST 24
Finished Feb 28 04:26:56 PM PST 24
Peak memory 205752 kb
Host smart-76814434-24a4-4fa1-8af9-32d39b71dd6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089900102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.4089900102
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2215430735
Short name T201
Test name
Test status
Simulation time 26162941 ps
CPU time 1.16 seconds
Started Feb 28 04:27:00 PM PST 24
Finished Feb 28 04:27:01 PM PST 24
Peak memory 205864 kb
Host smart-eedbbbb4-dac7-465c-ae45-2b4f75a17f27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215430735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2215430735
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2338431445
Short name T850
Test name
Test status
Simulation time 93172137 ps
CPU time 2.64 seconds
Started Feb 28 04:26:54 PM PST 24
Finished Feb 28 04:26:57 PM PST 24
Peak memory 214088 kb
Host smart-e415a7a4-c023-426b-9d60-f9a72b6b82ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338431445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2338431445
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.902127834
Short name T235
Test name
Test status
Simulation time 381023932 ps
CPU time 2.06 seconds
Started Feb 28 04:26:55 PM PST 24
Finished Feb 28 04:26:57 PM PST 24
Peak memory 205908 kb
Host smart-56a2e331-d13f-4467-a040-79baf24025c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902127834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.902127834
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.71067574
Short name T863
Test name
Test status
Simulation time 99298471 ps
CPU time 1.32 seconds
Started Feb 28 04:27:01 PM PST 24
Finished Feb 28 04:27:02 PM PST 24
Peak memory 216288 kb
Host smart-eaf9e9c9-156b-4475-ab9c-72c3c2f736cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71067574 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.71067574
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2616032820
Short name T219
Test name
Test status
Simulation time 12318997 ps
CPU time 0.86 seconds
Started Feb 28 04:26:59 PM PST 24
Finished Feb 28 04:27:00 PM PST 24
Peak memory 205832 kb
Host smart-70db911a-7d46-4119-8cc3-ba8f72bafb6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616032820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2616032820
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2476971720
Short name T918
Test name
Test status
Simulation time 25858312 ps
CPU time 0.83 seconds
Started Feb 28 04:26:59 PM PST 24
Finished Feb 28 04:27:00 PM PST 24
Peak memory 205812 kb
Host smart-27fd415e-efd5-4262-bbf1-5ab258a8d643
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476971720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2476971720
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1975463036
Short name T952
Test name
Test status
Simulation time 45876829 ps
CPU time 0.92 seconds
Started Feb 28 04:27:01 PM PST 24
Finished Feb 28 04:27:02 PM PST 24
Peak memory 205860 kb
Host smart-c9e34cc4-d60a-4812-89c8-4e54b1c16b84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975463036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1975463036
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1348003381
Short name T945
Test name
Test status
Simulation time 108214209 ps
CPU time 3.57 seconds
Started Feb 28 04:26:58 PM PST 24
Finished Feb 28 04:27:02 PM PST 24
Peak memory 214132 kb
Host smart-86c73b67-3cb0-42d3-923d-c9f42aaf1ce4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348003381 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1348003381
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.643335923
Short name T227
Test name
Test status
Simulation time 138218174 ps
CPU time 1.95 seconds
Started Feb 28 04:26:58 PM PST 24
Finished Feb 28 04:27:00 PM PST 24
Peak memory 205828 kb
Host smart-fef7c80f-6a7a-4963-935b-c0557d5a200b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643335923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.643335923
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.358888371
Short name T744
Test name
Test status
Simulation time 26371596 ps
CPU time 1.23 seconds
Started Feb 28 05:59:47 PM PST 24
Finished Feb 28 05:59:48 PM PST 24
Peak memory 215036 kb
Host smart-81bad0f6-3ca3-4354-9a25-d59c06a0f87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358888371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.358888371
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.3767174379
Short name T501
Test name
Test status
Simulation time 59111855 ps
CPU time 0.9 seconds
Started Feb 28 05:59:50 PM PST 24
Finished Feb 28 05:59:52 PM PST 24
Peak memory 205904 kb
Host smart-594dc022-de83-4a8b-80f8-aa3640ee3c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767174379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3767174379
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.983420890
Short name T763
Test name
Test status
Simulation time 29412843 ps
CPU time 0.82 seconds
Started Feb 28 05:59:52 PM PST 24
Finished Feb 28 05:59:53 PM PST 24
Peak memory 215192 kb
Host smart-00d2155a-c938-483e-ac9d-7c3575535d95
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983420890 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.983420890
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.3439416490
Short name T47
Test name
Test status
Simulation time 29865054 ps
CPU time 1 seconds
Started Feb 28 05:59:50 PM PST 24
Finished Feb 28 05:59:51 PM PST 24
Peak memory 222408 kb
Host smart-7eced079-6511-49b1-8992-b063ae38d718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439416490 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3439416490
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.3463985835
Short name T650
Test name
Test status
Simulation time 36049563 ps
CPU time 1.29 seconds
Started Feb 28 05:59:45 PM PST 24
Finished Feb 28 05:59:47 PM PST 24
Peak memory 217104 kb
Host smart-291af1f6-41ef-4a9a-9a63-90ba76738d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463985835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3463985835
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.3521973978
Short name T373
Test name
Test status
Simulation time 23257327 ps
CPU time 1.08 seconds
Started Feb 28 05:59:47 PM PST 24
Finished Feb 28 05:59:49 PM PST 24
Peak memory 214948 kb
Host smart-ebb28be4-1c57-4e5d-a6c3-880626cde960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521973978 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3521973978
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.972385563
Short name T20
Test name
Test status
Simulation time 305581319 ps
CPU time 4.94 seconds
Started Feb 28 05:59:50 PM PST 24
Finished Feb 28 05:59:55 PM PST 24
Peak memory 235024 kb
Host smart-ece04119-e880-47ae-b437-92dc94dafa31
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972385563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.972385563
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.374885531
Short name T513
Test name
Test status
Simulation time 17114597 ps
CPU time 1.01 seconds
Started Feb 28 05:59:45 PM PST 24
Finished Feb 28 05:59:46 PM PST 24
Peak memory 214692 kb
Host smart-067e4c64-e36e-4ebb-acbb-451fcd5c1a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374885531 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.374885531
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2205172262
Short name T515
Test name
Test status
Simulation time 162568318 ps
CPU time 3.32 seconds
Started Feb 28 05:59:48 PM PST 24
Finished Feb 28 05:59:52 PM PST 24
Peak memory 214704 kb
Host smart-708128ce-4452-497a-93d7-8da594d6f4f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205172262 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2205172262
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3465680565
Short name T742
Test name
Test status
Simulation time 78316896150 ps
CPU time 535.35 seconds
Started Feb 28 05:59:45 PM PST 24
Finished Feb 28 06:08:41 PM PST 24
Peak memory 218304 kb
Host smart-deb50c5a-82ce-4704-b939-63cfc64c742b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465680565 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3465680565
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.4031241447
Short name T461
Test name
Test status
Simulation time 75598233 ps
CPU time 0.86 seconds
Started Feb 28 05:59:54 PM PST 24
Finished Feb 28 05:59:55 PM PST 24
Peak memory 206216 kb
Host smart-83063d78-8c8b-4f76-8fa2-0094dc834ca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031241447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.4031241447
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.446713636
Short name T446
Test name
Test status
Simulation time 83759531 ps
CPU time 0.98 seconds
Started Feb 28 05:59:53 PM PST 24
Finished Feb 28 05:59:54 PM PST 24
Peak memory 216816 kb
Host smart-7cccb56c-e27e-428e-8346-dff663f8e49d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446713636 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_dis
able_auto_req_mode.446713636
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.3583610569
Short name T829
Test name
Test status
Simulation time 26442902 ps
CPU time 1.05 seconds
Started Feb 28 05:59:52 PM PST 24
Finished Feb 28 05:59:53 PM PST 24
Peak memory 217620 kb
Host smart-b0d798d8-88c0-4de2-a1a7-49323ba81d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583610569 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3583610569
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2510592135
Short name T815
Test name
Test status
Simulation time 229483214 ps
CPU time 2.74 seconds
Started Feb 28 05:59:52 PM PST 24
Finished Feb 28 05:59:55 PM PST 24
Peak memory 218212 kb
Host smart-b4d0c672-fddc-48dd-8345-ab0147dac02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510592135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2510592135
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1109944566
Short name T21
Test name
Test status
Simulation time 401278692 ps
CPU time 3.88 seconds
Started Feb 28 05:59:54 PM PST 24
Finished Feb 28 05:59:58 PM PST 24
Peak memory 233776 kb
Host smart-7fa9f89d-dcd2-4dd7-a505-12330aa547bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109944566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1109944566
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.1159541325
Short name T3
Test name
Test status
Simulation time 26362910 ps
CPU time 0.93 seconds
Started Feb 28 05:59:49 PM PST 24
Finished Feb 28 05:59:50 PM PST 24
Peak memory 214640 kb
Host smart-6e80d8b4-0e2a-45aa-b431-52fc379932ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159541325 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1159541325
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.448325824
Short name T753
Test name
Test status
Simulation time 292356445815 ps
CPU time 1453.76 seconds
Started Feb 28 05:59:54 PM PST 24
Finished Feb 28 06:24:08 PM PST 24
Peak memory 223232 kb
Host smart-3e5ae5f3-7fd3-4fd2-890c-595b60144c74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448325824 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.448325824
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.3373782577
Short name T732
Test name
Test status
Simulation time 46628763 ps
CPU time 0.86 seconds
Started Feb 28 06:00:31 PM PST 24
Finished Feb 28 06:00:32 PM PST 24
Peak memory 205844 kb
Host smart-18c3dda8-75d5-4814-94cd-34f4f0aaf402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373782577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3373782577
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_err.1253048537
Short name T488
Test name
Test status
Simulation time 19231807 ps
CPU time 1.04 seconds
Started Feb 28 06:00:27 PM PST 24
Finished Feb 28 06:00:29 PM PST 24
Peak memory 217252 kb
Host smart-add5cd14-65ae-495e-97ed-130bacb65ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253048537 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1253048537
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.993524827
Short name T570
Test name
Test status
Simulation time 50109128 ps
CPU time 1.39 seconds
Started Feb 28 06:00:33 PM PST 24
Finished Feb 28 06:00:34 PM PST 24
Peak memory 216072 kb
Host smart-b69df1d6-93b8-42bb-8544-382743e3d16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993524827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.993524827
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1554660316
Short name T345
Test name
Test status
Simulation time 32679989 ps
CPU time 0.92 seconds
Started Feb 28 06:00:31 PM PST 24
Finished Feb 28 06:00:32 PM PST 24
Peak memory 214760 kb
Host smart-d8a3de0a-ca58-441a-a562-2a505ca5633f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554660316 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1554660316
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1367671726
Short name T495
Test name
Test status
Simulation time 19047476 ps
CPU time 1 seconds
Started Feb 28 06:00:30 PM PST 24
Finished Feb 28 06:00:32 PM PST 24
Peak memory 214720 kb
Host smart-f2a401b5-81d0-4544-a673-e10558694331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367671726 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1367671726
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.973490410
Short name T267
Test name
Test status
Simulation time 513675784 ps
CPU time 3.7 seconds
Started Feb 28 06:00:27 PM PST 24
Finished Feb 28 06:00:31 PM PST 24
Peak memory 215736 kb
Host smart-e61367e6-7aaf-4005-83f4-a05f2ca44f68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973490410 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.973490410
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3149690370
Short name T459
Test name
Test status
Simulation time 22841807706 ps
CPU time 365.27 seconds
Started Feb 28 06:00:27 PM PST 24
Finished Feb 28 06:06:33 PM PST 24
Peak memory 217568 kb
Host smart-b66a7d91-12e2-4db4-b965-2ac3e2cf07db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149690370 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3149690370
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.2973550566
Short name T573
Test name
Test status
Simulation time 43086215 ps
CPU time 1.36 seconds
Started Feb 28 06:02:21 PM PST 24
Finished Feb 28 06:02:23 PM PST 24
Peak memory 216972 kb
Host smart-ac9b1e6a-4dba-4b00-9c17-a037be889dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973550566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2973550566
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.1928592369
Short name T748
Test name
Test status
Simulation time 78067989 ps
CPU time 1.32 seconds
Started Feb 28 06:02:24 PM PST 24
Finished Feb 28 06:02:26 PM PST 24
Peak memory 217632 kb
Host smart-49f1ecb8-ccd4-44a5-9142-308b6534d259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928592369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1928592369
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.3418311239
Short name T289
Test name
Test status
Simulation time 58252604 ps
CPU time 1.38 seconds
Started Feb 28 06:02:21 PM PST 24
Finished Feb 28 06:02:23 PM PST 24
Peak memory 218752 kb
Host smart-a5eda932-660a-4ff6-880d-3bbc80d1ab38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418311239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3418311239
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.4263954172
Short name T411
Test name
Test status
Simulation time 39324932 ps
CPU time 1.58 seconds
Started Feb 28 06:02:26 PM PST 24
Finished Feb 28 06:02:27 PM PST 24
Peak memory 217284 kb
Host smart-320a8d6d-bfb5-4717-974f-e6bc16665a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263954172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.4263954172
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.197665421
Short name T824
Test name
Test status
Simulation time 31697812 ps
CPU time 1.28 seconds
Started Feb 28 06:02:26 PM PST 24
Finished Feb 28 06:02:28 PM PST 24
Peak memory 216076 kb
Host smart-c4acb403-2ecc-4ea3-bf95-518d9e8b6385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197665421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.197665421
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2406572129
Short name T737
Test name
Test status
Simulation time 66753801 ps
CPU time 0.96 seconds
Started Feb 28 06:02:23 PM PST 24
Finished Feb 28 06:02:24 PM PST 24
Peak memory 215880 kb
Host smart-36273123-3c6e-4cdc-ad60-2bb6acd2a159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406572129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2406572129
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.3717794287
Short name T679
Test name
Test status
Simulation time 47642769 ps
CPU time 0.95 seconds
Started Feb 28 06:02:23 PM PST 24
Finished Feb 28 06:02:24 PM PST 24
Peak memory 215980 kb
Host smart-2728edaf-ad3d-4a19-a95a-d9ed81a9c44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717794287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3717794287
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2269380338
Short name T608
Test name
Test status
Simulation time 29936149 ps
CPU time 1.25 seconds
Started Feb 28 06:00:31 PM PST 24
Finished Feb 28 06:00:32 PM PST 24
Peak memory 215080 kb
Host smart-791ab7b6-b46c-48bd-8752-5987642e394a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269380338 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2269380338
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.1231165116
Short name T168
Test name
Test status
Simulation time 45572805 ps
CPU time 0.86 seconds
Started Feb 28 06:00:31 PM PST 24
Finished Feb 28 06:00:32 PM PST 24
Peak memory 215064 kb
Host smart-35dd6397-ba8f-4bad-9100-8a2b13df7459
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231165116 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1231165116
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.303887613
Short name T412
Test name
Test status
Simulation time 110540017 ps
CPU time 1.2 seconds
Started Feb 28 06:00:32 PM PST 24
Finished Feb 28 06:00:34 PM PST 24
Peak memory 215720 kb
Host smart-d5a85c39-5851-450d-95c9-fea088c06b38
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303887613 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_di
sable_auto_req_mode.303887613
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.3074895229
Short name T743
Test name
Test status
Simulation time 31624910 ps
CPU time 1 seconds
Started Feb 28 06:00:35 PM PST 24
Finished Feb 28 06:00:36 PM PST 24
Peak memory 222208 kb
Host smart-a4c7c71d-63ea-4362-a4c3-a6ab3a727086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074895229 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3074895229
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.1013269962
Short name T48
Test name
Test status
Simulation time 28083620 ps
CPU time 1.05 seconds
Started Feb 28 06:00:30 PM PST 24
Finished Feb 28 06:00:31 PM PST 24
Peak memory 222524 kb
Host smart-55d43059-4d51-4bf4-a2bb-f93b778cd539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013269962 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1013269962
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.2748398872
Short name T536
Test name
Test status
Simulation time 20060437 ps
CPU time 1.06 seconds
Started Feb 28 06:00:31 PM PST 24
Finished Feb 28 06:00:32 PM PST 24
Peak memory 214696 kb
Host smart-164399cb-ca1d-4465-b8af-b50df702835d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748398872 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2748398872
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.3773165107
Short name T749
Test name
Test status
Simulation time 170127883 ps
CPU time 2.21 seconds
Started Feb 28 06:00:30 PM PST 24
Finished Feb 28 06:00:32 PM PST 24
Peak memory 215784 kb
Host smart-3775b7da-8528-4ff3-b10a-d03ea85c4f2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773165107 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3773165107
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2910737309
Short name T579
Test name
Test status
Simulation time 373660642223 ps
CPU time 1396.19 seconds
Started Feb 28 06:00:31 PM PST 24
Finished Feb 28 06:23:47 PM PST 24
Peak memory 221904 kb
Host smart-c4ad27bd-07db-4fdf-afb3-ce2aa87d249f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910737309 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2910737309
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.551953816
Short name T642
Test name
Test status
Simulation time 102018650 ps
CPU time 1.25 seconds
Started Feb 28 06:02:26 PM PST 24
Finished Feb 28 06:02:27 PM PST 24
Peak memory 215836 kb
Host smart-c63590a2-b4d6-4d86-8f6f-ef46a394349d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551953816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.551953816
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.1895509421
Short name T256
Test name
Test status
Simulation time 59556109 ps
CPU time 2.17 seconds
Started Feb 28 06:02:24 PM PST 24
Finished Feb 28 06:02:27 PM PST 24
Peak memory 217668 kb
Host smart-26ec8e57-1434-48ec-9dea-481a01651ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895509421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1895509421
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.1231396372
Short name T234
Test name
Test status
Simulation time 49083947 ps
CPU time 1.34 seconds
Started Feb 28 06:02:25 PM PST 24
Finished Feb 28 06:02:26 PM PST 24
Peak memory 217132 kb
Host smart-f924cf17-e240-4b95-a04c-360e4e2b68a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231396372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1231396372
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.2998980184
Short name T663
Test name
Test status
Simulation time 33538385 ps
CPU time 1.63 seconds
Started Feb 28 06:02:29 PM PST 24
Finished Feb 28 06:02:30 PM PST 24
Peak memory 217320 kb
Host smart-85c6941d-2f7c-49af-930d-526047588bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998980184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2998980184
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.2459925588
Short name T648
Test name
Test status
Simulation time 45424432 ps
CPU time 1.47 seconds
Started Feb 28 06:02:28 PM PST 24
Finished Feb 28 06:02:30 PM PST 24
Peak memory 217332 kb
Host smart-5fedda79-7141-41df-9d3a-07252b754672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459925588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2459925588
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.2606537338
Short name T456
Test name
Test status
Simulation time 25827297 ps
CPU time 1.24 seconds
Started Feb 28 06:02:25 PM PST 24
Finished Feb 28 06:02:27 PM PST 24
Peak memory 217236 kb
Host smart-6bb205a1-cd64-4255-914c-1c958bcd15ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606537338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2606537338
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3648874123
Short name T730
Test name
Test status
Simulation time 83454908 ps
CPU time 2.98 seconds
Started Feb 28 06:02:24 PM PST 24
Finished Feb 28 06:02:27 PM PST 24
Peak memory 217256 kb
Host smart-26c9c00d-dd75-430e-8459-4095bddbe838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648874123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3648874123
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1072794927
Short name T155
Test name
Test status
Simulation time 79645788 ps
CPU time 1.11 seconds
Started Feb 28 06:00:36 PM PST 24
Finished Feb 28 06:00:37 PM PST 24
Peak memory 215016 kb
Host smart-3cd20303-21d4-40e2-a953-bcd78ba06b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072794927 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1072794927
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2987936163
Short name T478
Test name
Test status
Simulation time 133237423 ps
CPU time 0.93 seconds
Started Feb 28 06:00:38 PM PST 24
Finished Feb 28 06:00:39 PM PST 24
Peak memory 206144 kb
Host smart-65a140ca-a177-4b1b-9250-1f082992300e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987936163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2987936163
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2041389603
Short name T101
Test name
Test status
Simulation time 35304048 ps
CPU time 0.86 seconds
Started Feb 28 06:00:38 PM PST 24
Finished Feb 28 06:00:39 PM PST 24
Peak memory 215340 kb
Host smart-796d8d8d-5baf-4b25-b6b0-11be2030a103
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041389603 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2041389603
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1984759842
Short name T88
Test name
Test status
Simulation time 38667334 ps
CPU time 1.35 seconds
Started Feb 28 06:00:35 PM PST 24
Finished Feb 28 06:00:36 PM PST 24
Peak memory 215876 kb
Host smart-f6f94bdd-2921-49a9-aa1b-f9baa35bc23e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984759842 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1984759842
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.453892361
Short name T238
Test name
Test status
Simulation time 18291290 ps
CPU time 1.01 seconds
Started Feb 28 06:00:33 PM PST 24
Finished Feb 28 06:00:34 PM PST 24
Peak memory 217556 kb
Host smart-f6bc9618-62f1-4971-80db-da300ae7ae1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453892361 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.453892361
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.766779245
Short name T420
Test name
Test status
Simulation time 122038521 ps
CPU time 2.97 seconds
Started Feb 28 06:00:33 PM PST 24
Finished Feb 28 06:00:36 PM PST 24
Peak memory 218780 kb
Host smart-58a5c767-aa87-468a-97b0-49df6bc62c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766779245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.766779245
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3289889020
Short name T658
Test name
Test status
Simulation time 30903256 ps
CPU time 0.95 seconds
Started Feb 28 06:00:36 PM PST 24
Finished Feb 28 06:00:37 PM PST 24
Peak memory 214768 kb
Host smart-c96ccbff-30da-43b6-acca-d3b910d4602e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289889020 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3289889020
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.336204137
Short name T689
Test name
Test status
Simulation time 21568676 ps
CPU time 0.96 seconds
Started Feb 28 06:00:34 PM PST 24
Finished Feb 28 06:00:35 PM PST 24
Peak memory 214840 kb
Host smart-d7058053-1421-46ef-9e44-9c51a7d2a4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336204137 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.336204137
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.526751584
Short name T58
Test name
Test status
Simulation time 178129332 ps
CPU time 4.24 seconds
Started Feb 28 06:00:33 PM PST 24
Finished Feb 28 06:00:38 PM PST 24
Peak memory 215744 kb
Host smart-5a7972c9-4a48-40a8-93df-b2f5f226ca83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526751584 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.526751584
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2961929900
Short name T619
Test name
Test status
Simulation time 98061581163 ps
CPU time 598.83 seconds
Started Feb 28 06:00:35 PM PST 24
Finished Feb 28 06:10:34 PM PST 24
Peak memory 218300 kb
Host smart-aab3686a-6879-4e12-8035-761cdbee8fe0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961929900 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2961929900
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.3510821563
Short name T589
Test name
Test status
Simulation time 27594574 ps
CPU time 1.16 seconds
Started Feb 28 06:02:23 PM PST 24
Finished Feb 28 06:02:25 PM PST 24
Peak memory 216120 kb
Host smart-80091f16-d0df-4345-8db9-743777702cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510821563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3510821563
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.2963823527
Short name T313
Test name
Test status
Simulation time 81886619 ps
CPU time 1.58 seconds
Started Feb 28 06:02:27 PM PST 24
Finished Feb 28 06:02:29 PM PST 24
Peak memory 217344 kb
Host smart-5cb88d0d-04af-441b-98a2-89fa2148f24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963823527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2963823527
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.1542461926
Short name T591
Test name
Test status
Simulation time 42042120 ps
CPU time 1.49 seconds
Started Feb 28 06:02:25 PM PST 24
Finished Feb 28 06:02:27 PM PST 24
Peak memory 216264 kb
Host smart-163c664c-e7bd-461c-95d4-ed4f6301594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542461926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1542461926
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2215798445
Short name T601
Test name
Test status
Simulation time 122139605 ps
CPU time 1.76 seconds
Started Feb 28 06:02:25 PM PST 24
Finished Feb 28 06:02:27 PM PST 24
Peak memory 217528 kb
Host smart-4e0461a2-5dda-4801-a328-bf9a8eb57fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215798445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2215798445
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.3399806527
Short name T375
Test name
Test status
Simulation time 37703060 ps
CPU time 1.5 seconds
Started Feb 28 06:02:29 PM PST 24
Finished Feb 28 06:02:30 PM PST 24
Peak memory 217216 kb
Host smart-25fd9dbf-a888-42a2-bcf3-7cb50c870bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399806527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3399806527
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.1314237642
Short name T518
Test name
Test status
Simulation time 48042069 ps
CPU time 1.04 seconds
Started Feb 28 06:02:28 PM PST 24
Finished Feb 28 06:02:30 PM PST 24
Peak memory 216036 kb
Host smart-fe6e31fe-2033-4b47-a45b-97355c4ac358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314237642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1314237642
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.2688303985
Short name T475
Test name
Test status
Simulation time 48976086 ps
CPU time 1.6 seconds
Started Feb 28 06:02:29 PM PST 24
Finished Feb 28 06:02:31 PM PST 24
Peak memory 216320 kb
Host smart-a861ab45-968f-4df5-a836-acbba8210308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688303985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2688303985
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.4013828888
Short name T765
Test name
Test status
Simulation time 148952009 ps
CPU time 1.17 seconds
Started Feb 28 06:02:28 PM PST 24
Finished Feb 28 06:02:29 PM PST 24
Peak memory 214684 kb
Host smart-4f6eb7d4-3940-4b73-9c0b-fecd68fa9f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013828888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.4013828888
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.2464371496
Short name T295
Test name
Test status
Simulation time 66901772 ps
CPU time 2.69 seconds
Started Feb 28 06:02:29 PM PST 24
Finished Feb 28 06:02:32 PM PST 24
Peak memory 217540 kb
Host smart-2302482f-6689-401a-b5af-ef0e479957f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464371496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2464371496
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.879512422
Short name T551
Test name
Test status
Simulation time 26343165 ps
CPU time 1.26 seconds
Started Feb 28 06:00:38 PM PST 24
Finished Feb 28 06:00:40 PM PST 24
Peak memory 215004 kb
Host smart-d1645320-37a2-4912-a432-78458b10dd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879512422 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.879512422
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3150487616
Short name T361
Test name
Test status
Simulation time 30621111 ps
CPU time 0.97 seconds
Started Feb 28 06:00:39 PM PST 24
Finished Feb 28 06:00:41 PM PST 24
Peak memory 206256 kb
Host smart-3a9205b7-6171-4619-aab7-35aa5a7c8e9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150487616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3150487616
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_err.3989647558
Short name T457
Test name
Test status
Simulation time 22839764 ps
CPU time 0.91 seconds
Started Feb 28 06:00:38 PM PST 24
Finished Feb 28 06:00:39 PM PST 24
Peak memory 217168 kb
Host smart-7db02143-ec3c-4d12-b221-7f2be66e0024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989647558 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3989647558
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_intr.3402884759
Short name T337
Test name
Test status
Simulation time 41870657 ps
CPU time 0.98 seconds
Started Feb 28 06:00:38 PM PST 24
Finished Feb 28 06:00:39 PM PST 24
Peak memory 222548 kb
Host smart-97be9849-92c8-4611-9a7c-b11ff3e59bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402884759 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3402884759
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.812491646
Short name T612
Test name
Test status
Simulation time 23978840 ps
CPU time 1.01 seconds
Started Feb 28 06:00:35 PM PST 24
Finished Feb 28 06:00:37 PM PST 24
Peak memory 214664 kb
Host smart-c7816adf-f4c6-48e3-9091-926a480b94b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812491646 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.812491646
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1962260503
Short name T2
Test name
Test status
Simulation time 434043099 ps
CPU time 3.57 seconds
Started Feb 28 06:00:38 PM PST 24
Finished Feb 28 06:00:41 PM PST 24
Peak memory 218388 kb
Host smart-88c74568-6752-4c2c-8eef-f7eb59e9d4e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962260503 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1962260503
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.133898190
Short name T187
Test name
Test status
Simulation time 200527715068 ps
CPU time 1377.99 seconds
Started Feb 28 06:00:38 PM PST 24
Finished Feb 28 06:23:37 PM PST 24
Peak memory 223160 kb
Host smart-7c0814a1-317c-4b92-a441-f9fc5afde0fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133898190 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.133898190
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.4224819778
Short name T584
Test name
Test status
Simulation time 48633030 ps
CPU time 1.22 seconds
Started Feb 28 06:02:27 PM PST 24
Finished Feb 28 06:02:28 PM PST 24
Peak memory 218632 kb
Host smart-7442af58-944c-4d02-b59c-b47e9c6e1f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224819778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.4224819778
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.417447006
Short name T498
Test name
Test status
Simulation time 32351948 ps
CPU time 1.32 seconds
Started Feb 28 06:02:28 PM PST 24
Finished Feb 28 06:02:29 PM PST 24
Peak memory 215992 kb
Host smart-5ea7307c-bd46-4f5f-b6b9-dc38b83ffe25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417447006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.417447006
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.2192180654
Short name T356
Test name
Test status
Simulation time 63472665 ps
CPU time 1.49 seconds
Started Feb 28 06:02:27 PM PST 24
Finished Feb 28 06:02:29 PM PST 24
Peak memory 217324 kb
Host smart-c8337849-4633-4fb1-ab8c-ed3bef5d53a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192180654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2192180654
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.1365888975
Short name T638
Test name
Test status
Simulation time 69567339 ps
CPU time 1.15 seconds
Started Feb 28 06:02:28 PM PST 24
Finished Feb 28 06:02:29 PM PST 24
Peak memory 215952 kb
Host smart-ae106a06-e801-4a6e-b4c4-f8eb1fe6db4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365888975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1365888975
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3710710153
Short name T693
Test name
Test status
Simulation time 50091981 ps
CPU time 1.27 seconds
Started Feb 28 06:02:27 PM PST 24
Finished Feb 28 06:02:28 PM PST 24
Peak memory 218644 kb
Host smart-01e1ad8f-a732-4782-a587-132dd1493ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710710153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3710710153
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.1780559373
Short name T554
Test name
Test status
Simulation time 77021753 ps
CPU time 3.14 seconds
Started Feb 28 06:02:29 PM PST 24
Finished Feb 28 06:02:32 PM PST 24
Peak memory 219176 kb
Host smart-24a8beb9-30a2-403d-955a-93c481cddbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780559373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1780559373
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.226965204
Short name T231
Test name
Test status
Simulation time 78152732 ps
CPU time 1.41 seconds
Started Feb 28 06:02:34 PM PST 24
Finished Feb 28 06:02:36 PM PST 24
Peak memory 217416 kb
Host smart-d691bd97-57a9-4831-a2cb-7dbfdd0209ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226965204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.226965204
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1591182047
Short name T399
Test name
Test status
Simulation time 39616365 ps
CPU time 1.14 seconds
Started Feb 28 06:02:32 PM PST 24
Finished Feb 28 06:02:33 PM PST 24
Peak memory 215888 kb
Host smart-60bda119-bd8a-45b3-89f8-11e4c2a1aafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591182047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1591182047
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.4139293261
Short name T347
Test name
Test status
Simulation time 53015203 ps
CPU time 1.49 seconds
Started Feb 28 06:02:32 PM PST 24
Finished Feb 28 06:02:34 PM PST 24
Peak memory 217468 kb
Host smart-a43087c9-e0e0-4498-b165-1bfa8b0e1210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139293261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.4139293261
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.4010469750
Short name T434
Test name
Test status
Simulation time 48990289 ps
CPU time 1.16 seconds
Started Feb 28 06:02:33 PM PST 24
Finished Feb 28 06:02:34 PM PST 24
Peak memory 215768 kb
Host smart-8ee2fed8-df70-450c-87c4-eb6fe536d9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010469750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.4010469750
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.2636364394
Short name T18
Test name
Test status
Simulation time 28786783 ps
CPU time 1.26 seconds
Started Feb 28 06:00:42 PM PST 24
Finished Feb 28 06:00:44 PM PST 24
Peak memory 214956 kb
Host smart-eab2863f-6520-469a-81b8-f007a8c3b5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636364394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2636364394
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.4213381888
Short name T453
Test name
Test status
Simulation time 75975453 ps
CPU time 0.87 seconds
Started Feb 28 06:00:44 PM PST 24
Finished Feb 28 06:00:45 PM PST 24
Peak memory 204864 kb
Host smart-939ac5b3-83ba-47e3-bbc7-703b8e3d1018
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213381888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.4213381888
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1873837246
Short name T699
Test name
Test status
Simulation time 16287192 ps
CPU time 0.82 seconds
Started Feb 28 06:00:43 PM PST 24
Finished Feb 28 06:00:44 PM PST 24
Peak memory 214812 kb
Host smart-e06e441d-d056-48ac-ac3e-bee79293a69e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873837246 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1873837246
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.2375619353
Short name T86
Test name
Test status
Simulation time 52580498 ps
CPU time 0.94 seconds
Started Feb 28 06:00:41 PM PST 24
Finished Feb 28 06:00:42 PM PST 24
Peak memory 218648 kb
Host smart-511dbac8-15e6-4eac-94e9-76e3cdf58edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375619353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2375619353
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3909105290
Short name T540
Test name
Test status
Simulation time 42582820 ps
CPU time 1.17 seconds
Started Feb 28 06:00:43 PM PST 24
Finished Feb 28 06:00:45 PM PST 24
Peak memory 218532 kb
Host smart-4a5681ec-dd73-4d96-bc6b-8f795f727566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909105290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3909105290
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_smoke.846958971
Short name T616
Test name
Test status
Simulation time 17195749 ps
CPU time 1.07 seconds
Started Feb 28 06:00:42 PM PST 24
Finished Feb 28 06:00:43 PM PST 24
Peak memory 214788 kb
Host smart-93519a7d-0640-43e9-a2ca-a99c3c460fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846958971 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.846958971
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.4273933197
Short name T408
Test name
Test status
Simulation time 346516445 ps
CPU time 5.46 seconds
Started Feb 28 06:00:41 PM PST 24
Finished Feb 28 06:00:46 PM PST 24
Peak memory 214696 kb
Host smart-c1108958-6413-4137-ad27-eaf96b1e6c78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273933197 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.4273933197
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3434483143
Short name T324
Test name
Test status
Simulation time 56525485286 ps
CPU time 336.63 seconds
Started Feb 28 06:00:42 PM PST 24
Finished Feb 28 06:06:19 PM PST 24
Peak memory 218052 kb
Host smart-29817117-acae-49bd-9bbe-df98cd07d6e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434483143 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3434483143
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.2054456622
Short name T355
Test name
Test status
Simulation time 81498057 ps
CPU time 2.79 seconds
Started Feb 28 06:02:32 PM PST 24
Finished Feb 28 06:02:35 PM PST 24
Peak memory 216312 kb
Host smart-a5b45617-fd76-43df-990c-f3d0e53d531c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054456622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2054456622
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.2613016420
Short name T317
Test name
Test status
Simulation time 51781108 ps
CPU time 1.01 seconds
Started Feb 28 06:02:32 PM PST 24
Finished Feb 28 06:02:33 PM PST 24
Peak memory 218336 kb
Host smart-30347ea9-1b2b-45e3-bddd-4a68a458fb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613016420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2613016420
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.1314720918
Short name T545
Test name
Test status
Simulation time 83580308 ps
CPU time 1.05 seconds
Started Feb 28 06:02:30 PM PST 24
Finished Feb 28 06:02:32 PM PST 24
Peak memory 215936 kb
Host smart-41b2e66e-b1b1-4061-9053-ecfd10a2640a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314720918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1314720918
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.1531589649
Short name T783
Test name
Test status
Simulation time 136502943 ps
CPU time 1.42 seconds
Started Feb 28 06:02:31 PM PST 24
Finished Feb 28 06:02:33 PM PST 24
Peak memory 214952 kb
Host smart-f1c40198-b192-4f1e-84e1-fa60dedc0b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531589649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1531589649
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.2223706777
Short name T595
Test name
Test status
Simulation time 114992003 ps
CPU time 1.45 seconds
Started Feb 28 06:02:34 PM PST 24
Finished Feb 28 06:02:36 PM PST 24
Peak memory 217616 kb
Host smart-cddf2a1a-10f1-4ee0-8a3b-7a855573ba26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223706777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2223706777
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.2675455296
Short name T350
Test name
Test status
Simulation time 131445752 ps
CPU time 2.1 seconds
Started Feb 28 06:02:33 PM PST 24
Finished Feb 28 06:02:36 PM PST 24
Peak memory 219036 kb
Host smart-27d1ec2e-90c5-47d6-a7d9-56bfc877feac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675455296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2675455296
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.1861264579
Short name T671
Test name
Test status
Simulation time 36083865 ps
CPU time 1.49 seconds
Started Feb 28 06:02:33 PM PST 24
Finished Feb 28 06:02:35 PM PST 24
Peak memory 217260 kb
Host smart-b3e09f27-fab0-4383-adee-eed7c2211036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861264579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1861264579
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.1154395521
Short name T470
Test name
Test status
Simulation time 31331196 ps
CPU time 1.27 seconds
Started Feb 28 06:02:34 PM PST 24
Finished Feb 28 06:02:36 PM PST 24
Peak memory 215960 kb
Host smart-3064c25c-7603-4418-abf9-e27045db415e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154395521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1154395521
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.3913879114
Short name T669
Test name
Test status
Simulation time 112026389 ps
CPU time 1.33 seconds
Started Feb 28 06:02:33 PM PST 24
Finished Feb 28 06:02:34 PM PST 24
Peak memory 218836 kb
Host smart-f6240a1c-4d67-47a9-8c46-1ca91209590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913879114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3913879114
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.2400146561
Short name T407
Test name
Test status
Simulation time 65720503 ps
CPU time 1.13 seconds
Started Feb 28 06:02:34 PM PST 24
Finished Feb 28 06:02:35 PM PST 24
Peak memory 217372 kb
Host smart-f465ec9f-7a21-47f2-a25e-000f3c1f0151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400146561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2400146561
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.110425646
Short name T779
Test name
Test status
Simulation time 30220766 ps
CPU time 1.27 seconds
Started Feb 28 06:00:46 PM PST 24
Finished Feb 28 06:00:49 PM PST 24
Peak memory 205600 kb
Host smart-cc3f58ae-bdbd-4eb8-bc46-c170fbd0e1cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110425646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.110425646
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1284323177
Short name T710
Test name
Test status
Simulation time 29860853 ps
CPU time 0.79 seconds
Started Feb 28 06:00:46 PM PST 24
Finished Feb 28 06:00:47 PM PST 24
Peak memory 215116 kb
Host smart-d20489f2-4876-41ba-a171-c8ae6a8f4a17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284323177 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1284323177
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.746723799
Short name T688
Test name
Test status
Simulation time 34617898 ps
CPU time 0.84 seconds
Started Feb 28 06:00:48 PM PST 24
Finished Feb 28 06:00:49 PM PST 24
Peak memory 216780 kb
Host smart-44aedca9-919d-4f7b-9af0-fde986a21454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746723799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.746723799
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2194838341
Short name T666
Test name
Test status
Simulation time 224755397 ps
CPU time 1.28 seconds
Started Feb 28 06:00:41 PM PST 24
Finished Feb 28 06:00:42 PM PST 24
Peak memory 217568 kb
Host smart-fe833f60-bd35-4ab0-b676-82aebd74b40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194838341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2194838341
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.442734810
Short name T490
Test name
Test status
Simulation time 25851898 ps
CPU time 1.18 seconds
Started Feb 28 06:00:46 PM PST 24
Finished Feb 28 06:00:48 PM PST 24
Peak memory 223936 kb
Host smart-4eb2baa2-dcb6-4abb-812e-4b4094e4dd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442734810 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.442734810
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2910806735
Short name T682
Test name
Test status
Simulation time 15405003 ps
CPU time 1.02 seconds
Started Feb 28 06:00:39 PM PST 24
Finished Feb 28 06:00:41 PM PST 24
Peak memory 214708 kb
Host smart-f58c2ed8-2686-433e-bb7c-5471772f8cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910806735 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2910806735
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.812214408
Short name T527
Test name
Test status
Simulation time 267716666 ps
CPU time 2.97 seconds
Started Feb 28 06:00:46 PM PST 24
Finished Feb 28 06:00:49 PM PST 24
Peak memory 215780 kb
Host smart-11e94b7c-62b0-4d3d-b732-e772690b9745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812214408 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.812214408
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1682140615
Short name T623
Test name
Test status
Simulation time 258612056416 ps
CPU time 453.03 seconds
Started Feb 28 06:00:47 PM PST 24
Finished Feb 28 06:08:21 PM PST 24
Peak memory 217656 kb
Host smart-e26108c7-f8f3-45b8-8808-968e0d30e333
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682140615 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1682140615
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.3974808164
Short name T339
Test name
Test status
Simulation time 41763694 ps
CPU time 1.57 seconds
Started Feb 28 06:02:34 PM PST 24
Finished Feb 28 06:02:36 PM PST 24
Peak memory 217056 kb
Host smart-3f8e625c-9a3e-4f80-b25f-81c712dbd522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974808164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3974808164
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.211334223
Short name T547
Test name
Test status
Simulation time 85345615 ps
CPU time 1.68 seconds
Started Feb 28 06:02:35 PM PST 24
Finished Feb 28 06:02:37 PM PST 24
Peak memory 217536 kb
Host smart-032a43b5-410a-4892-bf29-965c6ced70b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211334223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.211334223
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.2345206821
Short name T506
Test name
Test status
Simulation time 84915894 ps
CPU time 1.13 seconds
Started Feb 28 06:02:31 PM PST 24
Finished Feb 28 06:02:32 PM PST 24
Peak memory 217424 kb
Host smart-e3f717e7-6643-4917-9dd0-62b7c7dbb2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345206821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2345206821
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.1490210595
Short name T304
Test name
Test status
Simulation time 64937566 ps
CPU time 1.05 seconds
Started Feb 28 06:02:31 PM PST 24
Finished Feb 28 06:02:32 PM PST 24
Peak memory 215804 kb
Host smart-136e565c-4db1-40e6-8a1a-7d276cb4e821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490210595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1490210595
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.637833026
Short name T414
Test name
Test status
Simulation time 55928988 ps
CPU time 2.03 seconds
Started Feb 28 06:02:31 PM PST 24
Finished Feb 28 06:02:34 PM PST 24
Peak memory 217264 kb
Host smart-f5316081-2889-40f7-8848-9b35164fa4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637833026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.637833026
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.3634444299
Short name T690
Test name
Test status
Simulation time 197815641 ps
CPU time 1.64 seconds
Started Feb 28 06:02:37 PM PST 24
Finished Feb 28 06:02:39 PM PST 24
Peak memory 217756 kb
Host smart-9beb2bb2-6dc4-4557-b782-d89cb68c4660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634444299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3634444299
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.1797582603
Short name T409
Test name
Test status
Simulation time 42973727 ps
CPU time 1.11 seconds
Started Feb 28 06:02:37 PM PST 24
Finished Feb 28 06:02:39 PM PST 24
Peak memory 214832 kb
Host smart-5533f950-5359-46d0-8669-4ba9c89869d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797582603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1797582603
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.1546083483
Short name T348
Test name
Test status
Simulation time 44957460 ps
CPU time 1.23 seconds
Started Feb 28 06:02:35 PM PST 24
Finished Feb 28 06:02:37 PM PST 24
Peak memory 215900 kb
Host smart-e02db7e9-77f0-42f4-9787-0405cddb892a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546083483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1546083483
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.956805945
Short name T371
Test name
Test status
Simulation time 196627969 ps
CPU time 1.17 seconds
Started Feb 28 06:02:35 PM PST 24
Finished Feb 28 06:02:36 PM PST 24
Peak memory 217156 kb
Host smart-552dde40-5c33-4b8b-b6e1-f859c5071648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956805945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.956805945
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.1861127538
Short name T126
Test name
Test status
Simulation time 84084058 ps
CPU time 1.17 seconds
Started Feb 28 06:00:47 PM PST 24
Finished Feb 28 06:00:49 PM PST 24
Peak memory 214960 kb
Host smart-2ad92b2f-1cdc-4bb5-8aff-1299c11b446a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861127538 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.1861127538
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2823019121
Short name T778
Test name
Test status
Simulation time 17208070 ps
CPU time 0.97 seconds
Started Feb 28 06:00:45 PM PST 24
Finished Feb 28 06:00:46 PM PST 24
Peak memory 206292 kb
Host smart-0e341a6d-d8d3-477c-bf7b-c69861749a88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823019121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2823019121
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.97580098
Short name T129
Test name
Test status
Simulation time 13499506 ps
CPU time 0.83 seconds
Started Feb 28 06:00:47 PM PST 24
Finished Feb 28 06:00:49 PM PST 24
Peak memory 214892 kb
Host smart-dd7be28c-b3aa-4fca-ba51-1cfd8febb4b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97580098 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.97580098
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_intr.238589476
Short name T133
Test name
Test status
Simulation time 21111555 ps
CPU time 1.13 seconds
Started Feb 28 06:00:45 PM PST 24
Finished Feb 28 06:00:46 PM PST 24
Peak memory 215148 kb
Host smart-99559f53-9c71-45f8-816e-5c930df73cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238589476 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.238589476
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1562958234
Short name T139
Test name
Test status
Simulation time 26618461 ps
CPU time 0.92 seconds
Started Feb 28 06:00:46 PM PST 24
Finished Feb 28 06:00:49 PM PST 24
Peak memory 214700 kb
Host smart-df43edfe-fbcf-4675-b126-f40fd3a12b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562958234 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1562958234
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2132472636
Short name T556
Test name
Test status
Simulation time 52231611 ps
CPU time 1.53 seconds
Started Feb 28 06:00:45 PM PST 24
Finished Feb 28 06:00:48 PM PST 24
Peak memory 217060 kb
Host smart-105b12b5-0304-40d0-9135-8a4fc68cf6b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132472636 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2132472636
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2921093819
Short name T193
Test name
Test status
Simulation time 33631204589 ps
CPU time 450.14 seconds
Started Feb 28 06:00:47 PM PST 24
Finished Feb 28 06:08:18 PM PST 24
Peak memory 218940 kb
Host smart-f378868e-2ca4-45ca-bab3-a63fa31a2848
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921093819 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2921093819
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.3197878106
Short name T484
Test name
Test status
Simulation time 60488977 ps
CPU time 1.45 seconds
Started Feb 28 06:02:38 PM PST 24
Finished Feb 28 06:02:40 PM PST 24
Peak memory 217248 kb
Host smart-76cf048d-118b-4662-a2b8-e8fe21357195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197878106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3197878106
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.4232148475
Short name T561
Test name
Test status
Simulation time 71421985 ps
CPU time 1.06 seconds
Started Feb 28 06:02:34 PM PST 24
Finished Feb 28 06:02:36 PM PST 24
Peak memory 217600 kb
Host smart-5fb086e1-db81-4c06-8abf-81c25cfcf793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232148475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.4232148475
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.161547712
Short name T378
Test name
Test status
Simulation time 74014243 ps
CPU time 1.02 seconds
Started Feb 28 06:02:38 PM PST 24
Finished Feb 28 06:02:40 PM PST 24
Peak memory 215896 kb
Host smart-e759332f-2735-4d20-bf64-c078490034c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161547712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.161547712
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.1683569735
Short name T473
Test name
Test status
Simulation time 193701217 ps
CPU time 2.12 seconds
Started Feb 28 06:02:35 PM PST 24
Finished Feb 28 06:02:38 PM PST 24
Peak memory 218608 kb
Host smart-f695476f-08f9-4175-ab7a-5903b8833195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683569735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1683569735
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.3636397217
Short name T541
Test name
Test status
Simulation time 88062363 ps
CPU time 1.46 seconds
Started Feb 28 06:02:36 PM PST 24
Finished Feb 28 06:02:37 PM PST 24
Peak memory 217564 kb
Host smart-f95b1959-35d0-400b-bbcf-d72b202f1b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636397217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3636397217
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.1949392808
Short name T597
Test name
Test status
Simulation time 63886069 ps
CPU time 1.38 seconds
Started Feb 28 06:02:37 PM PST 24
Finished Feb 28 06:02:39 PM PST 24
Peak memory 216980 kb
Host smart-2ec755bb-59db-46dc-a542-4255ea388726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949392808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1949392808
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.2345905940
Short name T474
Test name
Test status
Simulation time 94247562 ps
CPU time 1.35 seconds
Started Feb 28 06:02:34 PM PST 24
Finished Feb 28 06:02:36 PM PST 24
Peak memory 217444 kb
Host smart-3c264745-1930-4ca5-b81c-cef97a33cff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345905940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2345905940
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.2853136131
Short name T607
Test name
Test status
Simulation time 88865370 ps
CPU time 1.54 seconds
Started Feb 28 06:02:33 PM PST 24
Finished Feb 28 06:02:35 PM PST 24
Peak memory 217856 kb
Host smart-cb0b454f-a1e6-4a0b-b961-94c9720dd90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853136131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2853136131
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.4070368044
Short name T29
Test name
Test status
Simulation time 100413428 ps
CPU time 1.24 seconds
Started Feb 28 06:02:37 PM PST 24
Finished Feb 28 06:02:38 PM PST 24
Peak memory 217464 kb
Host smart-ceb07c73-e16e-4b71-bfea-d464378eb6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070368044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.4070368044
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1736281818
Short name T720
Test name
Test status
Simulation time 68665839 ps
CPU time 1.12 seconds
Started Feb 28 06:00:49 PM PST 24
Finished Feb 28 06:00:50 PM PST 24
Peak memory 215108 kb
Host smart-58874756-e791-4955-aded-b33e1f193c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736281818 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1736281818
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3944131876
Short name T751
Test name
Test status
Simulation time 14796168 ps
CPU time 0.88 seconds
Started Feb 28 06:00:49 PM PST 24
Finished Feb 28 06:00:50 PM PST 24
Peak memory 205300 kb
Host smart-8896de4e-6413-475f-a95c-e15741f6cc8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944131876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3944131876
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.2244790163
Short name T305
Test name
Test status
Simulation time 32069040 ps
CPU time 0.86 seconds
Started Feb 28 06:00:48 PM PST 24
Finished Feb 28 06:00:49 PM PST 24
Peak memory 214884 kb
Host smart-59192d47-3991-46eb-abd3-ca089e05814d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244790163 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2244790163
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2367437152
Short name T836
Test name
Test status
Simulation time 39430215 ps
CPU time 0.98 seconds
Started Feb 28 06:00:48 PM PST 24
Finished Feb 28 06:00:49 PM PST 24
Peak memory 215764 kb
Host smart-38e9d9c1-bd68-4ee0-a156-8ba64424c994
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367437152 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2367437152
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.618213632
Short name T421
Test name
Test status
Simulation time 27297005 ps
CPU time 1.14 seconds
Started Feb 28 06:00:47 PM PST 24
Finished Feb 28 06:00:49 PM PST 24
Peak memory 217388 kb
Host smart-022a0aa4-0e74-4b1a-8859-577025f5c985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618213632 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.618213632
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2735119060
Short name T140
Test name
Test status
Simulation time 29440235 ps
CPU time 1.02 seconds
Started Feb 28 06:00:48 PM PST 24
Finished Feb 28 06:00:50 PM PST 24
Peak memory 215840 kb
Host smart-30fce637-0b92-4fbe-a2dc-0a0282f0221a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735119060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2735119060
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.573939214
Short name T553
Test name
Test status
Simulation time 32536873 ps
CPU time 0.94 seconds
Started Feb 28 06:00:49 PM PST 24
Finished Feb 28 06:00:50 PM PST 24
Peak memory 214664 kb
Host smart-b2410487-70fa-41c3-a152-f89da0c6270b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573939214 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.573939214
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.1887087560
Short name T309
Test name
Test status
Simulation time 130083697 ps
CPU time 0.81 seconds
Started Feb 28 06:00:48 PM PST 24
Finished Feb 28 06:00:49 PM PST 24
Peak memory 214676 kb
Host smart-bda0ff3b-ba7a-409c-9708-d78449c0b4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887087560 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1887087560
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3453887302
Short name T678
Test name
Test status
Simulation time 191659687 ps
CPU time 4.08 seconds
Started Feb 28 06:00:47 PM PST 24
Finished Feb 28 06:00:52 PM PST 24
Peak memory 214764 kb
Host smart-a2ca0462-ad13-4938-9311-3a6809d60428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453887302 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3453887302
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/170.edn_genbits.1077664145
Short name T316
Test name
Test status
Simulation time 49912628 ps
CPU time 1.58 seconds
Started Feb 28 06:02:40 PM PST 24
Finished Feb 28 06:02:42 PM PST 24
Peak memory 217184 kb
Host smart-eb162ca6-58df-4ff9-8039-fc546ef22a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077664145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1077664145
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.2637062352
Short name T524
Test name
Test status
Simulation time 213458838 ps
CPU time 3.06 seconds
Started Feb 28 06:02:38 PM PST 24
Finished Feb 28 06:02:42 PM PST 24
Peak memory 216348 kb
Host smart-61e2a974-14b9-43e5-8aa8-7ce2a1b71fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637062352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2637062352
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.2761687113
Short name T814
Test name
Test status
Simulation time 53560531 ps
CPU time 1.65 seconds
Started Feb 28 06:02:38 PM PST 24
Finished Feb 28 06:02:40 PM PST 24
Peak memory 217280 kb
Host smart-a22ec439-f3b1-42d2-a24c-e9c0bad665b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761687113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2761687113
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.252858335
Short name T686
Test name
Test status
Simulation time 134917692 ps
CPU time 2.47 seconds
Started Feb 28 06:02:43 PM PST 24
Finished Feb 28 06:02:46 PM PST 24
Peak memory 218224 kb
Host smart-04d358f3-c546-4b08-b45d-4291c302e40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252858335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.252858335
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.1509854316
Short name T435
Test name
Test status
Simulation time 63421392 ps
CPU time 1.24 seconds
Started Feb 28 06:02:37 PM PST 24
Finished Feb 28 06:02:39 PM PST 24
Peak memory 217312 kb
Host smart-6c72c052-8119-42e6-bbb8-cb8a9ae0174d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509854316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.1509854316
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.3826279946
Short name T265
Test name
Test status
Simulation time 34669120 ps
CPU time 1.29 seconds
Started Feb 28 06:02:43 PM PST 24
Finished Feb 28 06:02:44 PM PST 24
Peak memory 217600 kb
Host smart-5f7f86b4-4a59-489c-aa8d-ba29ccf158a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826279946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3826279946
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.3342366984
Short name T674
Test name
Test status
Simulation time 27945913 ps
CPU time 1.23 seconds
Started Feb 28 06:02:37 PM PST 24
Finished Feb 28 06:02:38 PM PST 24
Peak memory 215944 kb
Host smart-8b061605-4892-459b-bc37-6af8d1c086db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342366984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3342366984
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.3764221670
Short name T255
Test name
Test status
Simulation time 53961205 ps
CPU time 1.31 seconds
Started Feb 28 06:02:37 PM PST 24
Finished Feb 28 06:02:39 PM PST 24
Peak memory 215936 kb
Host smart-edb5989e-9568-4082-947e-00dd822192f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764221670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3764221670
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.1033432518
Short name T388
Test name
Test status
Simulation time 294738083 ps
CPU time 2.86 seconds
Started Feb 28 06:02:41 PM PST 24
Finished Feb 28 06:02:44 PM PST 24
Peak memory 218992 kb
Host smart-43a51bf6-5c59-44a9-90fb-80e3f3d33545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033432518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1033432518
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.1835858393
Short name T586
Test name
Test status
Simulation time 74998471 ps
CPU time 1.15 seconds
Started Feb 28 06:02:40 PM PST 24
Finished Feb 28 06:02:41 PM PST 24
Peak memory 217064 kb
Host smart-9c7b8265-d9a7-4f37-a271-b5ea407de9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835858393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1835858393
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.2270415825
Short name T819
Test name
Test status
Simulation time 19034928 ps
CPU time 0.95 seconds
Started Feb 28 06:00:53 PM PST 24
Finished Feb 28 06:00:54 PM PST 24
Peak memory 206244 kb
Host smart-aa1f8eac-6c2f-4257-ae4d-f5e114018491
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270415825 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2270415825
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3306172439
Short name T341
Test name
Test status
Simulation time 20636571 ps
CPU time 0.88 seconds
Started Feb 28 06:00:51 PM PST 24
Finished Feb 28 06:00:53 PM PST 24
Peak memory 214824 kb
Host smart-b76c2703-579b-489b-aee6-4e90cc260834
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306172439 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3306172439
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2442596058
Short name T492
Test name
Test status
Simulation time 39283617 ps
CPU time 0.85 seconds
Started Feb 28 06:00:53 PM PST 24
Finished Feb 28 06:00:54 PM PST 24
Peak memory 215548 kb
Host smart-3739a36e-5fb1-4498-9ed8-0d2ec38f7659
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442596058 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2442596058
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2009804565
Short name T167
Test name
Test status
Simulation time 34999681 ps
CPU time 0.89 seconds
Started Feb 28 06:00:54 PM PST 24
Finished Feb 28 06:00:55 PM PST 24
Peak memory 217312 kb
Host smart-796e83a4-d058-42ea-9685-35006a752240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009804565 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2009804565
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.719874663
Short name T808
Test name
Test status
Simulation time 70226397 ps
CPU time 0.99 seconds
Started Feb 28 06:00:50 PM PST 24
Finished Feb 28 06:00:51 PM PST 24
Peak memory 216032 kb
Host smart-d7dc2d95-5099-4181-bec9-f3ff7bc356aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719874663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.719874663
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_smoke.2432600631
Short name T657
Test name
Test status
Simulation time 16303919 ps
CPU time 0.96 seconds
Started Feb 28 06:00:51 PM PST 24
Finished Feb 28 06:00:52 PM PST 24
Peak memory 214724 kb
Host smart-9d322225-7127-4a9f-acdd-8c32afa54a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432600631 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2432600631
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1673564166
Short name T389
Test name
Test status
Simulation time 205809503 ps
CPU time 2.49 seconds
Started Feb 28 06:00:48 PM PST 24
Finished Feb 28 06:00:51 PM PST 24
Peak memory 214796 kb
Host smart-676f85a1-7d2e-4f68-9e0b-526a9a9e4fee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673564166 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1673564166
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/180.edn_genbits.201033754
Short name T307
Test name
Test status
Simulation time 43430013 ps
CPU time 1.07 seconds
Started Feb 28 06:02:38 PM PST 24
Finished Feb 28 06:02:39 PM PST 24
Peak memory 215976 kb
Host smart-f16f066c-9c42-4e7e-a918-30e72657b0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201033754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.201033754
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.213120044
Short name T530
Test name
Test status
Simulation time 269477023 ps
CPU time 3.64 seconds
Started Feb 28 06:04:44 PM PST 24
Finished Feb 28 06:04:48 PM PST 24
Peak memory 217128 kb
Host smart-5f6f38a6-fdb4-4fb6-bba1-48c27c6f01db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213120044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.213120044
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.1345988877
Short name T365
Test name
Test status
Simulation time 38800897 ps
CPU time 1.33 seconds
Started Feb 28 06:02:40 PM PST 24
Finished Feb 28 06:02:41 PM PST 24
Peak memory 218116 kb
Host smart-7ecec2b9-09ef-41da-bd94-ea37150b8d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345988877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1345988877
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.1780762746
Short name T771
Test name
Test status
Simulation time 55945667 ps
CPU time 1.53 seconds
Started Feb 28 06:02:38 PM PST 24
Finished Feb 28 06:02:40 PM PST 24
Peak memory 217272 kb
Host smart-a82baaed-c5df-4df2-bb03-f83ed2a6e4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780762746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1780762746
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.1703118698
Short name T269
Test name
Test status
Simulation time 42028259 ps
CPU time 1.2 seconds
Started Feb 28 06:02:36 PM PST 24
Finished Feb 28 06:02:38 PM PST 24
Peak memory 217184 kb
Host smart-7965995e-9cf4-4ee5-8369-4998f1d5e10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703118698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1703118698
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.547126332
Short name T360
Test name
Test status
Simulation time 37293252 ps
CPU time 1.32 seconds
Started Feb 28 06:02:43 PM PST 24
Finished Feb 28 06:02:44 PM PST 24
Peak memory 216992 kb
Host smart-df3d7668-04ac-4886-8247-e00f4af95036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547126332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.547126332
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.1448651832
Short name T610
Test name
Test status
Simulation time 149023376 ps
CPU time 3.03 seconds
Started Feb 28 06:04:44 PM PST 24
Finished Feb 28 06:04:47 PM PST 24
Peak memory 217800 kb
Host smart-8eca79b4-7a2d-4827-ae3d-0b9852832c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448651832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1448651832
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.3307315937
Short name T471
Test name
Test status
Simulation time 67393694 ps
CPU time 1.33 seconds
Started Feb 28 06:02:38 PM PST 24
Finished Feb 28 06:02:40 PM PST 24
Peak memory 217000 kb
Host smart-4360b1d6-3f62-4ba2-9466-dc2f4bfd17a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307315937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3307315937
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.2505578058
Short name T260
Test name
Test status
Simulation time 52512550 ps
CPU time 1.82 seconds
Started Feb 28 06:02:41 PM PST 24
Finished Feb 28 06:02:43 PM PST 24
Peak memory 215868 kb
Host smart-0e429ef9-4adb-4e78-a476-e8050ac243d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505578058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2505578058
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.2918407578
Short name T555
Test name
Test status
Simulation time 28098970 ps
CPU time 1.25 seconds
Started Feb 28 06:04:27 PM PST 24
Finished Feb 28 06:04:29 PM PST 24
Peak memory 215088 kb
Host smart-13690031-da53-4c4a-89e7-cb13d2cee34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918407578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2918407578
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1586462189
Short name T441
Test name
Test status
Simulation time 50373055 ps
CPU time 1.19 seconds
Started Feb 28 06:00:51 PM PST 24
Finished Feb 28 06:00:52 PM PST 24
Peak memory 215028 kb
Host smart-38476f05-9cbf-4cd5-933e-399f16f6f5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586462189 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1586462189
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3507561044
Short name T562
Test name
Test status
Simulation time 45517805 ps
CPU time 0.86 seconds
Started Feb 28 06:00:55 PM PST 24
Finished Feb 28 06:00:56 PM PST 24
Peak memory 205384 kb
Host smart-154e99cf-facf-4c74-9cf2-23af3ef217d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507561044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3507561044
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.4164484972
Short name T781
Test name
Test status
Simulation time 22124140 ps
CPU time 0.89 seconds
Started Feb 28 06:00:56 PM PST 24
Finished Feb 28 06:00:57 PM PST 24
Peak memory 215080 kb
Host smart-726b8991-d2b3-4125-8717-87796832b255
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164484972 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.4164484972
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2971198440
Short name T89
Test name
Test status
Simulation time 62058817 ps
CPU time 1.15 seconds
Started Feb 28 06:00:55 PM PST 24
Finished Feb 28 06:00:57 PM PST 24
Peak memory 215800 kb
Host smart-aaa9d977-801b-4fa5-83ad-3acab88fb5b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971198440 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2971198440
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2563498418
Short name T386
Test name
Test status
Simulation time 51850103 ps
CPU time 0.95 seconds
Started Feb 28 06:00:55 PM PST 24
Finished Feb 28 06:00:56 PM PST 24
Peak memory 218644 kb
Host smart-bd179822-c969-4e30-ade6-8fc3ce7085ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563498418 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2563498418
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.4042699687
Short name T287
Test name
Test status
Simulation time 83235622 ps
CPU time 3.32 seconds
Started Feb 28 06:00:52 PM PST 24
Finished Feb 28 06:00:55 PM PST 24
Peak memory 217392 kb
Host smart-a21e4bbe-7682-44c0-b72f-ed9e53c19521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042699687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.4042699687
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.4031251583
Short name T5
Test name
Test status
Simulation time 26215754 ps
CPU time 0.98 seconds
Started Feb 28 06:00:52 PM PST 24
Finished Feb 28 06:00:53 PM PST 24
Peak memory 214780 kb
Host smart-48a30f9e-f79e-432b-9677-49b7c2cad439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031251583 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.4031251583
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1888203964
Short name T558
Test name
Test status
Simulation time 29012543 ps
CPU time 1.02 seconds
Started Feb 28 06:00:54 PM PST 24
Finished Feb 28 06:00:56 PM PST 24
Peak memory 214692 kb
Host smart-5ad45642-b8bd-4a2e-98e7-0153761b453f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888203964 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1888203964
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3216831082
Short name T469
Test name
Test status
Simulation time 470028777 ps
CPU time 4.58 seconds
Started Feb 28 06:00:49 PM PST 24
Finished Feb 28 06:00:54 PM PST 24
Peak memory 217204 kb
Host smart-cdb04026-d26b-48c9-b492-d0ad3a4c81b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216831082 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3216831082
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.227019398
Short name T189
Test name
Test status
Simulation time 55725397809 ps
CPU time 1421.16 seconds
Started Feb 28 06:00:53 PM PST 24
Finished Feb 28 06:24:34 PM PST 24
Peak memory 223304 kb
Host smart-0319129e-d405-4bd9-b9c0-d7f9acb1123e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227019398 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.227019398
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.171213937
Short name T517
Test name
Test status
Simulation time 258514431 ps
CPU time 3.73 seconds
Started Feb 28 06:02:40 PM PST 24
Finished Feb 28 06:02:44 PM PST 24
Peak memory 216220 kb
Host smart-5cef42a1-2ef2-4b9e-9172-570333d79281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171213937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.171213937
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.448340645
Short name T278
Test name
Test status
Simulation time 69482446 ps
CPU time 1.43 seconds
Started Feb 28 06:04:44 PM PST 24
Finished Feb 28 06:04:46 PM PST 24
Peak memory 217180 kb
Host smart-410e73d5-a500-4c36-8337-d4f01f1daebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448340645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.448340645
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.656156798
Short name T549
Test name
Test status
Simulation time 40192566 ps
CPU time 1.17 seconds
Started Feb 28 06:02:41 PM PST 24
Finished Feb 28 06:02:42 PM PST 24
Peak memory 216336 kb
Host smart-e1db4373-4dec-4916-8d01-0321ef04ef23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656156798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.656156798
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.1007147433
Short name T263
Test name
Test status
Simulation time 74603238 ps
CPU time 1.73 seconds
Started Feb 28 06:02:38 PM PST 24
Finished Feb 28 06:02:40 PM PST 24
Peak memory 217292 kb
Host smart-37ca04e7-1106-4ca1-aa69-3c1012e62838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007147433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1007147433
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.3768160614
Short name T802
Test name
Test status
Simulation time 109630298 ps
CPU time 2.38 seconds
Started Feb 28 06:02:38 PM PST 24
Finished Feb 28 06:02:41 PM PST 24
Peak memory 217952 kb
Host smart-b002dadd-8bc1-47b4-929f-34dc1e27acf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768160614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3768160614
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.862778516
Short name T178
Test name
Test status
Simulation time 115980347 ps
CPU time 1.68 seconds
Started Feb 28 06:02:40 PM PST 24
Finished Feb 28 06:02:42 PM PST 24
Peak memory 217476 kb
Host smart-d7d4efc0-91a1-404a-96bd-8a53487f63cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862778516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.862778516
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.935277313
Short name T283
Test name
Test status
Simulation time 74102864 ps
CPU time 2.61 seconds
Started Feb 28 06:04:43 PM PST 24
Finished Feb 28 06:04:46 PM PST 24
Peak memory 218528 kb
Host smart-72c73582-649f-4e9e-9879-55060b6da4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935277313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.935277313
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.3630202413
Short name T357
Test name
Test status
Simulation time 105158498 ps
CPU time 1.33 seconds
Started Feb 28 06:02:43 PM PST 24
Finished Feb 28 06:02:44 PM PST 24
Peak memory 216056 kb
Host smart-6cedd234-05ab-4fa3-8f7e-6183d1ccf90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630202413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3630202413
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2254966038
Short name T152
Test name
Test status
Simulation time 41795526 ps
CPU time 1.23 seconds
Started Feb 28 05:59:56 PM PST 24
Finished Feb 28 05:59:57 PM PST 24
Peak memory 215024 kb
Host smart-129e8d2a-770b-4d21-9b78-f165afcdde33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254966038 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2254966038
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.605067597
Short name T625
Test name
Test status
Simulation time 39648045 ps
CPU time 0.92 seconds
Started Feb 28 06:00:01 PM PST 24
Finished Feb 28 06:00:02 PM PST 24
Peak memory 206296 kb
Host smart-1769a15c-84e5-4b6c-9ada-5345efbe7dad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605067597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.605067597
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1749078863
Short name T482
Test name
Test status
Simulation time 11488485 ps
CPU time 0.87 seconds
Started Feb 28 05:59:59 PM PST 24
Finished Feb 28 06:00:00 PM PST 24
Peak memory 214824 kb
Host smart-befd3afb-dbc2-49fb-9c2f-522754489bcc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749078863 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1749078863
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3703474571
Short name T358
Test name
Test status
Simulation time 26374842 ps
CPU time 1.04 seconds
Started Feb 28 05:59:59 PM PST 24
Finished Feb 28 06:00:00 PM PST 24
Peak memory 215856 kb
Host smart-810623f8-402a-4035-8001-4a10cfe255b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703474571 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3703474571
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.134345477
Short name T833
Test name
Test status
Simulation time 32727885 ps
CPU time 0.9 seconds
Started Feb 28 06:00:01 PM PST 24
Finished Feb 28 06:00:02 PM PST 24
Peak memory 217080 kb
Host smart-91fdd1c1-e9f7-435a-b5e8-d0596011bf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134345477 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.134345477
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1493634269
Short name T733
Test name
Test status
Simulation time 81704060 ps
CPU time 1.09 seconds
Started Feb 28 05:59:56 PM PST 24
Finished Feb 28 05:59:57 PM PST 24
Peak memory 216100 kb
Host smart-d04cdeee-8f32-4ee6-b8c3-43ddcf4d86af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493634269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1493634269
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3207050625
Short name T429
Test name
Test status
Simulation time 49461112 ps
CPU time 0.83 seconds
Started Feb 28 05:59:57 PM PST 24
Finished Feb 28 05:59:58 PM PST 24
Peak memory 214688 kb
Host smart-db6aaf52-3424-4c2d-88c2-f0a3ded44612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207050625 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3207050625
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3874769604
Short name T54
Test name
Test status
Simulation time 376430905 ps
CPU time 3.84 seconds
Started Feb 28 06:00:00 PM PST 24
Finished Feb 28 06:00:04 PM PST 24
Peak memory 234124 kb
Host smart-1cd345cc-5d94-4b24-b113-ff2df83fc3d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874769604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3874769604
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3047040983
Short name T196
Test name
Test status
Simulation time 27567966 ps
CPU time 0.91 seconds
Started Feb 28 05:59:56 PM PST 24
Finished Feb 28 05:59:57 PM PST 24
Peak memory 206516 kb
Host smart-ffc49d6b-7901-45fc-9ab4-df6aec691b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047040983 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3047040983
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2126429007
Short name T382
Test name
Test status
Simulation time 456183556 ps
CPU time 4.93 seconds
Started Feb 28 05:59:55 PM PST 24
Finished Feb 28 06:00:00 PM PST 24
Peak memory 214712 kb
Host smart-caef4090-c73d-43f3-ac1f-27d57640e892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126429007 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2126429007
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3788575756
Short name T63
Test name
Test status
Simulation time 309060936080 ps
CPU time 1788.48 seconds
Started Feb 28 05:59:56 PM PST 24
Finished Feb 28 06:29:44 PM PST 24
Peak memory 224132 kb
Host smart-514441ae-f4e9-46a3-8cb9-e1e08d177d6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788575756 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3788575756
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3580391690
Short name T639
Test name
Test status
Simulation time 29450370 ps
CPU time 1.3 seconds
Started Feb 28 06:00:57 PM PST 24
Finished Feb 28 06:00:59 PM PST 24
Peak memory 215104 kb
Host smart-8e7d50aa-4b06-49f0-b891-87f1063c4298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580391690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3580391690
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3508797725
Short name T564
Test name
Test status
Simulation time 22410390 ps
CPU time 1.13 seconds
Started Feb 28 06:00:59 PM PST 24
Finished Feb 28 06:01:00 PM PST 24
Peak memory 206312 kb
Host smart-0b4c2cdc-02ee-4b72-9902-9328a8931ab6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508797725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3508797725
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3526213852
Short name T797
Test name
Test status
Simulation time 27899875 ps
CPU time 1.12 seconds
Started Feb 28 06:00:59 PM PST 24
Finished Feb 28 06:01:00 PM PST 24
Peak memory 215888 kb
Host smart-c8198166-9131-4245-acf9-6e8e34cfb2f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526213852 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3526213852
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2337725698
Short name T665
Test name
Test status
Simulation time 27767527 ps
CPU time 0.97 seconds
Started Feb 28 06:00:59 PM PST 24
Finished Feb 28 06:01:00 PM PST 24
Peak memory 222184 kb
Host smart-39076be2-ed51-45c3-ba8c-450cf48ea562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337725698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2337725698
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1240863444
Short name T332
Test name
Test status
Simulation time 98719422 ps
CPU time 1.24 seconds
Started Feb 28 06:00:54 PM PST 24
Finished Feb 28 06:00:56 PM PST 24
Peak memory 217928 kb
Host smart-d0667b23-00df-421b-a3c4-3d2c7934e098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240863444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1240863444
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.4169307485
Short name T413
Test name
Test status
Simulation time 107621938 ps
CPU time 0.88 seconds
Started Feb 28 06:00:56 PM PST 24
Finished Feb 28 06:00:57 PM PST 24
Peak memory 214792 kb
Host smart-c7afc1a9-8306-4181-9a0e-96b5e01e61dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169307485 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.4169307485
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1792224705
Short name T150
Test name
Test status
Simulation time 48089663 ps
CPU time 0.91 seconds
Started Feb 28 06:00:58 PM PST 24
Finished Feb 28 06:00:59 PM PST 24
Peak memory 214704 kb
Host smart-469d21a4-57b9-45ab-a979-85430d8d27d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792224705 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1792224705
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3601789988
Short name T832
Test name
Test status
Simulation time 239500700 ps
CPU time 1.75 seconds
Started Feb 28 06:00:54 PM PST 24
Finished Feb 28 06:00:57 PM PST 24
Peak memory 215920 kb
Host smart-0835db69-41f7-42f6-bcac-6f08cf88a2d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601789988 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3601789988
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2557591688
Short name T190
Test name
Test status
Simulation time 70299185090 ps
CPU time 805.05 seconds
Started Feb 28 06:00:58 PM PST 24
Finished Feb 28 06:14:23 PM PST 24
Peak memory 218972 kb
Host smart-7528528e-8b38-4026-9156-5f35b9c077de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557591688 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2557591688
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2491370942
Short name T282
Test name
Test status
Simulation time 72721317 ps
CPU time 1.29 seconds
Started Feb 28 06:02:44 PM PST 24
Finished Feb 28 06:02:46 PM PST 24
Peak memory 216012 kb
Host smart-ba3d2c8c-0338-4ef5-985a-9855cda96a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491370942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2491370942
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3930777188
Short name T627
Test name
Test status
Simulation time 52877739 ps
CPU time 1.33 seconds
Started Feb 28 06:02:41 PM PST 24
Finished Feb 28 06:02:43 PM PST 24
Peak memory 217276 kb
Host smart-22ae5b74-9b13-45d4-8e3c-614cd639638d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930777188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3930777188
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1531942775
Short name T752
Test name
Test status
Simulation time 37892750 ps
CPU time 1.49 seconds
Started Feb 28 06:04:27 PM PST 24
Finished Feb 28 06:04:29 PM PST 24
Peak memory 215212 kb
Host smart-b972062d-2be5-4abf-9257-c43861a57318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531942775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1531942775
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.4175941621
Short name T233
Test name
Test status
Simulation time 38262415 ps
CPU time 1.41 seconds
Started Feb 28 06:02:41 PM PST 24
Finished Feb 28 06:02:42 PM PST 24
Peak memory 218460 kb
Host smart-90089864-6680-413f-9c3e-7a613dd6f142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175941621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.4175941621
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2616850082
Short name T268
Test name
Test status
Simulation time 55098562 ps
CPU time 1.78 seconds
Started Feb 28 06:02:41 PM PST 24
Finished Feb 28 06:02:43 PM PST 24
Peak memory 216112 kb
Host smart-0ee6c5ee-f4e9-4670-9cb4-bdc3a8573e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616850082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2616850082
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1219321308
Short name T787
Test name
Test status
Simulation time 369209960 ps
CPU time 1.55 seconds
Started Feb 28 06:02:41 PM PST 24
Finished Feb 28 06:02:43 PM PST 24
Peak memory 216236 kb
Host smart-aad9b546-231e-4906-ba9a-df81a9a90f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219321308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1219321308
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2094897062
Short name T377
Test name
Test status
Simulation time 63911369 ps
CPU time 1.17 seconds
Started Feb 28 06:04:44 PM PST 24
Finished Feb 28 06:04:45 PM PST 24
Peak memory 216856 kb
Host smart-8ed42bda-78b8-44f0-915a-3f172dafa5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094897062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2094897062
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3428520765
Short name T338
Test name
Test status
Simulation time 40511183 ps
CPU time 1.49 seconds
Started Feb 28 06:02:41 PM PST 24
Finished Feb 28 06:02:43 PM PST 24
Peak memory 217232 kb
Host smart-b4536a87-1179-4a49-b63a-1f825d026102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428520765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3428520765
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.878673360
Short name T331
Test name
Test status
Simulation time 34818237 ps
CPU time 1.15 seconds
Started Feb 28 06:02:44 PM PST 24
Finished Feb 28 06:02:45 PM PST 24
Peak memory 217460 kb
Host smart-8bf4f2a3-5808-48ec-b4ef-884a37bd2245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878673360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.878673360
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2718777949
Short name T258
Test name
Test status
Simulation time 35265354 ps
CPU time 1.51 seconds
Started Feb 28 06:02:40 PM PST 24
Finished Feb 28 06:02:42 PM PST 24
Peak memory 217176 kb
Host smart-c965d4ed-a1c7-4358-be42-062e75c3efbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718777949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2718777949
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3788823614
Short name T154
Test name
Test status
Simulation time 37508875 ps
CPU time 1.17 seconds
Started Feb 28 06:01:02 PM PST 24
Finished Feb 28 06:01:03 PM PST 24
Peak memory 215028 kb
Host smart-332735da-33b1-4e3d-984b-c995e071024d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788823614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3788823614
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2089020178
Short name T57
Test name
Test status
Simulation time 25474405 ps
CPU time 1.05 seconds
Started Feb 28 06:00:59 PM PST 24
Finished Feb 28 06:01:01 PM PST 24
Peak memory 205740 kb
Host smart-bc8b7b73-3ade-4825-a5c5-420fd16d1ae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089020178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2089020178
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.642416129
Short name T466
Test name
Test status
Simulation time 73842452 ps
CPU time 0.86 seconds
Started Feb 28 06:01:01 PM PST 24
Finished Feb 28 06:01:02 PM PST 24
Peak memory 206596 kb
Host smart-a1354241-85d2-4843-b8e3-9d31171a5c68
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642416129 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.642416129
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_err.1737800868
Short name T111
Test name
Test status
Simulation time 25028944 ps
CPU time 0.88 seconds
Started Feb 28 06:00:58 PM PST 24
Finished Feb 28 06:00:59 PM PST 24
Peak memory 217132 kb
Host smart-43343b88-75b3-4f42-9a21-6ae4f5b5fe45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737800868 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1737800868
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2921484052
Short name T774
Test name
Test status
Simulation time 87093567 ps
CPU time 1.32 seconds
Started Feb 28 06:01:02 PM PST 24
Finished Feb 28 06:01:04 PM PST 24
Peak memory 217504 kb
Host smart-9489b360-4c11-4bc3-bff0-f08bbf011ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921484052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2921484052
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3323841988
Short name T349
Test name
Test status
Simulation time 38823861 ps
CPU time 1.07 seconds
Started Feb 28 06:01:02 PM PST 24
Finished Feb 28 06:01:04 PM PST 24
Peak memory 222488 kb
Host smart-0af38838-61b3-4b66-bd93-f9a081e19736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323841988 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3323841988
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2268606564
Short name T494
Test name
Test status
Simulation time 17209958 ps
CPU time 0.93 seconds
Started Feb 28 06:00:59 PM PST 24
Finished Feb 28 06:01:00 PM PST 24
Peak memory 214676 kb
Host smart-7c3c4e5f-1207-4584-9de6-66c7ea0ffc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268606564 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2268606564
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3706054544
Short name T546
Test name
Test status
Simulation time 21120079 ps
CPU time 1.06 seconds
Started Feb 28 06:00:58 PM PST 24
Finished Feb 28 06:00:59 PM PST 24
Peak memory 214684 kb
Host smart-b96c20f1-c46e-4111-9c03-357fa7c5c8f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706054544 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3706054544
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.232159726
Short name T372
Test name
Test status
Simulation time 16759849706 ps
CPU time 414.31 seconds
Started Feb 28 06:00:59 PM PST 24
Finished Feb 28 06:07:53 PM PST 24
Peak memory 222896 kb
Host smart-eded63f8-474a-43fe-99d4-05dcd79b0847
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232159726 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.232159726
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.823268441
Short name T539
Test name
Test status
Simulation time 77180991 ps
CPU time 1.16 seconds
Started Feb 28 06:04:27 PM PST 24
Finished Feb 28 06:04:29 PM PST 24
Peak memory 214376 kb
Host smart-b59c2904-ab84-4ce1-83f3-6ca8331e3027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823268441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.823268441
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2248859010
Short name T521
Test name
Test status
Simulation time 46705868 ps
CPU time 1.68 seconds
Started Feb 28 06:02:38 PM PST 24
Finished Feb 28 06:02:41 PM PST 24
Peak memory 217408 kb
Host smart-7f8c8148-2320-4689-a987-01d64c805238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248859010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2248859010
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2405074984
Short name T692
Test name
Test status
Simulation time 53915813 ps
CPU time 1.36 seconds
Started Feb 28 06:02:44 PM PST 24
Finished Feb 28 06:02:45 PM PST 24
Peak memory 214916 kb
Host smart-1917ac50-aa02-4abb-95ac-5e472dad1d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405074984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2405074984
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.4197704717
Short name T611
Test name
Test status
Simulation time 42824875 ps
CPU time 1.42 seconds
Started Feb 28 06:04:44 PM PST 24
Finished Feb 28 06:04:46 PM PST 24
Peak memory 217200 kb
Host smart-c1c483cc-6c1d-4ed5-989b-9d22a930f251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197704717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.4197704717
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3367102091
Short name T335
Test name
Test status
Simulation time 298596360 ps
CPU time 2.15 seconds
Started Feb 28 06:02:44 PM PST 24
Finished Feb 28 06:02:46 PM PST 24
Peak memory 217476 kb
Host smart-b9ec1866-e02d-4b97-805e-8cfe1ab1f782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367102091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3367102091
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3476346714
Short name T486
Test name
Test status
Simulation time 148470607 ps
CPU time 1.44 seconds
Started Feb 28 06:02:43 PM PST 24
Finished Feb 28 06:02:44 PM PST 24
Peak memory 217540 kb
Host smart-664b4307-c1e4-401c-953c-93083777ea19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476346714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3476346714
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1644164126
Short name T559
Test name
Test status
Simulation time 47792313 ps
CPU time 1.44 seconds
Started Feb 28 06:02:44 PM PST 24
Finished Feb 28 06:02:45 PM PST 24
Peak memory 216112 kb
Host smart-1d74eac4-fa1e-4544-bf85-80c52281426f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644164126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1644164126
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3660426168
Short name T602
Test name
Test status
Simulation time 53205485 ps
CPU time 1.24 seconds
Started Feb 28 06:04:27 PM PST 24
Finished Feb 28 06:04:29 PM PST 24
Peak memory 214012 kb
Host smart-38f05be1-be73-4023-9b69-96faff673805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660426168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3660426168
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.10913114
Short name T406
Test name
Test status
Simulation time 63938618 ps
CPU time 1.08 seconds
Started Feb 28 06:02:45 PM PST 24
Finished Feb 28 06:02:46 PM PST 24
Peak memory 217180 kb
Host smart-0c4bd422-e88b-4711-a2e0-4a3142bb6d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10913114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.10913114
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2578851429
Short name T322
Test name
Test status
Simulation time 47529747 ps
CPU time 1.52 seconds
Started Feb 28 06:02:56 PM PST 24
Finished Feb 28 06:02:57 PM PST 24
Peak memory 217228 kb
Host smart-f6ca8297-37dd-49c7-bcae-1d8b114f95a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578851429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2578851429
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.480887872
Short name T599
Test name
Test status
Simulation time 115249087 ps
CPU time 1.09 seconds
Started Feb 28 06:01:00 PM PST 24
Finished Feb 28 06:01:01 PM PST 24
Peak memory 215112 kb
Host smart-be27d785-6b34-42a8-a099-03962cc053d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480887872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.480887872
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2944355467
Short name T828
Test name
Test status
Simulation time 14357083 ps
CPU time 1.02 seconds
Started Feb 28 06:01:03 PM PST 24
Finished Feb 28 06:01:04 PM PST 24
Peak memory 206220 kb
Host smart-d9b3fd0a-301c-4f45-a819-b7406bc15027
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944355467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2944355467
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_err.642287957
Short name T64
Test name
Test status
Simulation time 23472413 ps
CPU time 0.87 seconds
Started Feb 28 06:00:59 PM PST 24
Finished Feb 28 06:01:00 PM PST 24
Peak memory 217112 kb
Host smart-51fd7ef0-4025-44cc-864f-10485ac74d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642287957 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.642287957
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2960338928
Short name T755
Test name
Test status
Simulation time 138903314 ps
CPU time 1.42 seconds
Started Feb 28 06:01:00 PM PST 24
Finished Feb 28 06:01:01 PM PST 24
Peak memory 217720 kb
Host smart-2e97f084-966f-41cb-b8d8-6a508c1bee36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960338928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2960338928
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.317283165
Short name T22
Test name
Test status
Simulation time 35754891 ps
CPU time 0.88 seconds
Started Feb 28 06:01:02 PM PST 24
Finished Feb 28 06:01:03 PM PST 24
Peak memory 214976 kb
Host smart-ab1f268e-4f03-45ea-8495-85d15f9bfee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317283165 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.317283165
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.201209585
Short name T485
Test name
Test status
Simulation time 23073464 ps
CPU time 0.95 seconds
Started Feb 28 06:00:59 PM PST 24
Finished Feb 28 06:01:00 PM PST 24
Peak memory 214692 kb
Host smart-0bfc4249-2d8e-45a6-b9bf-6fe7c22babd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201209585 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.201209585
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.3657934347
Short name T497
Test name
Test status
Simulation time 373953441 ps
CPU time 6.82 seconds
Started Feb 28 06:00:58 PM PST 24
Finished Feb 28 06:01:05 PM PST 24
Peak memory 214644 kb
Host smart-d678d7cf-3981-45a8-b950-bcbf6eb5cad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657934347 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3657934347
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2656006069
Short name T326
Test name
Test status
Simulation time 156857672315 ps
CPU time 1793.98 seconds
Started Feb 28 06:01:01 PM PST 24
Finished Feb 28 06:30:55 PM PST 24
Peak memory 224552 kb
Host smart-8a2c553c-595b-4f6b-b17c-3d4f0c25c9ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656006069 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2656006069
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.447104531
Short name T415
Test name
Test status
Simulation time 46009266 ps
CPU time 1.3 seconds
Started Feb 28 06:02:49 PM PST 24
Finished Feb 28 06:02:51 PM PST 24
Peak memory 217432 kb
Host smart-10496d9e-a43a-4953-a563-6ad256e6abda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447104531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.447104531
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.4184741661
Short name T613
Test name
Test status
Simulation time 36091603 ps
CPU time 1.41 seconds
Started Feb 28 06:02:45 PM PST 24
Finished Feb 28 06:02:46 PM PST 24
Peak memory 214796 kb
Host smart-5b96e679-941b-46f8-9764-b04c32e533ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184741661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.4184741661
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.48847366
Short name T533
Test name
Test status
Simulation time 62811421 ps
CPU time 2.18 seconds
Started Feb 28 06:02:44 PM PST 24
Finished Feb 28 06:02:47 PM PST 24
Peak memory 217572 kb
Host smart-bc2f0a79-19f7-41ff-a7e9-cc4df864285f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48847366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.48847366
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3501176333
Short name T149
Test name
Test status
Simulation time 32708970 ps
CPU time 1.21 seconds
Started Feb 28 06:02:45 PM PST 24
Finished Feb 28 06:02:46 PM PST 24
Peak memory 215980 kb
Host smart-3104cfc2-477b-4538-a140-541fb8cbd789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501176333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3501176333
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2939034400
Short name T696
Test name
Test status
Simulation time 32595357 ps
CPU time 1.35 seconds
Started Feb 28 06:02:45 PM PST 24
Finished Feb 28 06:02:46 PM PST 24
Peak memory 217068 kb
Host smart-3f7efd3f-22bf-4564-bc2d-24e1da349e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939034400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2939034400
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3142696924
Short name T621
Test name
Test status
Simulation time 30419336 ps
CPU time 1.21 seconds
Started Feb 28 06:02:45 PM PST 24
Finished Feb 28 06:02:47 PM PST 24
Peak memory 215896 kb
Host smart-310361ed-470c-4535-b8d6-73e3efd2784a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142696924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3142696924
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2067758881
Short name T801
Test name
Test status
Simulation time 44166077 ps
CPU time 1.17 seconds
Started Feb 28 06:02:46 PM PST 24
Finished Feb 28 06:02:47 PM PST 24
Peak memory 217276 kb
Host smart-7d7b1594-15d8-44e5-94a2-5bcde4654c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067758881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2067758881
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.296075789
Short name T35
Test name
Test status
Simulation time 251009423 ps
CPU time 1.64 seconds
Started Feb 28 06:02:44 PM PST 24
Finished Feb 28 06:02:46 PM PST 24
Peak memory 217836 kb
Host smart-e6aaa412-0a25-4ce5-8946-fb032e956695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296075789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.296075789
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1129329683
Short name T566
Test name
Test status
Simulation time 76355620 ps
CPU time 1.04 seconds
Started Feb 28 06:02:51 PM PST 24
Finished Feb 28 06:02:52 PM PST 24
Peak memory 216036 kb
Host smart-b925577a-f8f6-4486-ac2c-e92306fc1215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129329683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1129329683
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.496362961
Short name T445
Test name
Test status
Simulation time 28942568 ps
CPU time 1.08 seconds
Started Feb 28 06:02:48 PM PST 24
Finished Feb 28 06:02:49 PM PST 24
Peak memory 215832 kb
Host smart-896fb578-c3df-46da-bd5f-6bdc93479056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496362961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.496362961
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2723717020
Short name T185
Test name
Test status
Simulation time 75028872 ps
CPU time 1.22 seconds
Started Feb 28 06:01:04 PM PST 24
Finished Feb 28 06:01:05 PM PST 24
Peak memory 215064 kb
Host smart-dbfae345-df10-40c1-bfbc-d003aeec5373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723717020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2723717020
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.982356133
Short name T664
Test name
Test status
Simulation time 31425057 ps
CPU time 0.96 seconds
Started Feb 28 06:01:03 PM PST 24
Finished Feb 28 06:01:05 PM PST 24
Peak memory 206220 kb
Host smart-4488a437-c345-4ac1-9de0-2e42626887a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982356133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.982356133
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1555791250
Short name T443
Test name
Test status
Simulation time 22348909 ps
CPU time 0.88 seconds
Started Feb 28 06:01:03 PM PST 24
Finished Feb 28 06:01:05 PM PST 24
Peak memory 214820 kb
Host smart-d7da26bc-c455-46f1-860f-4bcf783c1c7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555791250 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1555791250
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.3061739914
Short name T49
Test name
Test status
Simulation time 18444879 ps
CPU time 1.13 seconds
Started Feb 28 06:01:03 PM PST 24
Finished Feb 28 06:01:05 PM PST 24
Peak memory 222360 kb
Host smart-3cdb2146-0ad8-45a0-ba52-14f6ee1e1d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061739914 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3061739914
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1210516708
Short name T38
Test name
Test status
Simulation time 24648599 ps
CPU time 1.13 seconds
Started Feb 28 06:01:02 PM PST 24
Finished Feb 28 06:01:04 PM PST 24
Peak memory 215960 kb
Host smart-5a6a2cb2-2da8-4faf-9444-d4acf2cdad5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210516708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1210516708
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1564684154
Short name T145
Test name
Test status
Simulation time 20629217 ps
CPU time 1.09 seconds
Started Feb 28 06:01:13 PM PST 24
Finished Feb 28 06:01:15 PM PST 24
Peak memory 215272 kb
Host smart-bae2ac17-fc64-466c-8df6-c2a4aa709d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564684154 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1564684154
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3662636062
Short name T147
Test name
Test status
Simulation time 27814810 ps
CPU time 1.06 seconds
Started Feb 28 06:01:03 PM PST 24
Finished Feb 28 06:01:05 PM PST 24
Peak memory 214684 kb
Host smart-f8759786-145c-4e7c-988a-4b6925887507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662636062 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3662636062
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1353537922
Short name T799
Test name
Test status
Simulation time 218979651 ps
CPU time 1.6 seconds
Started Feb 28 06:01:04 PM PST 24
Finished Feb 28 06:01:06 PM PST 24
Peak memory 215784 kb
Host smart-be4b6cf9-5098-48cb-9cee-3573a66d11c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353537922 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1353537922
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2678138739
Short name T188
Test name
Test status
Simulation time 74811602665 ps
CPU time 1294.51 seconds
Started Feb 28 06:01:03 PM PST 24
Finished Feb 28 06:22:39 PM PST 24
Peak memory 223348 kb
Host smart-2d95083b-82cb-492a-86fa-d7324d89dcc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678138739 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2678138739
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2036290940
Short name T637
Test name
Test status
Simulation time 39942774 ps
CPU time 1.48 seconds
Started Feb 28 06:02:48 PM PST 24
Finished Feb 28 06:02:49 PM PST 24
Peak memory 218424 kb
Host smart-f37ddec1-4ad7-4f76-94ae-1666e12a6bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036290940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2036290940
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3534404985
Short name T723
Test name
Test status
Simulation time 52407449 ps
CPU time 1.62 seconds
Started Feb 28 06:02:50 PM PST 24
Finished Feb 28 06:02:52 PM PST 24
Peak memory 217120 kb
Host smart-437a8da9-bbe8-4f00-9a03-5583e1ae7309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534404985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3534404985
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.752472591
Short name T465
Test name
Test status
Simulation time 54260288 ps
CPU time 1.8 seconds
Started Feb 28 06:02:48 PM PST 24
Finished Feb 28 06:02:50 PM PST 24
Peak memory 216236 kb
Host smart-c7d2aebd-f6ac-4c61-8596-d484758bac32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752472591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.752472591
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.720633971
Short name T656
Test name
Test status
Simulation time 45079837 ps
CPU time 1.22 seconds
Started Feb 28 06:02:52 PM PST 24
Finished Feb 28 06:02:53 PM PST 24
Peak memory 217396 kb
Host smart-f60e9757-73b2-41d5-8bce-46c6dac2d547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720633971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.720633971
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.266279093
Short name T277
Test name
Test status
Simulation time 115884025 ps
CPU time 2.44 seconds
Started Feb 28 06:02:46 PM PST 24
Finished Feb 28 06:02:49 PM PST 24
Peak memory 218996 kb
Host smart-fde18686-79cf-44da-871c-92e103066f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266279093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.266279093
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1906621726
Short name T702
Test name
Test status
Simulation time 274070941 ps
CPU time 3.92 seconds
Started Feb 28 06:02:50 PM PST 24
Finished Feb 28 06:02:54 PM PST 24
Peak memory 217324 kb
Host smart-51d6eb13-00fa-418d-93a3-543cc5ddb5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906621726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1906621726
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.638004635
Short name T542
Test name
Test status
Simulation time 44281127 ps
CPU time 1.3 seconds
Started Feb 28 06:02:51 PM PST 24
Finished Feb 28 06:02:52 PM PST 24
Peak memory 217376 kb
Host smart-28c3e1a2-961f-45ce-99d7-59702e532b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638004635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.638004635
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3365481584
Short name T427
Test name
Test status
Simulation time 67077519 ps
CPU time 1.36 seconds
Started Feb 28 06:02:48 PM PST 24
Finished Feb 28 06:02:49 PM PST 24
Peak memory 217712 kb
Host smart-64ebd8dc-45cd-4ed8-8f6e-50dc5ebd77fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365481584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3365481584
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3747281224
Short name T700
Test name
Test status
Simulation time 31981814 ps
CPU time 1.21 seconds
Started Feb 28 06:02:48 PM PST 24
Finished Feb 28 06:02:50 PM PST 24
Peak memory 217064 kb
Host smart-661e3007-d600-4511-a369-81dc91687d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747281224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3747281224
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3334924196
Short name T24
Test name
Test status
Simulation time 185053454 ps
CPU time 1.05 seconds
Started Feb 28 06:02:51 PM PST 24
Finished Feb 28 06:02:52 PM PST 24
Peak memory 216160 kb
Host smart-282a84f1-22df-4521-a095-1b0f82069e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334924196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3334924196
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1230876189
Short name T248
Test name
Test status
Simulation time 25622906 ps
CPU time 1.3 seconds
Started Feb 28 06:01:08 PM PST 24
Finished Feb 28 06:01:10 PM PST 24
Peak memory 215016 kb
Host smart-f1318ffc-40ef-40fe-a5bb-6aacac2188b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230876189 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1230876189
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.629793559
Short name T290
Test name
Test status
Simulation time 18322436 ps
CPU time 0.81 seconds
Started Feb 28 06:01:08 PM PST 24
Finished Feb 28 06:01:09 PM PST 24
Peak memory 204952 kb
Host smart-7e838c7e-2e94-426a-8791-652dae9190c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629793559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.629793559
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2246471494
Short name T708
Test name
Test status
Simulation time 27141664 ps
CPU time 0.8 seconds
Started Feb 28 06:01:09 PM PST 24
Finished Feb 28 06:01:10 PM PST 24
Peak memory 215236 kb
Host smart-9b553e3a-997b-40cd-9b54-fdfe0c606343
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246471494 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2246471494
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.854169617
Short name T76
Test name
Test status
Simulation time 47291466 ps
CPU time 1.44 seconds
Started Feb 28 06:01:06 PM PST 24
Finished Feb 28 06:01:08 PM PST 24
Peak memory 215960 kb
Host smart-2c7b2e33-9d22-48dc-bfca-8728e36752c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854169617 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.854169617
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.296210444
Short name T321
Test name
Test status
Simulation time 21752730 ps
CPU time 0.91 seconds
Started Feb 28 06:01:05 PM PST 24
Finished Feb 28 06:01:07 PM PST 24
Peak memory 217040 kb
Host smart-3120e77a-6c4f-4105-bab4-b43368de8077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296210444 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.296210444
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3818887832
Short name T367
Test name
Test status
Simulation time 45379940 ps
CPU time 1.18 seconds
Started Feb 28 06:01:03 PM PST 24
Finished Feb 28 06:01:05 PM PST 24
Peak memory 217100 kb
Host smart-69f70cc4-53eb-41b9-a0af-b052271826e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818887832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3818887832
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3476411806
Short name T633
Test name
Test status
Simulation time 21176142 ps
CPU time 1.1 seconds
Started Feb 28 06:01:08 PM PST 24
Finished Feb 28 06:01:09 PM PST 24
Peak memory 214992 kb
Host smart-2af7b82b-bc41-4db3-ba58-8c94bffcf476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476411806 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3476411806
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1617964691
Short name T328
Test name
Test status
Simulation time 24849056 ps
CPU time 0.92 seconds
Started Feb 28 06:01:06 PM PST 24
Finished Feb 28 06:01:07 PM PST 24
Peak memory 214648 kb
Host smart-091bba55-361c-46ac-bd33-083dfbd613f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617964691 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1617964691
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3103780720
Short name T462
Test name
Test status
Simulation time 223281802 ps
CPU time 2.95 seconds
Started Feb 28 06:01:03 PM PST 24
Finished Feb 28 06:01:07 PM PST 24
Peak memory 218948 kb
Host smart-09dd5a31-7f41-4827-9a78-69f15a4fac78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103780720 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3103780720
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.619836503
Short name T192
Test name
Test status
Simulation time 41484335560 ps
CPU time 892.02 seconds
Started Feb 28 06:01:08 PM PST 24
Finished Feb 28 06:16:00 PM PST 24
Peak memory 218988 kb
Host smart-3084d42e-e0be-4f07-92a1-dc1078997a73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619836503 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.619836503
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2014958637
Short name T747
Test name
Test status
Simulation time 220762372 ps
CPU time 3.45 seconds
Started Feb 28 06:02:49 PM PST 24
Finished Feb 28 06:02:53 PM PST 24
Peak memory 216360 kb
Host smart-8fe14999-2e76-44db-89b3-798b88f1104d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014958637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2014958637
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2271704671
Short name T271
Test name
Test status
Simulation time 53735450 ps
CPU time 1.24 seconds
Started Feb 28 06:02:49 PM PST 24
Finished Feb 28 06:02:51 PM PST 24
Peak memory 216504 kb
Host smart-ef16fb50-972c-44a8-ba59-0633479f8985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271704671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2271704671
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.495254666
Short name T766
Test name
Test status
Simulation time 45644968 ps
CPU time 1.33 seconds
Started Feb 28 06:02:49 PM PST 24
Finished Feb 28 06:02:51 PM PST 24
Peak memory 216044 kb
Host smart-685d6196-dfb4-4fb4-bbd5-8a50f763ee5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495254666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.495254666
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.67759454
Short name T463
Test name
Test status
Simulation time 32628440 ps
CPU time 1.25 seconds
Started Feb 28 06:02:48 PM PST 24
Finished Feb 28 06:02:49 PM PST 24
Peak memory 218628 kb
Host smart-58f4c8c2-5511-4996-be2d-e58ec3a46631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67759454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.67759454
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3769131857
Short name T334
Test name
Test status
Simulation time 45709481 ps
CPU time 1.97 seconds
Started Feb 28 06:02:48 PM PST 24
Finished Feb 28 06:02:50 PM PST 24
Peak memory 214796 kb
Host smart-b78d5b59-adc6-4aec-8e9a-42e1b653282f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769131857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3769131857
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1375186641
Short name T380
Test name
Test status
Simulation time 37961460 ps
CPU time 1.38 seconds
Started Feb 28 06:02:48 PM PST 24
Finished Feb 28 06:02:50 PM PST 24
Peak memory 216260 kb
Host smart-cbdfb1c6-b714-44fe-a168-f76ed6a10985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375186641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1375186641
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1183885276
Short name T280
Test name
Test status
Simulation time 134324512 ps
CPU time 1.12 seconds
Started Feb 28 06:02:51 PM PST 24
Finished Feb 28 06:02:52 PM PST 24
Peak memory 218364 kb
Host smart-a26e93fc-8b86-4df4-8e5a-7a444f54521d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183885276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1183885276
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2918442607
Short name T568
Test name
Test status
Simulation time 223612887 ps
CPU time 1 seconds
Started Feb 28 06:02:52 PM PST 24
Finished Feb 28 06:02:53 PM PST 24
Peak memory 215892 kb
Host smart-fc25bb00-1588-4655-a64e-b9523b180f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918442607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2918442607
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.530560998
Short name T768
Test name
Test status
Simulation time 139423829 ps
CPU time 1.64 seconds
Started Feb 28 06:02:51 PM PST 24
Finished Feb 28 06:02:53 PM PST 24
Peak memory 217396 kb
Host smart-d136b427-8ad7-4fc8-b12a-a81acea67616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530560998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.530560998
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1388520931
Short name T712
Test name
Test status
Simulation time 43977814 ps
CPU time 1.63 seconds
Started Feb 28 06:02:51 PM PST 24
Finished Feb 28 06:02:52 PM PST 24
Peak memory 217216 kb
Host smart-2c7c5271-638c-49e9-8112-ffba40a5af6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388520931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1388520931
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3998099598
Short name T675
Test name
Test status
Simulation time 28665025 ps
CPU time 1.28 seconds
Started Feb 28 06:01:06 PM PST 24
Finished Feb 28 06:01:08 PM PST 24
Peak memory 215044 kb
Host smart-e5815db2-84ee-46cb-be69-f17d759077d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998099598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3998099598
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1094219857
Short name T362
Test name
Test status
Simulation time 18821781 ps
CPU time 1.04 seconds
Started Feb 28 06:01:05 PM PST 24
Finished Feb 28 06:01:06 PM PST 24
Peak memory 205960 kb
Host smart-b93c2691-f790-4895-a3ca-892f36241721
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094219857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1094219857
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_err.3372665826
Short name T68
Test name
Test status
Simulation time 36637386 ps
CPU time 1 seconds
Started Feb 28 06:01:05 PM PST 24
Finished Feb 28 06:01:07 PM PST 24
Peak memory 229008 kb
Host smart-3f9caeee-709b-418e-9be6-5dc00ffc40bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372665826 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3372665826
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3339632011
Short name T402
Test name
Test status
Simulation time 116358178 ps
CPU time 1.54 seconds
Started Feb 28 06:01:06 PM PST 24
Finished Feb 28 06:01:09 PM PST 24
Peak memory 217612 kb
Host smart-e935e15d-cfce-4228-aa82-4923469d4a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339632011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3339632011
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3943798770
Short name T576
Test name
Test status
Simulation time 26348783 ps
CPU time 1.01 seconds
Started Feb 28 06:01:09 PM PST 24
Finished Feb 28 06:01:10 PM PST 24
Peak memory 222584 kb
Host smart-bf1e5fa8-204f-486d-8ae4-ba31a5fb0cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943798770 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3943798770
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1487407779
Short name T552
Test name
Test status
Simulation time 40689067 ps
CPU time 0.88 seconds
Started Feb 28 06:01:08 PM PST 24
Finished Feb 28 06:01:09 PM PST 24
Peak memory 214484 kb
Host smart-4d3e7d6d-ad4a-4154-a005-57c40d2dcb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487407779 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1487407779
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.51639566
Short name T198
Test name
Test status
Simulation time 177024628 ps
CPU time 1.3 seconds
Started Feb 28 06:01:06 PM PST 24
Finished Feb 28 06:01:07 PM PST 24
Peak memory 206520 kb
Host smart-23ecbfaa-a853-476b-b6dc-bc24b895bed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51639566 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.51639566
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1609883144
Short name T647
Test name
Test status
Simulation time 228578624955 ps
CPU time 1361.17 seconds
Started Feb 28 06:01:06 PM PST 24
Finished Feb 28 06:23:47 PM PST 24
Peak memory 224296 kb
Host smart-8aff4f15-ff6f-4e4a-8940-855b3db05f71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609883144 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1609883144
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1047171522
Short name T387
Test name
Test status
Simulation time 48960686 ps
CPU time 1.18 seconds
Started Feb 28 06:02:52 PM PST 24
Finished Feb 28 06:02:54 PM PST 24
Peak memory 218684 kb
Host smart-1e8af67d-7a39-48ce-a91b-56c61312209f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047171522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1047171522
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.770376902
Short name T822
Test name
Test status
Simulation time 47471539 ps
CPU time 1.16 seconds
Started Feb 28 06:02:50 PM PST 24
Finished Feb 28 06:02:52 PM PST 24
Peak memory 217300 kb
Host smart-be3148ac-ddf3-4a3a-a74a-4faee4db4d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770376902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.770376902
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2229862145
Short name T261
Test name
Test status
Simulation time 162548188 ps
CPU time 1.15 seconds
Started Feb 28 06:03:00 PM PST 24
Finished Feb 28 06:03:01 PM PST 24
Peak memory 216188 kb
Host smart-704a602e-fdf8-4932-8938-a549379929ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229862145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2229862145
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2858469729
Short name T703
Test name
Test status
Simulation time 22653483 ps
CPU time 1.01 seconds
Started Feb 28 06:02:50 PM PST 24
Finished Feb 28 06:02:51 PM PST 24
Peak memory 215816 kb
Host smart-0570e5c2-9462-4a4d-a93b-6ece949d4826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858469729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2858469729
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2258362319
Short name T724
Test name
Test status
Simulation time 42728995 ps
CPU time 1.36 seconds
Started Feb 28 06:02:50 PM PST 24
Finished Feb 28 06:02:52 PM PST 24
Peak memory 216104 kb
Host smart-58d0daf9-fd53-490a-b656-c848ecd9ad1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258362319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2258362319
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.697498508
Short name T13
Test name
Test status
Simulation time 87193478 ps
CPU time 1.26 seconds
Started Feb 28 06:03:00 PM PST 24
Finished Feb 28 06:03:02 PM PST 24
Peak memory 217532 kb
Host smart-56bc3b14-6ed5-4bca-ac64-b75e0615b573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697498508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.697498508
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.796856788
Short name T449
Test name
Test status
Simulation time 52762776 ps
CPU time 1.38 seconds
Started Feb 28 06:02:53 PM PST 24
Finished Feb 28 06:02:55 PM PST 24
Peak memory 217324 kb
Host smart-0f6b8369-9947-422c-b1ce-21be855aa606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796856788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.796856788
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2768939770
Short name T438
Test name
Test status
Simulation time 39182530 ps
CPU time 1.41 seconds
Started Feb 28 06:02:52 PM PST 24
Finished Feb 28 06:02:53 PM PST 24
Peak memory 216012 kb
Host smart-6d7a4217-b1ef-4342-af72-b77700142057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768939770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2768939770
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2470450167
Short name T711
Test name
Test status
Simulation time 21737514 ps
CPU time 1.07 seconds
Started Feb 28 06:02:52 PM PST 24
Finished Feb 28 06:02:53 PM PST 24
Peak memory 215900 kb
Host smart-e6b48f40-0a0b-4f84-94c7-03d06b1caa2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470450167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2470450167
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.406028031
Short name T756
Test name
Test status
Simulation time 34920658 ps
CPU time 1.56 seconds
Started Feb 28 06:02:51 PM PST 24
Finished Feb 28 06:02:53 PM PST 24
Peak memory 217208 kb
Host smart-3590eb3d-c5c5-4ce5-a1c9-a71d3461ea49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406028031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.406028031
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3903286408
Short name T251
Test name
Test status
Simulation time 25580791 ps
CPU time 1.23 seconds
Started Feb 28 06:01:09 PM PST 24
Finished Feb 28 06:01:10 PM PST 24
Peak memory 215044 kb
Host smart-21a3e1ed-bcee-4f68-a76a-06bb91c7432c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903286408 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3903286408
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.326082607
Short name T725
Test name
Test status
Simulation time 20454017 ps
CPU time 1.11 seconds
Started Feb 28 06:01:11 PM PST 24
Finished Feb 28 06:01:12 PM PST 24
Peak memory 206448 kb
Host smart-88d4afe8-5da5-408e-baa9-1bf14d4c9149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326082607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.326082607
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1044913132
Short name T468
Test name
Test status
Simulation time 31962947 ps
CPU time 1.05 seconds
Started Feb 28 06:01:14 PM PST 24
Finished Feb 28 06:01:15 PM PST 24
Peak memory 217192 kb
Host smart-a28a5e67-b2ac-4aa8-a78f-f4b9596f03d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044913132 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1044913132
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.4251150989
Short name T107
Test name
Test status
Simulation time 23297123 ps
CPU time 0.93 seconds
Started Feb 28 06:01:10 PM PST 24
Finished Feb 28 06:01:11 PM PST 24
Peak memory 217116 kb
Host smart-099e0812-b357-4483-be5d-e1d4d3561394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251150989 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.4251150989
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.811644185
Short name T354
Test name
Test status
Simulation time 84690498 ps
CPU time 1.1 seconds
Started Feb 28 06:01:08 PM PST 24
Finished Feb 28 06:01:09 PM PST 24
Peak memory 216108 kb
Host smart-b9dba08b-c499-421c-9547-52744af98444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811644185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.811644185
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.1280567472
Short name T630
Test name
Test status
Simulation time 27827517 ps
CPU time 1.1 seconds
Started Feb 28 06:01:12 PM PST 24
Finished Feb 28 06:01:13 PM PST 24
Peak memory 223400 kb
Host smart-4cfc756f-f467-4088-ab2b-10563f80738f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280567472 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1280567472
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.1086896617
Short name T384
Test name
Test status
Simulation time 18149821 ps
CPU time 1 seconds
Started Feb 28 06:01:08 PM PST 24
Finished Feb 28 06:01:09 PM PST 24
Peak memory 214668 kb
Host smart-95cfdac7-da66-4f26-b303-8092252d8ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086896617 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.1086896617
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1407820896
Short name T776
Test name
Test status
Simulation time 431857772 ps
CPU time 3.02 seconds
Started Feb 28 06:01:14 PM PST 24
Finished Feb 28 06:01:17 PM PST 24
Peak memory 216012 kb
Host smart-1f00230a-22cf-44e4-a802-2b315fce0af7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407820896 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1407820896
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3752026009
Short name T813
Test name
Test status
Simulation time 45906136657 ps
CPU time 1059.91 seconds
Started Feb 28 06:01:10 PM PST 24
Finished Feb 28 06:18:50 PM PST 24
Peak memory 223124 kb
Host smart-de828e35-518a-4e7b-bd0f-ce55ba546e32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752026009 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3752026009
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3084504474
Short name T342
Test name
Test status
Simulation time 57953423 ps
CPU time 1.18 seconds
Started Feb 28 06:03:00 PM PST 24
Finished Feb 28 06:03:01 PM PST 24
Peak memory 218132 kb
Host smart-9003df50-8852-412a-bb8e-52fd51fb1b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084504474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3084504474
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1960582926
Short name T762
Test name
Test status
Simulation time 39762391 ps
CPU time 1.5 seconds
Started Feb 28 06:03:00 PM PST 24
Finished Feb 28 06:03:01 PM PST 24
Peak memory 217200 kb
Host smart-3cf834d5-906c-4110-9fd5-d4e561b332a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960582926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1960582926
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2365465076
Short name T428
Test name
Test status
Simulation time 24347357 ps
CPU time 1.19 seconds
Started Feb 28 06:02:51 PM PST 24
Finished Feb 28 06:02:53 PM PST 24
Peak memory 217236 kb
Host smart-2330fd82-8c54-4ff4-9b52-97b754c88518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365465076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2365465076
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1734774485
Short name T343
Test name
Test status
Simulation time 56765882 ps
CPU time 1.43 seconds
Started Feb 28 06:02:53 PM PST 24
Finished Feb 28 06:02:55 PM PST 24
Peak memory 218824 kb
Host smart-0d047025-59b6-4f0b-a582-b9d49b5a33ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734774485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1734774485
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1856499012
Short name T726
Test name
Test status
Simulation time 52914650 ps
CPU time 1.23 seconds
Started Feb 28 06:02:55 PM PST 24
Finished Feb 28 06:02:56 PM PST 24
Peak memory 215864 kb
Host smart-25fb3a99-e6d0-452f-848f-bb30bbaab502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856499012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1856499012
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2502076133
Short name T452
Test name
Test status
Simulation time 63996682 ps
CPU time 1.07 seconds
Started Feb 28 06:03:00 PM PST 24
Finished Feb 28 06:03:01 PM PST 24
Peak memory 215724 kb
Host smart-da8451ea-15c0-4a9a-b4d0-a89dc505016b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502076133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2502076133
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.949827400
Short name T483
Test name
Test status
Simulation time 98475241 ps
CPU time 1.25 seconds
Started Feb 28 06:02:51 PM PST 24
Finished Feb 28 06:02:53 PM PST 24
Peak memory 218604 kb
Host smart-96cea3b4-ba55-4afd-8e5d-68e9b08e9ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949827400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.949827400
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3800865919
Short name T588
Test name
Test status
Simulation time 40403074 ps
CPU time 1.57 seconds
Started Feb 28 06:02:52 PM PST 24
Finished Feb 28 06:02:54 PM PST 24
Peak memory 215940 kb
Host smart-54397451-bbc1-400f-8328-1bc08fff9fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800865919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3800865919
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.914405682
Short name T823
Test name
Test status
Simulation time 33914654 ps
CPU time 1.22 seconds
Started Feb 28 06:02:52 PM PST 24
Finished Feb 28 06:02:53 PM PST 24
Peak memory 218516 kb
Host smart-74af0dd8-2dd0-4404-9745-0be352bad634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914405682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.914405682
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.269005778
Short name T750
Test name
Test status
Simulation time 59647706 ps
CPU time 1.22 seconds
Started Feb 28 06:02:57 PM PST 24
Finished Feb 28 06:02:58 PM PST 24
Peak memory 215844 kb
Host smart-f4f597ef-ebfb-4fca-8661-8421665b1f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269005778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.269005778
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.368360098
Short name T641
Test name
Test status
Simulation time 29588022 ps
CPU time 1.24 seconds
Started Feb 28 06:01:18 PM PST 24
Finished Feb 28 06:01:19 PM PST 24
Peak memory 215044 kb
Host smart-827d6587-b295-440a-acb0-d8b070c5df5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368360098 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.368360098
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1588510788
Short name T632
Test name
Test status
Simulation time 50332556 ps
CPU time 0.88 seconds
Started Feb 28 06:01:14 PM PST 24
Finished Feb 28 06:01:15 PM PST 24
Peak memory 205992 kb
Host smart-a47a60d7-b8cb-4f03-b335-c995d7575427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588510788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1588510788
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.4026824709
Short name T114
Test name
Test status
Simulation time 44211183 ps
CPU time 0.77 seconds
Started Feb 28 06:01:17 PM PST 24
Finished Feb 28 06:01:18 PM PST 24
Peak memory 215116 kb
Host smart-d3cbd3d6-5acb-498a-bdd2-41e1d17ab24b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026824709 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.4026824709
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.4070516060
Short name T831
Test name
Test status
Simulation time 126699103 ps
CPU time 1.04 seconds
Started Feb 28 06:01:16 PM PST 24
Finished Feb 28 06:01:17 PM PST 24
Peak memory 215652 kb
Host smart-4b81e2a6-bb1c-4bcf-879d-6236bc039619
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070516060 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.4070516060
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.4252458217
Short name T176
Test name
Test status
Simulation time 67938208 ps
CPU time 1.19 seconds
Started Feb 28 06:01:19 PM PST 24
Finished Feb 28 06:01:20 PM PST 24
Peak memory 223456 kb
Host smart-c307751d-b83a-4819-92d9-7a53531cfb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252458217 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.4252458217
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3465321373
Short name T359
Test name
Test status
Simulation time 64219718 ps
CPU time 1.18 seconds
Started Feb 28 06:01:11 PM PST 24
Finished Feb 28 06:01:13 PM PST 24
Peak memory 216084 kb
Host smart-09929507-4a7d-4df7-bdae-954d51323851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465321373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3465321373
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2461454831
Short name T66
Test name
Test status
Simulation time 28247123 ps
CPU time 0.86 seconds
Started Feb 28 06:01:15 PM PST 24
Finished Feb 28 06:01:16 PM PST 24
Peak memory 214980 kb
Host smart-86a4897c-5ccb-48a1-8f68-59ae7ca83563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461454831 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2461454831
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1690417937
Short name T352
Test name
Test status
Simulation time 36228516 ps
CPU time 0.94 seconds
Started Feb 28 06:01:11 PM PST 24
Finished Feb 28 06:01:12 PM PST 24
Peak memory 214692 kb
Host smart-648ceddd-3368-4cdf-9d80-4dba359f8e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690417937 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1690417937
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3927169778
Short name T687
Test name
Test status
Simulation time 79866987 ps
CPU time 1.02 seconds
Started Feb 28 06:01:15 PM PST 24
Finished Feb 28 06:01:16 PM PST 24
Peak memory 214696 kb
Host smart-d6259df9-0ee6-4367-9dee-3f20c1fac419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927169778 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3927169778
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3887329644
Short name T455
Test name
Test status
Simulation time 29820678514 ps
CPU time 635.04 seconds
Started Feb 28 06:01:11 PM PST 24
Finished Feb 28 06:11:46 PM PST 24
Peak memory 216876 kb
Host smart-a4585597-6e71-4d79-b30e-38686968e3ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887329644 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3887329644
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.3188770105
Short name T28
Test name
Test status
Simulation time 73129454 ps
CPU time 1.23 seconds
Started Feb 28 06:02:55 PM PST 24
Finished Feb 28 06:02:56 PM PST 24
Peak memory 215788 kb
Host smart-af4eed63-62da-4f7a-8100-f97c45d3b5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188770105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3188770105
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1593701695
Short name T499
Test name
Test status
Simulation time 72490795 ps
CPU time 1.34 seconds
Started Feb 28 06:02:54 PM PST 24
Finished Feb 28 06:02:56 PM PST 24
Peak memory 216012 kb
Host smart-a184b277-63c8-4050-a332-3ecf7a16954d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593701695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1593701695
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1985082844
Short name T643
Test name
Test status
Simulation time 61256671 ps
CPU time 1.09 seconds
Started Feb 28 06:02:57 PM PST 24
Finished Feb 28 06:02:59 PM PST 24
Peak memory 214780 kb
Host smart-5eb06625-c2e7-4d35-92fe-aa6fe975901a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985082844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1985082844
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.352464688
Short name T510
Test name
Test status
Simulation time 73937683 ps
CPU time 1.09 seconds
Started Feb 28 06:03:01 PM PST 24
Finished Feb 28 06:03:03 PM PST 24
Peak memory 215904 kb
Host smart-6d5ac341-3ab8-47a0-a24a-1b19acef5624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352464688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.352464688
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.4192929260
Short name T184
Test name
Test status
Simulation time 235792155 ps
CPU time 1.08 seconds
Started Feb 28 06:02:55 PM PST 24
Finished Feb 28 06:02:57 PM PST 24
Peak memory 215844 kb
Host smart-92f8fa1e-7b6f-4904-a9fe-4a72af3f316b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192929260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.4192929260
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.645612259
Short name T281
Test name
Test status
Simulation time 67141177 ps
CPU time 2.58 seconds
Started Feb 28 06:02:55 PM PST 24
Finished Feb 28 06:02:58 PM PST 24
Peak memory 217196 kb
Host smart-1c2f6f1b-833d-479b-b173-9f5bf63f165d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645612259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.645612259
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1139399219
Short name T509
Test name
Test status
Simulation time 76042190 ps
CPU time 1.08 seconds
Started Feb 28 06:02:55 PM PST 24
Finished Feb 28 06:02:56 PM PST 24
Peak memory 216028 kb
Host smart-1526b615-8e65-4f18-afb6-91c9dcc51a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139399219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1139399219
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1081630997
Short name T721
Test name
Test status
Simulation time 64119082 ps
CPU time 1.21 seconds
Started Feb 28 06:02:54 PM PST 24
Finished Feb 28 06:02:56 PM PST 24
Peak memory 216012 kb
Host smart-b48df359-89e6-4c3f-9038-cd281061af57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081630997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1081630997
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3032750260
Short name T812
Test name
Test status
Simulation time 41801756 ps
CPU time 1.66 seconds
Started Feb 28 06:02:55 PM PST 24
Finished Feb 28 06:02:57 PM PST 24
Peak memory 217148 kb
Host smart-1423a225-0a8b-46c2-9ffb-1755dc94f9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032750260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3032750260
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3717660870
Short name T34
Test name
Test status
Simulation time 31541028 ps
CPU time 1.15 seconds
Started Feb 28 06:02:58 PM PST 24
Finished Feb 28 06:02:59 PM PST 24
Peak memory 217432 kb
Host smart-93031896-a5f0-45d9-a8fb-95694a77657d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717660870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3717660870
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2983576200
Short name T249
Test name
Test status
Simulation time 261150991 ps
CPU time 1.25 seconds
Started Feb 28 06:01:18 PM PST 24
Finished Feb 28 06:01:19 PM PST 24
Peak memory 215056 kb
Host smart-cfe85c48-68cb-43ab-93ee-bf8231386227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983576200 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2983576200
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3534361415
Short name T646
Test name
Test status
Simulation time 16360005 ps
CPU time 0.87 seconds
Started Feb 28 06:01:21 PM PST 24
Finished Feb 28 06:01:22 PM PST 24
Peak memory 205384 kb
Host smart-1b60ef8d-7ca2-4e72-aea9-75e33af2fa71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534361415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3534361415
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.3253600060
Short name T344
Test name
Test status
Simulation time 22022749 ps
CPU time 0.91 seconds
Started Feb 28 06:01:19 PM PST 24
Finished Feb 28 06:01:20 PM PST 24
Peak memory 214852 kb
Host smart-5b9e6245-a521-4ff6-9eaf-7d0213c3dfe9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253600060 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3253600060
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2710707253
Short name T161
Test name
Test status
Simulation time 79571263 ps
CPU time 1.09 seconds
Started Feb 28 06:01:19 PM PST 24
Finished Feb 28 06:01:20 PM PST 24
Peak memory 217204 kb
Host smart-fd104ee4-2c96-4cae-96bb-1455395c0ffa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710707253 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2710707253
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2787031602
Short name T683
Test name
Test status
Simulation time 19179127 ps
CPU time 1.01 seconds
Started Feb 28 06:01:19 PM PST 24
Finished Feb 28 06:01:20 PM PST 24
Peak memory 217148 kb
Host smart-c1aef8b9-289b-4374-b3ad-5302766751e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787031602 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2787031602
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.4150876531
Short name T503
Test name
Test status
Simulation time 88741689 ps
CPU time 1.34 seconds
Started Feb 28 06:01:19 PM PST 24
Finished Feb 28 06:01:21 PM PST 24
Peak memory 217560 kb
Host smart-b70a55e4-aaa3-43be-9d9a-bf8ea0c699be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150876531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.4150876531
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.294883471
Short name T431
Test name
Test status
Simulation time 20926819 ps
CPU time 1.08 seconds
Started Feb 28 06:01:17 PM PST 24
Finished Feb 28 06:01:19 PM PST 24
Peak memory 215120 kb
Host smart-0f77537a-4724-4f8c-b37c-3a7453495d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294883471 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.294883471
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3689194424
Short name T195
Test name
Test status
Simulation time 20401439 ps
CPU time 1.06 seconds
Started Feb 28 06:01:23 PM PST 24
Finished Feb 28 06:01:24 PM PST 24
Peak memory 206544 kb
Host smart-e30aa9cf-b5e0-4c66-9a2d-2f891c57c387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689194424 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3689194424
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3770410408
Short name T782
Test name
Test status
Simulation time 379735342 ps
CPU time 2.87 seconds
Started Feb 28 06:01:18 PM PST 24
Finished Feb 28 06:01:21 PM PST 24
Peak memory 215772 kb
Host smart-0e06e2e4-1c1f-45ce-b215-a617d1cba8e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770410408 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3770410408
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2929267199
Short name T148
Test name
Test status
Simulation time 1150675441651 ps
CPU time 2113.8 seconds
Started Feb 28 06:01:17 PM PST 24
Finished Feb 28 06:36:32 PM PST 24
Peak memory 229196 kb
Host smart-9e139fd4-24a7-4a2b-8ef4-72eececc2c9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929267199 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2929267199
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2519332497
Short name T624
Test name
Test status
Simulation time 46503512 ps
CPU time 1.33 seconds
Started Feb 28 06:02:57 PM PST 24
Finished Feb 28 06:02:58 PM PST 24
Peak memory 218576 kb
Host smart-d8c77993-a925-452b-ac45-851ddbfe61b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519332497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2519332497
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1240426667
Short name T528
Test name
Test status
Simulation time 48750188 ps
CPU time 1.71 seconds
Started Feb 28 06:02:56 PM PST 24
Finished Feb 28 06:02:57 PM PST 24
Peak memory 219040 kb
Host smart-3e5e88bd-4f1f-44b5-9ab8-217a5f41eabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240426667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1240426667
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2554453097
Short name T259
Test name
Test status
Simulation time 49116035 ps
CPU time 1.75 seconds
Started Feb 28 06:02:56 PM PST 24
Finished Feb 28 06:02:58 PM PST 24
Peak memory 217220 kb
Host smart-8be42b5b-23e4-48fe-bf6d-ab25f52fc2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554453097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2554453097
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2145617981
Short name T385
Test name
Test status
Simulation time 78748234 ps
CPU time 1.32 seconds
Started Feb 28 06:02:58 PM PST 24
Finished Feb 28 06:02:59 PM PST 24
Peak memory 215912 kb
Host smart-949121d3-e119-4aab-a177-23f71191b7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145617981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2145617981
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1515262316
Short name T563
Test name
Test status
Simulation time 32135930 ps
CPU time 1.07 seconds
Started Feb 28 06:03:01 PM PST 24
Finished Feb 28 06:03:03 PM PST 24
Peak memory 218596 kb
Host smart-3bb96f64-ed18-4253-ae9b-1b90d300e7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515262316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1515262316
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1000689593
Short name T397
Test name
Test status
Simulation time 86544935 ps
CPU time 1.33 seconds
Started Feb 28 06:02:55 PM PST 24
Finished Feb 28 06:02:56 PM PST 24
Peak memory 215928 kb
Host smart-5d73b92c-b090-4884-83bb-017b820b07ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000689593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1000689593
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.779421693
Short name T424
Test name
Test status
Simulation time 44640809 ps
CPU time 1.61 seconds
Started Feb 28 06:02:55 PM PST 24
Finished Feb 28 06:02:57 PM PST 24
Peak memory 218940 kb
Host smart-a1b3c445-cb6d-4abb-af53-be8388508fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779421693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.779421693
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3866808785
Short name T9
Test name
Test status
Simulation time 288925315 ps
CPU time 3.7 seconds
Started Feb 28 06:02:57 PM PST 24
Finished Feb 28 06:03:01 PM PST 24
Peak memory 218768 kb
Host smart-892f95cf-aaea-4e84-8ffb-9bc17ddc9ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866808785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3866808785
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1055770496
Short name T232
Test name
Test status
Simulation time 54997921 ps
CPU time 1.24 seconds
Started Feb 28 06:02:56 PM PST 24
Finished Feb 28 06:02:57 PM PST 24
Peak memory 216064 kb
Host smart-61cf71ce-51ff-4fd2-acce-1574a1324699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055770496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1055770496
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1741605814
Short name T244
Test name
Test status
Simulation time 77538530 ps
CPU time 1.25 seconds
Started Feb 28 06:01:18 PM PST 24
Finished Feb 28 06:01:20 PM PST 24
Peak memory 215024 kb
Host smart-638cfc72-ba61-4845-a9e3-2c4da518309e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741605814 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1741605814
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3920744848
Short name T312
Test name
Test status
Simulation time 64966089 ps
CPU time 0.88 seconds
Started Feb 28 06:01:19 PM PST 24
Finished Feb 28 06:01:21 PM PST 24
Peak memory 205420 kb
Host smart-ae35869e-a23b-43fb-83b4-751c1a3e36f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920744848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3920744848
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3389612928
Short name T100
Test name
Test status
Simulation time 11549849 ps
CPU time 0.9 seconds
Started Feb 28 06:01:18 PM PST 24
Finished Feb 28 06:01:19 PM PST 24
Peak memory 215288 kb
Host smart-6377a328-03dc-4626-bf49-cff0ac653b62
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389612928 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3389612928
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_err.2338675182
Short name T826
Test name
Test status
Simulation time 25640527 ps
CPU time 0.99 seconds
Started Feb 28 06:01:18 PM PST 24
Finished Feb 28 06:01:19 PM PST 24
Peak memory 215940 kb
Host smart-e990a5ef-5928-48c9-81cd-23698ec51aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338675182 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2338675182
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.959035770
Short name T793
Test name
Test status
Simulation time 39072542 ps
CPU time 1.54 seconds
Started Feb 28 06:01:18 PM PST 24
Finished Feb 28 06:01:20 PM PST 24
Peak memory 217120 kb
Host smart-51ccd033-f3fc-43ee-ba42-e2bc55c16b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959035770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.959035770
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2625460968
Short name T46
Test name
Test status
Simulation time 58343870 ps
CPU time 0.93 seconds
Started Feb 28 06:01:20 PM PST 24
Finished Feb 28 06:01:21 PM PST 24
Peak memory 222340 kb
Host smart-415ca5a4-6d40-41f4-b145-cca029cc730f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625460968 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2625460968
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.2028247759
Short name T320
Test name
Test status
Simulation time 55789712 ps
CPU time 0.93 seconds
Started Feb 28 06:01:21 PM PST 24
Finished Feb 28 06:01:22 PM PST 24
Peak memory 214728 kb
Host smart-a79ffc75-086d-414e-8ff1-bb7e5b807017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028247759 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2028247759
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.279563480
Short name T293
Test name
Test status
Simulation time 190678851 ps
CPU time 1.37 seconds
Started Feb 28 06:01:19 PM PST 24
Finished Feb 28 06:01:21 PM PST 24
Peak memory 215908 kb
Host smart-8081d7fa-3910-4b51-a3b9-f9b5050633f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279563480 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.279563480
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2076360600
Short name T191
Test name
Test status
Simulation time 28593048448 ps
CPU time 240.11 seconds
Started Feb 28 06:01:17 PM PST 24
Finished Feb 28 06:05:18 PM PST 24
Peak memory 223136 kb
Host smart-b1203b86-8c2c-469d-9445-8e1db9a3903f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076360600 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2076360600
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.412005399
Short name T390
Test name
Test status
Simulation time 20103693 ps
CPU time 1.16 seconds
Started Feb 28 06:02:55 PM PST 24
Finished Feb 28 06:02:57 PM PST 24
Peak memory 216384 kb
Host smart-f089b9ae-3fb9-4fc1-a890-7b2819b82763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412005399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.412005399
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1072872800
Short name T653
Test name
Test status
Simulation time 38566317 ps
CPU time 1.24 seconds
Started Feb 28 06:03:01 PM PST 24
Finished Feb 28 06:03:03 PM PST 24
Peak memory 215996 kb
Host smart-54321e77-f6f7-4f8e-ad21-39630f6b2df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072872800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1072872800
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2647525147
Short name T795
Test name
Test status
Simulation time 60699110 ps
CPU time 1.1 seconds
Started Feb 28 06:03:01 PM PST 24
Finished Feb 28 06:03:03 PM PST 24
Peak memory 217192 kb
Host smart-b7a0baac-0ea1-4d15-9c08-0e649a7c0975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647525147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2647525147
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3366322940
Short name T794
Test name
Test status
Simulation time 209205942 ps
CPU time 2.68 seconds
Started Feb 28 06:02:58 PM PST 24
Finished Feb 28 06:03:00 PM PST 24
Peak memory 216304 kb
Host smart-2c445a47-4e79-40cd-9530-87439d57a523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366322940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3366322940
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1264168519
Short name T440
Test name
Test status
Simulation time 71802928 ps
CPU time 2.77 seconds
Started Feb 28 06:03:01 PM PST 24
Finished Feb 28 06:03:04 PM PST 24
Peak memory 217260 kb
Host smart-431be229-1ae4-43ba-af40-1c302d9c93cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264168519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1264168519
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1376037442
Short name T451
Test name
Test status
Simulation time 46012577 ps
CPU time 1.19 seconds
Started Feb 28 06:02:59 PM PST 24
Finished Feb 28 06:03:01 PM PST 24
Peak memory 216104 kb
Host smart-01914805-ddda-455c-b9e3-7ed1e3b5acc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376037442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1376037442
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3712145997
Short name T567
Test name
Test status
Simulation time 107594342 ps
CPU time 1.1 seconds
Started Feb 28 06:02:58 PM PST 24
Finished Feb 28 06:02:59 PM PST 24
Peak memory 215860 kb
Host smart-d4953ec8-d777-425b-800f-cb0ac6de2ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712145997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3712145997
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.426351267
Short name T417
Test name
Test status
Simulation time 82180624 ps
CPU time 1.2 seconds
Started Feb 28 06:03:07 PM PST 24
Finished Feb 28 06:03:08 PM PST 24
Peak memory 215992 kb
Host smart-7e9997cc-34a2-4b17-afb3-905c20d6cabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426351267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.426351267
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2752259729
Short name T493
Test name
Test status
Simulation time 44440786 ps
CPU time 1.78 seconds
Started Feb 28 06:02:59 PM PST 24
Finished Feb 28 06:03:01 PM PST 24
Peak memory 217992 kb
Host smart-812d8e2f-9f4a-4cf3-8492-ad26cc2da1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752259729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2752259729
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.4203043388
Short name T722
Test name
Test status
Simulation time 88039636 ps
CPU time 0.96 seconds
Started Feb 28 06:03:00 PM PST 24
Finished Feb 28 06:03:01 PM PST 24
Peak memory 215836 kb
Host smart-5b5d58ec-f679-4477-ab3b-9fe077087f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203043388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.4203043388
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.531783049
Short name T789
Test name
Test status
Simulation time 112347050 ps
CPU time 1.12 seconds
Started Feb 28 06:00:02 PM PST 24
Finished Feb 28 06:00:04 PM PST 24
Peak memory 215028 kb
Host smart-8b8f7708-7a74-4dea-9d5a-36caa6bab023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531783049 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.531783049
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3759411967
Short name T376
Test name
Test status
Simulation time 41755604 ps
CPU time 0.91 seconds
Started Feb 28 06:00:07 PM PST 24
Finished Feb 28 06:00:08 PM PST 24
Peak memory 206212 kb
Host smart-d2a8b839-3587-4235-b8b3-cd8bb1ee9a98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759411967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3759411967
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2587207779
Short name T811
Test name
Test status
Simulation time 75531242 ps
CPU time 0.88 seconds
Started Feb 28 06:00:07 PM PST 24
Finished Feb 28 06:00:08 PM PST 24
Peak memory 214944 kb
Host smart-e95929c0-9da6-47a1-84c9-a442d36cb8c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587207779 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2587207779
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_err.76370930
Short name T383
Test name
Test status
Simulation time 18693969 ps
CPU time 1.07 seconds
Started Feb 28 06:00:01 PM PST 24
Finished Feb 28 06:00:02 PM PST 24
Peak memory 217504 kb
Host smart-55d52936-6086-480c-b330-850f92964836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76370930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.76370930
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1038825948
Short name T489
Test name
Test status
Simulation time 104377984 ps
CPU time 1.15 seconds
Started Feb 28 06:00:02 PM PST 24
Finished Feb 28 06:00:03 PM PST 24
Peak memory 215988 kb
Host smart-e968b69a-8fe1-4704-97a3-9db28827ba10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038825948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1038825948
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1132596513
Short name T143
Test name
Test status
Simulation time 32722399 ps
CPU time 0.84 seconds
Started Feb 28 06:00:04 PM PST 24
Finished Feb 28 06:00:05 PM PST 24
Peak memory 214908 kb
Host smart-a10f2acb-48ae-4ae2-b89b-08946b016ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132596513 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1132596513
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_smoke.3545521434
Short name T432
Test name
Test status
Simulation time 23027501 ps
CPU time 0.94 seconds
Started Feb 28 05:59:59 PM PST 24
Finished Feb 28 06:00:00 PM PST 24
Peak memory 214680 kb
Host smart-90251a95-e7d6-432c-8d7d-944433aeec9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545521434 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3545521434
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1206471042
Short name T660
Test name
Test status
Simulation time 343858570 ps
CPU time 2.32 seconds
Started Feb 28 06:00:04 PM PST 24
Finished Feb 28 06:00:06 PM PST 24
Peak memory 214644 kb
Host smart-aae2c323-3dd2-4ba8-a27a-ab319bdb5b8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206471042 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1206471042
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3403211917
Short name T644
Test name
Test status
Simulation time 281425611376 ps
CPU time 2659.97 seconds
Started Feb 28 06:00:02 PM PST 24
Finished Feb 28 06:44:22 PM PST 24
Peak memory 226776 kb
Host smart-72b42dad-fd9e-4764-a526-343bb774b94c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403211917 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3403211917
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1173299960
Short name T104
Test name
Test status
Simulation time 195207373 ps
CPU time 1.39 seconds
Started Feb 28 06:01:23 PM PST 24
Finished Feb 28 06:01:25 PM PST 24
Peak memory 214960 kb
Host smart-d1662533-ce68-4fea-97f2-3a5e424494ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173299960 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1173299960
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2127482740
Short name T464
Test name
Test status
Simulation time 21739205 ps
CPU time 0.81 seconds
Started Feb 28 06:01:24 PM PST 24
Finished Feb 28 06:01:25 PM PST 24
Peak memory 205052 kb
Host smart-8e0a95a7-b4e0-4753-8300-e1cae483bf7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127482740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2127482740
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1116213620
Short name T98
Test name
Test status
Simulation time 12806565 ps
CPU time 0.9 seconds
Started Feb 28 06:01:25 PM PST 24
Finished Feb 28 06:01:26 PM PST 24
Peak memory 215020 kb
Host smart-4ec4bea7-84d1-4855-86c9-e651658702e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116213620 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1116213620
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.25399848
Short name T67
Test name
Test status
Simulation time 31543247 ps
CPU time 1.07 seconds
Started Feb 28 06:01:22 PM PST 24
Finished Feb 28 06:01:23 PM PST 24
Peak memory 217064 kb
Host smart-f4b1d184-9432-4a9b-b345-d1b3783d035f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25399848 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_dis
able_auto_req_mode.25399848
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3049900877
Short name T628
Test name
Test status
Simulation time 57092585 ps
CPU time 1.05 seconds
Started Feb 28 06:01:22 PM PST 24
Finished Feb 28 06:01:23 PM PST 24
Peak memory 217444 kb
Host smart-985faa25-a840-4780-b5c7-57289d08fe40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049900877 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3049900877
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3521322268
Short name T767
Test name
Test status
Simulation time 49173432 ps
CPU time 1.56 seconds
Started Feb 28 06:01:22 PM PST 24
Finished Feb 28 06:01:24 PM PST 24
Peak memory 217164 kb
Host smart-fbfefd88-e68b-4e5a-9110-4cf43c86a2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521322268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3521322268
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.499636769
Short name T500
Test name
Test status
Simulation time 20342107 ps
CPU time 1 seconds
Started Feb 28 06:01:25 PM PST 24
Finished Feb 28 06:01:26 PM PST 24
Peak memory 215216 kb
Host smart-31c19783-d987-4ba3-99a6-644becacaaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499636769 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.499636769
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2311123493
Short name T292
Test name
Test status
Simulation time 37127662 ps
CPU time 0.91 seconds
Started Feb 28 06:01:23 PM PST 24
Finished Feb 28 06:01:24 PM PST 24
Peak memory 214684 kb
Host smart-d144a4b8-253f-4068-854e-9560d5d05385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311123493 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2311123493
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3329764640
Short name T504
Test name
Test status
Simulation time 132502271 ps
CPU time 1.51 seconds
Started Feb 28 06:01:23 PM PST 24
Finished Feb 28 06:01:25 PM PST 24
Peak memory 216156 kb
Host smart-06b2f0d4-8785-41d8-83fb-bad1fbfa8f56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329764640 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3329764640
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1167079293
Short name T769
Test name
Test status
Simulation time 282640533413 ps
CPU time 486.59 seconds
Started Feb 28 06:01:24 PM PST 24
Finished Feb 28 06:09:30 PM PST 24
Peak memory 218440 kb
Host smart-4cd5f4c8-f891-4582-8045-68e98fac47bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167079293 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1167079293
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3192032102
Short name T673
Test name
Test status
Simulation time 69300592 ps
CPU time 1.11 seconds
Started Feb 28 06:01:21 PM PST 24
Finished Feb 28 06:01:23 PM PST 24
Peak memory 215044 kb
Host smart-d0a2976b-f2f4-4940-83af-a18c692d083a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192032102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3192032102
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3092567819
Short name T369
Test name
Test status
Simulation time 26172056 ps
CPU time 1.07 seconds
Started Feb 28 06:01:22 PM PST 24
Finished Feb 28 06:01:23 PM PST 24
Peak memory 206256 kb
Host smart-6e3fc292-6f63-49ec-9043-b89b99e02046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092567819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3092567819
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.1182025955
Short name T604
Test name
Test status
Simulation time 33934127 ps
CPU time 0.85 seconds
Started Feb 28 06:01:23 PM PST 24
Finished Feb 28 06:01:24 PM PST 24
Peak memory 214812 kb
Host smart-45032ad0-a50f-450c-9edb-7af98f39ef9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182025955 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1182025955
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.789036451
Short name T786
Test name
Test status
Simulation time 37032269 ps
CPU time 0.95 seconds
Started Feb 28 06:01:23 PM PST 24
Finished Feb 28 06:01:25 PM PST 24
Peak memory 217204 kb
Host smart-58b5a656-df8c-46b9-8097-ca93e21c86a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789036451 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_di
sable_auto_req_mode.789036451
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3674914496
Short name T659
Test name
Test status
Simulation time 20126004 ps
CPU time 1.22 seconds
Started Feb 28 06:01:24 PM PST 24
Finished Feb 28 06:01:26 PM PST 24
Peak memory 218864 kb
Host smart-a1dc7216-a866-43d5-8f6a-473c286b9d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674914496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3674914496
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1637823272
Short name T676
Test name
Test status
Simulation time 126840923 ps
CPU time 1.08 seconds
Started Feb 28 06:01:20 PM PST 24
Finished Feb 28 06:01:22 PM PST 24
Peak memory 215864 kb
Host smart-629813b7-0362-4943-b9b5-858145012d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637823272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1637823272
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1832405617
Short name T40
Test name
Test status
Simulation time 36975397 ps
CPU time 0.88 seconds
Started Feb 28 06:01:24 PM PST 24
Finished Feb 28 06:01:25 PM PST 24
Peak memory 214936 kb
Host smart-d135eda8-a84d-4858-9d88-885d5b8ca8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832405617 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1832405617
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.729374494
Short name T629
Test name
Test status
Simulation time 20087559 ps
CPU time 0.91 seconds
Started Feb 28 06:01:24 PM PST 24
Finished Feb 28 06:01:25 PM PST 24
Peak memory 214684 kb
Host smart-697cc2e2-ec4d-41b8-86de-a4e5118c98dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729374494 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.729374494
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3142656888
Short name T548
Test name
Test status
Simulation time 512911219 ps
CPU time 3.95 seconds
Started Feb 28 06:01:27 PM PST 24
Finished Feb 28 06:01:31 PM PST 24
Peak memory 217244 kb
Host smart-a04923fe-82f1-4ab2-9705-0485c44f649d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142656888 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3142656888
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.782775559
Short name T654
Test name
Test status
Simulation time 50292022042 ps
CPU time 618.25 seconds
Started Feb 28 06:01:23 PM PST 24
Finished Feb 28 06:11:42 PM PST 24
Peak memory 218044 kb
Host smart-af53541e-d566-4549-9fbb-b95ffc677cae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782775559 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.782775559
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1617106416
Short name T746
Test name
Test status
Simulation time 33713924 ps
CPU time 1.16 seconds
Started Feb 28 06:01:26 PM PST 24
Finished Feb 28 06:01:28 PM PST 24
Peak memory 215076 kb
Host smart-bd33fdfa-3e52-4d8f-82f1-359557e370bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617106416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1617106416
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2639926385
Short name T684
Test name
Test status
Simulation time 17996682 ps
CPU time 0.98 seconds
Started Feb 28 06:01:27 PM PST 24
Finished Feb 28 06:01:29 PM PST 24
Peak memory 205784 kb
Host smart-d321140c-ba11-48a6-bb72-3fecaf044adb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639926385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2639926385
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.396753102
Short name T587
Test name
Test status
Simulation time 40417282 ps
CPU time 1.04 seconds
Started Feb 28 06:01:24 PM PST 24
Finished Feb 28 06:01:26 PM PST 24
Peak memory 216064 kb
Host smart-83b0aef6-9528-4af9-8050-8a403979cb84
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396753102 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.396753102
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3910414676
Short name T404
Test name
Test status
Simulation time 18635779 ps
CPU time 1.11 seconds
Started Feb 28 06:01:26 PM PST 24
Finished Feb 28 06:01:27 PM PST 24
Peak memory 222452 kb
Host smart-3e14bb01-fcd4-448f-a08b-084cf8143a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910414676 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3910414676
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2513171491
Short name T439
Test name
Test status
Simulation time 69101138 ps
CPU time 1.49 seconds
Started Feb 28 06:01:26 PM PST 24
Finished Feb 28 06:01:28 PM PST 24
Peak memory 217192 kb
Host smart-755a8403-60b7-4881-8d6f-d87547fecd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513171491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2513171491
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.4127255811
Short name T777
Test name
Test status
Simulation time 22541527 ps
CPU time 1.18 seconds
Started Feb 28 06:01:26 PM PST 24
Finished Feb 28 06:01:27 PM PST 24
Peak memory 214900 kb
Host smart-8b72b179-4622-4c82-947f-111c35fedab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127255811 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.4127255811
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2019013877
Short name T685
Test name
Test status
Simulation time 20603331 ps
CPU time 1.01 seconds
Started Feb 28 06:01:25 PM PST 24
Finished Feb 28 06:01:27 PM PST 24
Peak memory 214704 kb
Host smart-736c37c8-f015-4d2c-93ac-546e0fc54b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019013877 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2019013877
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.377468510
Short name T197
Test name
Test status
Simulation time 293124301 ps
CPU time 3.14 seconds
Started Feb 28 06:01:22 PM PST 24
Finished Feb 28 06:01:25 PM PST 24
Peak memory 215856 kb
Host smart-c42e7cf8-d271-4c30-8b49-a25a7277d19e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377468510 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.377468510
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2254621483
Short name T163
Test name
Test status
Simulation time 36449214950 ps
CPU time 827.03 seconds
Started Feb 28 06:01:22 PM PST 24
Finished Feb 28 06:15:10 PM PST 24
Peak memory 220720 kb
Host smart-68bb7751-f0a9-4338-ab9d-a772ac6a40a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254621483 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2254621483
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert_test.1866573891
Short name T308
Test name
Test status
Simulation time 22701964 ps
CPU time 0.86 seconds
Started Feb 28 06:01:28 PM PST 24
Finished Feb 28 06:01:29 PM PST 24
Peak memory 206300 kb
Host smart-1f1c9323-83cd-4261-9acd-f3b2820034d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866573891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1866573891
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.3893007500
Short name T773
Test name
Test status
Simulation time 12679526 ps
CPU time 0.91 seconds
Started Feb 28 06:01:26 PM PST 24
Finished Feb 28 06:01:27 PM PST 24
Peak memory 215320 kb
Host smart-1aea17c0-eb7d-4abc-a601-b148de890564
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893007500 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3893007500
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1159996547
Short name T677
Test name
Test status
Simulation time 33102092 ps
CPU time 1.11 seconds
Started Feb 28 06:01:29 PM PST 24
Finished Feb 28 06:01:30 PM PST 24
Peak memory 215820 kb
Host smart-9b698fbb-30f2-44e6-83df-55d9df33fe7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159996547 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1159996547
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.3409615304
Short name T165
Test name
Test status
Simulation time 30652555 ps
CPU time 1.3 seconds
Started Feb 28 06:01:26 PM PST 24
Finished Feb 28 06:01:28 PM PST 24
Peak memory 218500 kb
Host smart-2ee701db-ae81-4103-877d-f7bad236921b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409615304 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3409615304
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3923153916
Short name T450
Test name
Test status
Simulation time 51868418 ps
CPU time 1.31 seconds
Started Feb 28 06:01:25 PM PST 24
Finished Feb 28 06:01:26 PM PST 24
Peak memory 216148 kb
Host smart-2b044d9d-950a-40d1-83db-0992766a163c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923153916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3923153916
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1870290106
Short name T144
Test name
Test status
Simulation time 27803230 ps
CPU time 0.84 seconds
Started Feb 28 06:01:26 PM PST 24
Finished Feb 28 06:01:27 PM PST 24
Peak memory 214960 kb
Host smart-127d775a-4ec8-43ba-b18e-dffa487bb505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870290106 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1870290106
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2034357971
Short name T425
Test name
Test status
Simulation time 49525212 ps
CPU time 0.97 seconds
Started Feb 28 06:01:25 PM PST 24
Finished Feb 28 06:01:26 PM PST 24
Peak memory 214788 kb
Host smart-91592e48-d737-42df-a3cb-4ae8cabe9359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034357971 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2034357971
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.549503347
Short name T636
Test name
Test status
Simulation time 900673233 ps
CPU time 4.74 seconds
Started Feb 28 06:01:24 PM PST 24
Finished Feb 28 06:01:29 PM PST 24
Peak memory 214760 kb
Host smart-a16ae0fd-bb54-4e59-b532-bc6748587163
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549503347 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.549503347
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3682703151
Short name T472
Test name
Test status
Simulation time 583073591285 ps
CPU time 1427.63 seconds
Started Feb 28 06:01:27 PM PST 24
Finished Feb 28 06:25:15 PM PST 24
Peak memory 224808 kb
Host smart-a71ef0d6-3653-441a-99be-9c0310c96d42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682703151 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3682703151
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1343559413
Short name T790
Test name
Test status
Simulation time 24967955 ps
CPU time 1.21 seconds
Started Feb 28 06:01:27 PM PST 24
Finished Feb 28 06:01:28 PM PST 24
Peak memory 215072 kb
Host smart-59c24fbc-20f4-438b-b908-be4351334617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343559413 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1343559413
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1544444517
Short name T291
Test name
Test status
Simulation time 31329149 ps
CPU time 1.11 seconds
Started Feb 28 06:01:28 PM PST 24
Finished Feb 28 06:01:29 PM PST 24
Peak memory 206084 kb
Host smart-6234d92a-6328-4a15-aa9d-bc3154a757f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544444517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1544444517
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.71780084
Short name T32
Test name
Test status
Simulation time 11461044 ps
CPU time 0.9 seconds
Started Feb 28 06:01:28 PM PST 24
Finished Feb 28 06:01:29 PM PST 24
Peak memory 214792 kb
Host smart-4df7de36-5d48-46f2-bf59-a20cc66080e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71780084 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.71780084
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2010830331
Short name T172
Test name
Test status
Simulation time 51648849 ps
CPU time 1.51 seconds
Started Feb 28 06:01:29 PM PST 24
Finished Feb 28 06:01:31 PM PST 24
Peak memory 218296 kb
Host smart-739f8cbd-d8c6-446d-8764-3c91431aac53
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010830331 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2010830331
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.1199839571
Short name T821
Test name
Test status
Simulation time 20691839 ps
CPU time 1.13 seconds
Started Feb 28 06:01:28 PM PST 24
Finished Feb 28 06:01:29 PM PST 24
Peak memory 218476 kb
Host smart-6630ea44-e746-453c-9748-8b92ecede3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199839571 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.1199839571
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2287496602
Short name T523
Test name
Test status
Simulation time 54437285 ps
CPU time 1.84 seconds
Started Feb 28 06:01:32 PM PST 24
Finished Feb 28 06:01:34 PM PST 24
Peak memory 217180 kb
Host smart-be513ab2-77d2-4746-a983-5719072f5c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287496602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2287496602
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2683224728
Short name T745
Test name
Test status
Simulation time 21484633 ps
CPU time 1.23 seconds
Started Feb 28 06:01:29 PM PST 24
Finished Feb 28 06:01:30 PM PST 24
Peak memory 222584 kb
Host smart-9c7d7678-ecf1-4872-a51a-cf913e6ce96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683224728 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2683224728
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2382301220
Short name T543
Test name
Test status
Simulation time 23577430 ps
CPU time 0.98 seconds
Started Feb 28 06:01:32 PM PST 24
Finished Feb 28 06:01:33 PM PST 24
Peak memory 214744 kb
Host smart-f9da02c0-07db-49eb-877f-57efb2cd70a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382301220 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2382301220
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.972560839
Short name T785
Test name
Test status
Simulation time 269907672 ps
CPU time 4.92 seconds
Started Feb 28 06:01:28 PM PST 24
Finished Feb 28 06:01:33 PM PST 24
Peak memory 215940 kb
Host smart-dada25f8-6789-4656-aede-33b85dc3a53d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972560839 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.972560839
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2308251067
Short name T458
Test name
Test status
Simulation time 81911291574 ps
CPU time 250.57 seconds
Started Feb 28 06:01:28 PM PST 24
Finished Feb 28 06:05:39 PM PST 24
Peak memory 217412 kb
Host smart-6656488c-d477-4bfe-89e5-c915f8fe80b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308251067 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2308251067
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3340191054
Short name T229
Test name
Test status
Simulation time 22427264 ps
CPU time 1.06 seconds
Started Feb 28 06:01:31 PM PST 24
Finished Feb 28 06:01:32 PM PST 24
Peak memory 214980 kb
Host smart-943680a9-f0f5-45c2-8359-8de90ff4a3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340191054 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3340191054
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2830087194
Short name T44
Test name
Test status
Simulation time 184548312 ps
CPU time 1.01 seconds
Started Feb 28 06:01:33 PM PST 24
Finished Feb 28 06:01:34 PM PST 24
Peak memory 205468 kb
Host smart-4d498689-13a7-4a1d-8171-3d5530863056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830087194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2830087194
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.4143836408
Short name T175
Test name
Test status
Simulation time 13804069 ps
CPU time 0.83 seconds
Started Feb 28 06:01:32 PM PST 24
Finished Feb 28 06:01:33 PM PST 24
Peak memory 215104 kb
Host smart-b1a48711-4879-4598-9871-53db2464066a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143836408 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.4143836408
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3442879376
Short name T516
Test name
Test status
Simulation time 44128522 ps
CPU time 1.19 seconds
Started Feb 28 06:01:35 PM PST 24
Finished Feb 28 06:01:36 PM PST 24
Peak memory 215784 kb
Host smart-e2aaec95-8aec-4208-b2b0-3431768188ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442879376 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3442879376
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1019041318
Short name T61
Test name
Test status
Simulation time 67600236 ps
CPU time 1.01 seconds
Started Feb 28 06:01:33 PM PST 24
Finished Feb 28 06:01:34 PM PST 24
Peak memory 229144 kb
Host smart-d88d8a14-5c3b-4139-84fa-58933e1faf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019041318 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1019041318
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2387669873
Short name T315
Test name
Test status
Simulation time 37260951 ps
CPU time 1.33 seconds
Started Feb 28 06:01:28 PM PST 24
Finished Feb 28 06:01:29 PM PST 24
Peak memory 217004 kb
Host smart-87f0076f-d437-49a5-b17a-408ff7e2c798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387669873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2387669873
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1182123283
Short name T391
Test name
Test status
Simulation time 28350572 ps
CPU time 1.01 seconds
Started Feb 28 06:01:31 PM PST 24
Finished Feb 28 06:01:32 PM PST 24
Peak memory 223396 kb
Host smart-20f1f455-d86d-486d-ac96-e26fd08abd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182123283 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1182123283
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3018265484
Short name T496
Test name
Test status
Simulation time 42625790 ps
CPU time 0.9 seconds
Started Feb 28 06:01:29 PM PST 24
Finished Feb 28 06:01:30 PM PST 24
Peak memory 214660 kb
Host smart-1d83cd6a-44d0-4e3f-b2d7-769f67655913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018265484 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3018265484
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.4199261848
Short name T199
Test name
Test status
Simulation time 140583046 ps
CPU time 3.04 seconds
Started Feb 28 06:01:32 PM PST 24
Finished Feb 28 06:01:35 PM PST 24
Peak memory 215808 kb
Host smart-ff07d7d6-c9ae-47d9-85fb-ebe508c409a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199261848 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.4199261848
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2392151731
Short name T393
Test name
Test status
Simulation time 13013380997 ps
CPU time 155.84 seconds
Started Feb 28 06:01:32 PM PST 24
Finished Feb 28 06:04:08 PM PST 24
Peak memory 217020 kb
Host smart-94bd0aee-b7fc-4047-99c6-304d34c66035
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392151731 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2392151731
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.2790249438
Short name T183
Test name
Test status
Simulation time 64271439 ps
CPU time 1.39 seconds
Started Feb 28 06:01:32 PM PST 24
Finished Feb 28 06:01:34 PM PST 24
Peak memory 215068 kb
Host smart-90c8ecca-15ec-4736-8201-a800e3e75d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790249438 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2790249438
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2048820435
Short name T502
Test name
Test status
Simulation time 23513612 ps
CPU time 0.87 seconds
Started Feb 28 06:01:37 PM PST 24
Finished Feb 28 06:01:38 PM PST 24
Peak memory 206200 kb
Host smart-355c2804-9308-4685-ab55-fd1f0c2c395f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048820435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2048820435
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1790848327
Short name T537
Test name
Test status
Simulation time 15800465 ps
CPU time 0.89 seconds
Started Feb 28 06:01:37 PM PST 24
Finished Feb 28 06:01:38 PM PST 24
Peak memory 214944 kb
Host smart-9bf69e5e-4692-42a1-9fb4-44f9b28c288a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790848327 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1790848327
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3008077341
Short name T477
Test name
Test status
Simulation time 40656534 ps
CPU time 1.02 seconds
Started Feb 28 06:01:37 PM PST 24
Finished Feb 28 06:01:39 PM PST 24
Peak memory 215764 kb
Host smart-139c17b2-6d41-492e-b68e-24341bbac55e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008077341 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3008077341
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1006721723
Short name T792
Test name
Test status
Simulation time 18607263 ps
CPU time 1.03 seconds
Started Feb 28 06:01:36 PM PST 24
Finished Feb 28 06:01:37 PM PST 24
Peak memory 217288 kb
Host smart-07b4c8cb-9981-44e3-82cd-44f89b2fa4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006721723 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1006721723
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1842126820
Short name T592
Test name
Test status
Simulation time 77363577 ps
CPU time 3.1 seconds
Started Feb 28 06:01:33 PM PST 24
Finished Feb 28 06:01:36 PM PST 24
Peak memory 216432 kb
Host smart-c2b30f42-d37e-4435-9fac-fccd4613ede6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842126820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1842126820
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2171001360
Short name T55
Test name
Test status
Simulation time 27895385 ps
CPU time 0.94 seconds
Started Feb 28 06:01:34 PM PST 24
Finished Feb 28 06:01:35 PM PST 24
Peak memory 214980 kb
Host smart-ea34edde-f15a-476c-93aa-d300e416bfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171001360 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2171001360
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3803967464
Short name T694
Test name
Test status
Simulation time 15305404 ps
CPU time 1.01 seconds
Started Feb 28 06:01:32 PM PST 24
Finished Feb 28 06:01:33 PM PST 24
Peak memory 214708 kb
Host smart-a2b6e10e-0e8d-43a8-9fdf-fe3a743ccb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803967464 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3803967464
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3776235131
Short name T731
Test name
Test status
Simulation time 281393901 ps
CPU time 5.42 seconds
Started Feb 28 06:01:30 PM PST 24
Finished Feb 28 06:01:36 PM PST 24
Peak memory 215860 kb
Host smart-707e071d-d8f3-428c-95f0-da5c904cb04f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776235131 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3776235131
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1981724353
Short name T60
Test name
Test status
Simulation time 36778733336 ps
CPU time 832.01 seconds
Started Feb 28 06:01:33 PM PST 24
Finished Feb 28 06:15:26 PM PST 24
Peak memory 218072 kb
Host smart-99229aac-5fac-453d-b99a-5cc0db357510
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981724353 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1981724353
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert_test.198166185
Short name T327
Test name
Test status
Simulation time 31564303 ps
CPU time 0.94 seconds
Started Feb 28 06:01:37 PM PST 24
Finished Feb 28 06:01:39 PM PST 24
Peak memory 205836 kb
Host smart-aa0632d7-7b5a-4487-a1e3-1caff99de764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198166185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.198166185
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.4079060764
Short name T806
Test name
Test status
Simulation time 41742707 ps
CPU time 0.79 seconds
Started Feb 28 06:01:36 PM PST 24
Finished Feb 28 06:01:37 PM PST 24
Peak memory 214712 kb
Host smart-ea3ec4dd-ebb1-4d47-8ccc-39e3f655aad8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079060764 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.4079060764
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1132957487
Short name T95
Test name
Test status
Simulation time 130834785 ps
CPU time 1.16 seconds
Started Feb 28 06:01:38 PM PST 24
Finished Feb 28 06:01:40 PM PST 24
Peak memory 215824 kb
Host smart-a244f09f-1702-413c-a759-48290acfc8e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132957487 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1132957487
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3340770017
Short name T827
Test name
Test status
Simulation time 36107435 ps
CPU time 1.51 seconds
Started Feb 28 06:01:39 PM PST 24
Finished Feb 28 06:01:40 PM PST 24
Peak memory 223436 kb
Host smart-aa60bb36-06a9-48c1-9bb4-40c01b8ec203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340770017 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3340770017
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1220335145
Short name T336
Test name
Test status
Simulation time 84998901 ps
CPU time 1.65 seconds
Started Feb 28 06:01:38 PM PST 24
Finished Feb 28 06:01:40 PM PST 24
Peak memory 217372 kb
Host smart-6fdca200-b05a-4abf-8fb0-61cc9df0c3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220335145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1220335145
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.543767291
Short name T142
Test name
Test status
Simulation time 22962204 ps
CPU time 0.95 seconds
Started Feb 28 06:01:40 PM PST 24
Finished Feb 28 06:01:41 PM PST 24
Peak memory 215264 kb
Host smart-f5d5b659-3852-4797-a475-34793bdc0363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543767291 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.543767291
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.153535920
Short name T487
Test name
Test status
Simulation time 17953806 ps
CPU time 1.08 seconds
Started Feb 28 06:01:40 PM PST 24
Finished Feb 28 06:01:41 PM PST 24
Peak memory 214692 kb
Host smart-19ae2fd2-95f7-4bef-83a7-71b304a7813b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153535920 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.153535920
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1441441040
Short name T780
Test name
Test status
Simulation time 295491554 ps
CPU time 2.1 seconds
Started Feb 28 06:01:37 PM PST 24
Finished Feb 28 06:01:40 PM PST 24
Peak memory 214664 kb
Host smart-0759f9e2-5196-48d0-ace9-1ee672c2c62b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441441040 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1441441040
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1084243832
Short name T714
Test name
Test status
Simulation time 56245933072 ps
CPU time 1299.16 seconds
Started Feb 28 06:01:35 PM PST 24
Finished Feb 28 06:23:14 PM PST 24
Peak memory 220388 kb
Host smart-59f81ba5-8abf-41a4-a26a-14299a04d9eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084243832 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1084243832
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1694165715
Short name T243
Test name
Test status
Simulation time 78047749 ps
CPU time 1.2 seconds
Started Feb 28 06:01:42 PM PST 24
Finished Feb 28 06:01:43 PM PST 24
Peak memory 214992 kb
Host smart-d63fd46c-4c35-4ad8-876a-156274be11ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694165715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1694165715
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2072582698
Short name T550
Test name
Test status
Simulation time 49341437 ps
CPU time 0.87 seconds
Started Feb 28 06:01:55 PM PST 24
Finished Feb 28 06:01:56 PM PST 24
Peak memory 206212 kb
Host smart-db3ac93c-2cc8-436b-82a4-7819604609b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072582698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2072582698
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2589785414
Short name T121
Test name
Test status
Simulation time 89876759 ps
CPU time 0.92 seconds
Started Feb 28 06:01:50 PM PST 24
Finished Feb 28 06:01:51 PM PST 24
Peak memory 215092 kb
Host smart-40887ec7-1166-42e4-b88f-37738d11fc4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589785414 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2589785414
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2355773010
Short name T36
Test name
Test status
Simulation time 448158468 ps
CPU time 1.11 seconds
Started Feb 28 06:01:43 PM PST 24
Finished Feb 28 06:01:45 PM PST 24
Peak memory 215916 kb
Host smart-e21aae7d-77fc-4c20-af6b-d8504ca9855e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355773010 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2355773010
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.4280457744
Short name T80
Test name
Test status
Simulation time 102841693 ps
CPU time 1.2 seconds
Started Feb 28 06:01:41 PM PST 24
Finished Feb 28 06:01:43 PM PST 24
Peak memory 229048 kb
Host smart-55b7b2f5-899d-468f-a8e7-48e7541c49db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280457744 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.4280457744
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2366172348
Short name T59
Test name
Test status
Simulation time 47446577 ps
CPU time 1.28 seconds
Started Feb 28 06:01:38 PM PST 24
Finished Feb 28 06:01:40 PM PST 24
Peak memory 216052 kb
Host smart-7a1386f2-0040-41fb-b35e-91e98d3bc26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366172348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2366172348
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3001027018
Short name T136
Test name
Test status
Simulation time 20436258 ps
CPU time 1.06 seconds
Started Feb 28 06:01:38 PM PST 24
Finished Feb 28 06:01:40 PM PST 24
Peak memory 215144 kb
Host smart-a68fc6d8-cebb-41dc-894f-83082ff8f6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001027018 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3001027018
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.995087686
Short name T294
Test name
Test status
Simulation time 51576231 ps
CPU time 0.95 seconds
Started Feb 28 06:01:41 PM PST 24
Finished Feb 28 06:01:43 PM PST 24
Peak memory 214664 kb
Host smart-40227823-66dd-45bc-86f4-57581df9edca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995087686 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.995087686
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3989118451
Short name T698
Test name
Test status
Simulation time 247302119 ps
CPU time 1.6 seconds
Started Feb 28 06:01:35 PM PST 24
Finished Feb 28 06:01:37 PM PST 24
Peak memory 214572 kb
Host smart-89752a66-f0bf-4126-8d65-e3cadef74367
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989118451 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3989118451
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1334680862
Short name T479
Test name
Test status
Simulation time 23765360215 ps
CPU time 604.88 seconds
Started Feb 28 06:01:38 PM PST 24
Finished Feb 28 06:11:43 PM PST 24
Peak memory 217724 kb
Host smart-b313ca45-0f0b-4988-9cd9-3cf729528dba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334680862 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1334680862
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2079656533
Short name T775
Test name
Test status
Simulation time 221447235 ps
CPU time 1.42 seconds
Started Feb 28 06:01:49 PM PST 24
Finished Feb 28 06:01:51 PM PST 24
Peak memory 215024 kb
Host smart-d85ffd82-ff01-44ce-b50f-db0300d1ac6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079656533 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2079656533
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.63816301
Short name T302
Test name
Test status
Simulation time 31062029 ps
CPU time 0.95 seconds
Started Feb 28 06:01:44 PM PST 24
Finished Feb 28 06:01:45 PM PST 24
Peak memory 205852 kb
Host smart-20c59778-cd25-4d72-87b8-1c92eaad3856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63816301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.63816301
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.125116192
Short name T119
Test name
Test status
Simulation time 53324998 ps
CPU time 0.88 seconds
Started Feb 28 06:01:48 PM PST 24
Finished Feb 28 06:01:49 PM PST 24
Peak memory 215076 kb
Host smart-70f7b26d-017a-4704-8fb6-7c2e6fecb539
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125116192 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.125116192
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1508763054
Short name T75
Test name
Test status
Simulation time 266633287 ps
CPU time 1.09 seconds
Started Feb 28 06:01:41 PM PST 24
Finished Feb 28 06:01:42 PM PST 24
Peak memory 215676 kb
Host smart-911cbe8a-5eb2-4491-a7d4-fbb996f5df3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508763054 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1508763054
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2538808081
Short name T170
Test name
Test status
Simulation time 74561870 ps
CPU time 1.16 seconds
Started Feb 28 06:01:49 PM PST 24
Finished Feb 28 06:01:50 PM PST 24
Peak memory 223408 kb
Host smart-3f51a3a7-e507-4915-ace6-20705c8155ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538808081 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2538808081
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3614466920
Short name T519
Test name
Test status
Simulation time 39562397 ps
CPU time 1.69 seconds
Started Feb 28 06:01:40 PM PST 24
Finished Feb 28 06:01:42 PM PST 24
Peak memory 217384 kb
Host smart-76de8d56-3026-4e7a-9559-d4da04e28a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614466920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3614466920
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.4058876780
Short name T816
Test name
Test status
Simulation time 29349304 ps
CPU time 1.03 seconds
Started Feb 28 06:01:43 PM PST 24
Finished Feb 28 06:01:45 PM PST 24
Peak memory 214984 kb
Host smart-2019d0fb-c313-4163-902a-b9d54c8c8eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058876780 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.4058876780
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1046720394
Short name T405
Test name
Test status
Simulation time 51734799 ps
CPU time 0.9 seconds
Started Feb 28 06:01:39 PM PST 24
Finished Feb 28 06:01:40 PM PST 24
Peak memory 214728 kb
Host smart-f9a2a78c-e8d6-420d-a1d2-d44238f1a984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046720394 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1046720394
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.408271508
Short name T381
Test name
Test status
Simulation time 397024971 ps
CPU time 7.6 seconds
Started Feb 28 06:01:41 PM PST 24
Finished Feb 28 06:01:49 PM PST 24
Peak memory 215824 kb
Host smart-9dfe2b3e-0f2e-40e3-8dd7-fc762d5e94a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408271508 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.408271508
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3136301574
Short name T194
Test name
Test status
Simulation time 166134547701 ps
CPU time 969.77 seconds
Started Feb 28 06:01:40 PM PST 24
Finished Feb 28 06:17:50 PM PST 24
Peak memory 219552 kb
Host smart-bbea0708-ddc9-47e6-8594-e3ef1137e58f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136301574 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3136301574
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3105657559
Short name T103
Test name
Test status
Simulation time 38285693 ps
CPU time 1.26 seconds
Started Feb 28 06:00:07 PM PST 24
Finished Feb 28 06:00:08 PM PST 24
Peak memory 214960 kb
Host smart-72778069-1627-4342-a3d3-bd4874ceb55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105657559 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3105657559
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3751895984
Short name T42
Test name
Test status
Simulation time 37440622 ps
CPU time 0.87 seconds
Started Feb 28 06:00:11 PM PST 24
Finished Feb 28 06:00:12 PM PST 24
Peak memory 206104 kb
Host smart-9fede855-1fd7-4e3e-bbf6-f2a9cc4d850d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751895984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3751895984
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.522322153
Short name T174
Test name
Test status
Simulation time 16198604 ps
CPU time 0.9 seconds
Started Feb 28 06:00:10 PM PST 24
Finished Feb 28 06:00:11 PM PST 24
Peak memory 215164 kb
Host smart-4de5fa3a-d4e5-4338-a1d0-fc29b6f81602
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522322153 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.522322153
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2922324845
Short name T444
Test name
Test status
Simulation time 45773681 ps
CPU time 1.05 seconds
Started Feb 28 06:00:10 PM PST 24
Finished Feb 28 06:00:11 PM PST 24
Peak memory 217276 kb
Host smart-df344e92-34bf-464e-9bc3-d9033a85529f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922324845 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2922324845
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2925109635
Short name T116
Test name
Test status
Simulation time 19280421 ps
CPU time 1.12 seconds
Started Feb 28 06:00:08 PM PST 24
Finished Feb 28 06:00:09 PM PST 24
Peak memory 222472 kb
Host smart-cbca8cac-fc76-478e-9b43-643135b613f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925109635 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2925109635
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.4027093716
Short name T572
Test name
Test status
Simulation time 23641022 ps
CPU time 1.18 seconds
Started Feb 28 06:00:06 PM PST 24
Finished Feb 28 06:00:07 PM PST 24
Peak memory 218456 kb
Host smart-dd74306a-049b-494d-a938-e40189778c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027093716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.4027093716
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2465834924
Short name T448
Test name
Test status
Simulation time 40243567 ps
CPU time 0.97 seconds
Started Feb 28 06:00:06 PM PST 24
Finished Feb 28 06:00:07 PM PST 24
Peak memory 215036 kb
Host smart-175199bb-0564-4438-b0c9-c9bcaf4b2594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465834924 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2465834924
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2055278944
Short name T241
Test name
Test status
Simulation time 75074987 ps
CPU time 0.84 seconds
Started Feb 28 06:00:05 PM PST 24
Finished Feb 28 06:00:06 PM PST 24
Peak memory 206512 kb
Host smart-a61dc63b-6fb2-4bff-9a0d-15b8b62adcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055278944 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2055278944
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1795516756
Short name T53
Test name
Test status
Simulation time 1157057201 ps
CPU time 4.28 seconds
Started Feb 28 06:00:10 PM PST 24
Finished Feb 28 06:00:14 PM PST 24
Peak memory 234900 kb
Host smart-67e52118-0206-46cf-8758-11fb0eb08421
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795516756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1795516756
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.94574233
Short name T820
Test name
Test status
Simulation time 16351096 ps
CPU time 0.96 seconds
Started Feb 28 06:00:06 PM PST 24
Finished Feb 28 06:00:07 PM PST 24
Peak memory 214644 kb
Host smart-7c21c991-e179-4da8-9462-79f34b79e147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94574233 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.94574233
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2152780926
Short name T655
Test name
Test status
Simulation time 174167203 ps
CPU time 3.72 seconds
Started Feb 28 06:00:10 PM PST 24
Finished Feb 28 06:00:14 PM PST 24
Peak memory 214740 kb
Host smart-20659da5-cb45-412f-b906-b31c56795839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152780926 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2152780926
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3210436545
Short name T505
Test name
Test status
Simulation time 19400806233 ps
CPU time 337.57 seconds
Started Feb 28 06:00:07 PM PST 24
Finished Feb 28 06:05:44 PM PST 24
Peak memory 220064 kb
Host smart-845ff373-ec47-4204-9bd4-c38771733ff7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210436545 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3210436545
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.105028035
Short name T585
Test name
Test status
Simulation time 27424977 ps
CPU time 1.27 seconds
Started Feb 28 06:01:40 PM PST 24
Finished Feb 28 06:01:41 PM PST 24
Peak memory 215004 kb
Host smart-e6d5f44d-be4f-4f51-9a9d-7a896982aed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105028035 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.105028035
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3828291281
Short name T735
Test name
Test status
Simulation time 42748298 ps
CPU time 0.97 seconds
Started Feb 28 06:01:46 PM PST 24
Finished Feb 28 06:01:47 PM PST 24
Peak memory 205940 kb
Host smart-054ead80-4222-4aa6-a708-11de61602536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828291281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3828291281
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3131466307
Short name T574
Test name
Test status
Simulation time 28706737 ps
CPU time 0.9 seconds
Started Feb 28 06:01:42 PM PST 24
Finished Feb 28 06:01:43 PM PST 24
Peak memory 215264 kb
Host smart-1707c329-5b79-43f7-84f8-7f7ac37f9a10
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131466307 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3131466307
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2142126131
Short name T535
Test name
Test status
Simulation time 44901836 ps
CPU time 1.08 seconds
Started Feb 28 06:01:45 PM PST 24
Finished Feb 28 06:01:46 PM PST 24
Peak memory 216868 kb
Host smart-8eb62b36-3c93-4262-9ffc-3a4f4345038a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142126131 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2142126131
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1285644373
Short name T71
Test name
Test status
Simulation time 26266516 ps
CPU time 1.25 seconds
Started Feb 28 06:01:40 PM PST 24
Finished Feb 28 06:01:41 PM PST 24
Peak memory 229136 kb
Host smart-6d757b99-ad98-42cb-8ade-3ef76789850d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285644373 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1285644373
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.80657752
Short name T835
Test name
Test status
Simulation time 19961899 ps
CPU time 1.12 seconds
Started Feb 28 06:01:40 PM PST 24
Finished Feb 28 06:01:41 PM PST 24
Peak memory 218656 kb
Host smart-a95f79e4-d9b9-4cc8-ae59-64e439a51b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80657752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.80657752
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3086059376
Short name T754
Test name
Test status
Simulation time 21154458 ps
CPU time 1.26 seconds
Started Feb 28 06:01:42 PM PST 24
Finished Feb 28 06:01:43 PM PST 24
Peak memory 222464 kb
Host smart-04970fea-d978-468a-b8f4-f4fdfc1ffcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086059376 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3086059376
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1893369666
Short name T151
Test name
Test status
Simulation time 62285930 ps
CPU time 0.9 seconds
Started Feb 28 06:01:43 PM PST 24
Finished Feb 28 06:01:44 PM PST 24
Peak memory 214692 kb
Host smart-120d8470-1fe2-4b38-b29a-82507a51e4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893369666 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1893369666
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3495776298
Short name T728
Test name
Test status
Simulation time 201425871 ps
CPU time 4.12 seconds
Started Feb 28 06:01:50 PM PST 24
Finished Feb 28 06:01:55 PM PST 24
Peak memory 214684 kb
Host smart-4b54eab9-92e8-4572-82ae-8764e3add919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495776298 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3495776298
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3947867108
Short name T403
Test name
Test status
Simulation time 802489022658 ps
CPU time 1599.67 seconds
Started Feb 28 06:01:49 PM PST 24
Finished Feb 28 06:28:29 PM PST 24
Peak memory 231096 kb
Host smart-6cdd7b81-741d-4b7e-b49f-701a1623fe47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947867108 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3947867108
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1381889118
Short name T153
Test name
Test status
Simulation time 26705572 ps
CPU time 1.18 seconds
Started Feb 28 06:01:43 PM PST 24
Finished Feb 28 06:01:45 PM PST 24
Peak memory 215028 kb
Host smart-3214cf43-e092-4ace-8734-797e66879384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381889118 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1381889118
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.4139590973
Short name T306
Test name
Test status
Simulation time 14377567 ps
CPU time 0.9 seconds
Started Feb 28 06:01:46 PM PST 24
Finished Feb 28 06:01:47 PM PST 24
Peak memory 206180 kb
Host smart-ffe9a330-ddf9-4d1c-bc66-bd8b27d9e1ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139590973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.4139590973
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2278833918
Short name T120
Test name
Test status
Simulation time 12882293 ps
CPU time 0.91 seconds
Started Feb 28 06:01:43 PM PST 24
Finished Feb 28 06:01:45 PM PST 24
Peak memory 215300 kb
Host smart-02b27585-c97a-4a39-87dc-6ac82ed6acc6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278833918 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2278833918
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1262937050
Short name T182
Test name
Test status
Simulation time 18688167 ps
CPU time 0.96 seconds
Started Feb 28 06:01:43 PM PST 24
Finished Feb 28 06:01:45 PM PST 24
Peak memory 216748 kb
Host smart-64aa2e44-ac53-49d8-9733-248d054e68fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262937050 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1262937050
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2313604888
Short name T709
Test name
Test status
Simulation time 22682847 ps
CPU time 1.2 seconds
Started Feb 28 06:01:44 PM PST 24
Finished Feb 28 06:01:45 PM PST 24
Peak memory 217468 kb
Host smart-82a6415e-f854-4551-bffa-2f7189eb3448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313604888 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2313604888
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1512977405
Short name T422
Test name
Test status
Simulation time 260074513 ps
CPU time 1.27 seconds
Started Feb 28 06:01:45 PM PST 24
Finished Feb 28 06:01:46 PM PST 24
Peak memory 218956 kb
Host smart-db106c48-c0b6-451a-988e-32b712868415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512977405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1512977405
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1850764590
Short name T437
Test name
Test status
Simulation time 23417417 ps
CPU time 1.21 seconds
Started Feb 28 06:01:44 PM PST 24
Finished Feb 28 06:01:45 PM PST 24
Peak memory 231944 kb
Host smart-d48edf78-fee3-4a95-8c01-19b2b23ac152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850764590 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1850764590
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3416134992
Short name T800
Test name
Test status
Simulation time 41400511 ps
CPU time 0.87 seconds
Started Feb 28 06:01:43 PM PST 24
Finished Feb 28 06:01:44 PM PST 24
Peak memory 206604 kb
Host smart-78e28568-03b8-40c7-b95f-cc7fe2cf7931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416134992 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3416134992
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3531740481
Short name T716
Test name
Test status
Simulation time 704529191 ps
CPU time 4.68 seconds
Started Feb 28 06:01:48 PM PST 24
Finished Feb 28 06:01:52 PM PST 24
Peak memory 214908 kb
Host smart-ba1ace19-a145-4fa2-af88-db0450f14f0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531740481 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3531740481
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.4169159714
Short name T817
Test name
Test status
Simulation time 224954720454 ps
CPU time 1306.24 seconds
Started Feb 28 06:01:43 PM PST 24
Finished Feb 28 06:23:31 PM PST 24
Peak memory 222636 kb
Host smart-dc7aa5fb-4f45-4a9d-909e-75a6db9258d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169159714 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.4169159714
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1807531070
Short name T156
Test name
Test status
Simulation time 112302644 ps
CPU time 1.11 seconds
Started Feb 28 06:01:49 PM PST 24
Finished Feb 28 06:01:51 PM PST 24
Peak memory 215008 kb
Host smart-e24963a5-96c5-4cff-9514-3c9cd74e4ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807531070 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1807531070
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.27491100
Short name T739
Test name
Test status
Simulation time 17671770 ps
CPU time 0.84 seconds
Started Feb 28 06:01:49 PM PST 24
Finished Feb 28 06:01:50 PM PST 24
Peak memory 204984 kb
Host smart-ee061d6d-a680-4c65-a966-70a005948186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27491100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.27491100
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2786154428
Short name T834
Test name
Test status
Simulation time 26651425 ps
CPU time 0.86 seconds
Started Feb 28 06:01:48 PM PST 24
Finished Feb 28 06:01:49 PM PST 24
Peak memory 214880 kb
Host smart-9f7204e6-abcb-4910-9806-695ff65949e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786154428 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2786154428
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1207143233
Short name T626
Test name
Test status
Simulation time 48848217 ps
CPU time 1.04 seconds
Started Feb 28 06:01:46 PM PST 24
Finished Feb 28 06:01:47 PM PST 24
Peak memory 215932 kb
Host smart-d5070df2-f30f-46b5-a8ca-1bd5d8e5410f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207143233 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1207143233
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.656877397
Short name T525
Test name
Test status
Simulation time 20438929 ps
CPU time 1.06 seconds
Started Feb 28 06:01:49 PM PST 24
Finished Feb 28 06:01:51 PM PST 24
Peak memory 218796 kb
Host smart-b954bbef-336a-4af4-b390-03f4dfef591d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656877397 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.656877397
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.4256015988
Short name T491
Test name
Test status
Simulation time 915531502 ps
CPU time 5.78 seconds
Started Feb 28 06:01:43 PM PST 24
Finished Feb 28 06:01:50 PM PST 24
Peak memory 217212 kb
Host smart-9996117a-d0c2-4b26-91f5-456175d090fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256015988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.4256015988
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2936583859
Short name T729
Test name
Test status
Simulation time 22407412 ps
CPU time 1.06 seconds
Started Feb 28 06:01:43 PM PST 24
Finished Feb 28 06:01:45 PM PST 24
Peak memory 214792 kb
Host smart-65eb0b42-fb23-43fd-8e1e-2713cc3b5a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936583859 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2936583859
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3486169638
Short name T695
Test name
Test status
Simulation time 16889690 ps
CPU time 1.03 seconds
Started Feb 28 06:01:42 PM PST 24
Finished Feb 28 06:01:43 PM PST 24
Peak memory 214672 kb
Host smart-3e1cf5ea-6b27-4cda-b8a4-5c5dfb1a75ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486169638 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3486169638
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1952049001
Short name T529
Test name
Test status
Simulation time 539816576 ps
CPU time 5.17 seconds
Started Feb 28 06:01:43 PM PST 24
Finished Feb 28 06:01:49 PM PST 24
Peak memory 215936 kb
Host smart-59503944-7f88-4598-984c-9d32977fc577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952049001 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1952049001
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.201971141
Short name T146
Test name
Test status
Simulation time 37281852225 ps
CPU time 544.39 seconds
Started Feb 28 06:01:43 PM PST 24
Finished Feb 28 06:10:48 PM PST 24
Peak memory 217340 kb
Host smart-30e5198d-16ab-496a-8408-aa41b447de4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201971141 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.201971141
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2797892913
Short name T108
Test name
Test status
Simulation time 66311734 ps
CPU time 1.15 seconds
Started Feb 28 06:01:49 PM PST 24
Finished Feb 28 06:01:51 PM PST 24
Peak memory 215076 kb
Host smart-853673e1-d7d6-43ed-bfb4-eb3091faa01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797892913 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2797892913
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3910092306
Short name T394
Test name
Test status
Simulation time 67214015 ps
CPU time 0.83 seconds
Started Feb 28 06:01:51 PM PST 24
Finished Feb 28 06:01:52 PM PST 24
Peak memory 206036 kb
Host smart-cfe6c51d-64a5-4104-a2de-a34c0e88636d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910092306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3910092306
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.133821110
Short name T396
Test name
Test status
Simulation time 68411413 ps
CPU time 1.13 seconds
Started Feb 28 06:01:49 PM PST 24
Finished Feb 28 06:01:51 PM PST 24
Peak memory 215948 kb
Host smart-f7ffeafa-6614-494c-b5d3-01ae28c5a02b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133821110 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.133821110
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.4283211042
Short name T738
Test name
Test status
Simulation time 31291802 ps
CPU time 0.95 seconds
Started Feb 28 06:01:51 PM PST 24
Finished Feb 28 06:01:52 PM PST 24
Peak memory 217272 kb
Host smart-8f524b27-83b5-4f5a-a9ae-16828267cf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283211042 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.4283211042
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1932836083
Short name T809
Test name
Test status
Simulation time 32759000 ps
CPU time 1.32 seconds
Started Feb 28 06:01:48 PM PST 24
Finished Feb 28 06:01:49 PM PST 24
Peak memory 216032 kb
Host smart-c8d0ba35-0afa-440b-b1da-eaa26bc1e65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932836083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1932836083
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.4528559
Short name T706
Test name
Test status
Simulation time 26514439 ps
CPU time 1.15 seconds
Started Feb 28 06:01:51 PM PST 24
Finished Feb 28 06:01:53 PM PST 24
Peak memory 222788 kb
Host smart-f17358e6-0eac-4c0c-a00e-c67c2c01fd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4528559 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.4528559
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.310020338
Short name T447
Test name
Test status
Simulation time 29799128 ps
CPU time 1.08 seconds
Started Feb 28 06:01:50 PM PST 24
Finished Feb 28 06:01:51 PM PST 24
Peak memory 214844 kb
Host smart-c1160913-6ea9-4fad-8190-3ca990731c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310020338 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.310020338
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.115970314
Short name T590
Test name
Test status
Simulation time 374335897 ps
CPU time 4.05 seconds
Started Feb 28 06:01:47 PM PST 24
Finished Feb 28 06:01:51 PM PST 24
Peak memory 215720 kb
Host smart-1f5e74be-e9be-4d3b-9d1e-1549330b0cd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115970314 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.115970314
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.253776681
Short name T323
Test name
Test status
Simulation time 173987637510 ps
CPU time 1484.28 seconds
Started Feb 28 06:01:48 PM PST 24
Finished Feb 28 06:26:32 PM PST 24
Peak memory 224768 kb
Host smart-5f0bfbb6-d72d-4d41-8bf3-4f333f205541
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253776681 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.253776681
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3055135888
Short name T109
Test name
Test status
Simulation time 71960350 ps
CPU time 1.09 seconds
Started Feb 28 06:01:52 PM PST 24
Finished Feb 28 06:01:53 PM PST 24
Peak memory 215060 kb
Host smart-475f37a1-8021-4d6b-ae8b-b7290ea4a13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055135888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3055135888
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.597575156
Short name T618
Test name
Test status
Simulation time 39194502 ps
CPU time 0.86 seconds
Started Feb 28 06:01:53 PM PST 24
Finished Feb 28 06:01:54 PM PST 24
Peak memory 206200 kb
Host smart-d06d0a37-1bd3-4e1a-97c4-a5639c3240c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597575156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.597575156
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.1136151377
Short name T125
Test name
Test status
Simulation time 40575806 ps
CPU time 0.79 seconds
Started Feb 28 06:01:54 PM PST 24
Finished Feb 28 06:01:55 PM PST 24
Peak memory 215228 kb
Host smart-2990ff8b-71c3-4099-aea9-7c7adb11ab43
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136151377 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1136151377
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.688943173
Short name T713
Test name
Test status
Simulation time 58130145 ps
CPU time 1.14 seconds
Started Feb 28 06:01:54 PM PST 24
Finished Feb 28 06:01:55 PM PST 24
Peak memory 215708 kb
Host smart-76ca3ed3-99d1-428c-a689-b781bda78243
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688943173 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.688943173
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.4001965243
Short name T90
Test name
Test status
Simulation time 25490088 ps
CPU time 1.08 seconds
Started Feb 28 06:01:49 PM PST 24
Finished Feb 28 06:01:50 PM PST 24
Peak memory 229136 kb
Host smart-55bc3eec-566d-4ce4-a389-d208f5e4fa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001965243 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.4001965243
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2073475177
Short name T37
Test name
Test status
Simulation time 66731467 ps
CPU time 1.35 seconds
Started Feb 28 06:01:50 PM PST 24
Finished Feb 28 06:01:51 PM PST 24
Peak memory 217036 kb
Host smart-69c46f0c-93db-4bd1-9069-0d4a75575a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073475177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2073475177
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1811861774
Short name T138
Test name
Test status
Simulation time 89354636 ps
CPU time 0.84 seconds
Started Feb 28 06:01:49 PM PST 24
Finished Feb 28 06:01:50 PM PST 24
Peak memory 214984 kb
Host smart-b2521586-ad20-4a96-a6a7-a3913c347a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811861774 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1811861774
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1118294612
Short name T442
Test name
Test status
Simulation time 181482097 ps
CPU time 0.9 seconds
Started Feb 28 06:01:51 PM PST 24
Finished Feb 28 06:01:52 PM PST 24
Peak memory 214708 kb
Host smart-68ed1712-b98e-4c80-9809-231c55ce000d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118294612 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1118294612
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.162883414
Short name T662
Test name
Test status
Simulation time 443851282 ps
CPU time 4.67 seconds
Started Feb 28 06:01:49 PM PST 24
Finished Feb 28 06:01:54 PM PST 24
Peak memory 214676 kb
Host smart-a4f00475-a6d5-40f1-8b7a-a6144d76cc30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162883414 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.162883414
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.3125147500
Short name T575
Test name
Test status
Simulation time 45240420930 ps
CPU time 1155.46 seconds
Started Feb 28 06:01:51 PM PST 24
Finished Feb 28 06:21:07 PM PST 24
Peak memory 219256 kb
Host smart-2aef42b7-fd7b-407a-a6a6-d34fd7b39c9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125147500 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.3125147500
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert_test.1244897790
Short name T299
Test name
Test status
Simulation time 15187217 ps
CPU time 0.87 seconds
Started Feb 28 06:01:55 PM PST 24
Finished Feb 28 06:01:57 PM PST 24
Peak memory 206228 kb
Host smart-441b2b4e-5ff6-421f-885f-219a9fe6e98c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244897790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1244897790
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1947714985
Short name T160
Test name
Test status
Simulation time 39358974 ps
CPU time 0.83 seconds
Started Feb 28 06:01:56 PM PST 24
Finished Feb 28 06:01:57 PM PST 24
Peak memory 215120 kb
Host smart-1b59cccf-eb8d-4572-a825-410daad1ed3f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947714985 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1947714985
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1350186707
Short name T162
Test name
Test status
Simulation time 33115521 ps
CPU time 1.22 seconds
Started Feb 28 06:01:54 PM PST 24
Finished Feb 28 06:01:56 PM PST 24
Peak memory 217192 kb
Host smart-950029ff-16a6-46e0-8d31-723beab05993
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350186707 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1350186707
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2456793046
Short name T631
Test name
Test status
Simulation time 22575685 ps
CPU time 1.06 seconds
Started Feb 28 06:01:53 PM PST 24
Finished Feb 28 06:01:54 PM PST 24
Peak memory 217320 kb
Host smart-26f0667f-25a8-4e3e-9b9c-12657d6f7826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456793046 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2456793046
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.240035323
Short name T691
Test name
Test status
Simulation time 39635347 ps
CPU time 1.16 seconds
Started Feb 28 06:01:56 PM PST 24
Finished Feb 28 06:01:58 PM PST 24
Peak memory 216096 kb
Host smart-aba90c56-ce28-4255-b545-5d59e7c02682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240035323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.240035323
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.4172128867
Short name T298
Test name
Test status
Simulation time 45141000 ps
CPU time 0.95 seconds
Started Feb 28 06:02:03 PM PST 24
Finished Feb 28 06:02:05 PM PST 24
Peak memory 215104 kb
Host smart-b838badf-f94a-4bff-8e59-43b192d81aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172128867 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.4172128867
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1298617213
Short name T718
Test name
Test status
Simulation time 17138023 ps
CPU time 1.02 seconds
Started Feb 28 06:02:05 PM PST 24
Finished Feb 28 06:02:07 PM PST 24
Peak memory 214688 kb
Host smart-dd547407-64bc-447a-8c8c-0b165ff6c599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298617213 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1298617213
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.481255069
Short name T368
Test name
Test status
Simulation time 76535359 ps
CPU time 1.86 seconds
Started Feb 28 06:01:58 PM PST 24
Finished Feb 28 06:02:00 PM PST 24
Peak memory 217376 kb
Host smart-cca0bd38-ab2e-4c29-8264-3f60efdf2561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481255069 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.481255069
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1028586313
Short name T803
Test name
Test status
Simulation time 21504777809 ps
CPU time 348.28 seconds
Started Feb 28 06:02:05 PM PST 24
Finished Feb 28 06:07:54 PM PST 24
Peak memory 222380 kb
Host smart-91db842d-c7e5-4e66-80b5-0cf6f4951f64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028586313 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1028586313
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1123593926
Short name T741
Test name
Test status
Simulation time 78820624 ps
CPU time 1.31 seconds
Started Feb 28 06:02:05 PM PST 24
Finished Feb 28 06:02:07 PM PST 24
Peak memory 215020 kb
Host smart-ad025a7a-ad84-4897-85d2-40acee573216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123593926 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1123593926
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2592506016
Short name T788
Test name
Test status
Simulation time 10623980 ps
CPU time 0.81 seconds
Started Feb 28 06:01:58 PM PST 24
Finished Feb 28 06:01:59 PM PST 24
Peak memory 205140 kb
Host smart-4047256f-706b-498d-aa23-024282bf862a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592506016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2592506016
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3769950528
Short name T680
Test name
Test status
Simulation time 45250973 ps
CPU time 0.91 seconds
Started Feb 28 06:02:05 PM PST 24
Finished Feb 28 06:02:06 PM PST 24
Peak memory 215208 kb
Host smart-3859fc55-7d02-47ab-8e73-880ad0db8a50
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769950528 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3769950528
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_err.1341971904
Short name T91
Test name
Test status
Simulation time 36906585 ps
CPU time 1.08 seconds
Started Feb 28 06:01:56 PM PST 24
Finished Feb 28 06:01:58 PM PST 24
Peak memory 229112 kb
Host smart-01314f47-1b45-493f-baf8-37d932bead4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341971904 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1341971904
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.3044238286
Short name T363
Test name
Test status
Simulation time 69435695 ps
CPU time 1.42 seconds
Started Feb 28 06:01:58 PM PST 24
Finished Feb 28 06:02:00 PM PST 24
Peak memory 216096 kb
Host smart-b67699e1-3795-4df6-b0ac-995fcf98dbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044238286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3044238286
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3138535502
Short name T538
Test name
Test status
Simulation time 41495349 ps
CPU time 0.91 seconds
Started Feb 28 06:01:56 PM PST 24
Finished Feb 28 06:01:58 PM PST 24
Peak memory 214732 kb
Host smart-55d2783f-b54b-4255-8861-6e53caaa0782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138535502 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3138535502
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.471322582
Short name T300
Test name
Test status
Simulation time 30820663 ps
CPU time 0.91 seconds
Started Feb 28 06:01:56 PM PST 24
Finished Feb 28 06:01:58 PM PST 24
Peak memory 214720 kb
Host smart-cb6af09a-5fdc-4a35-a5ef-b27e561eab60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471322582 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.471322582
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2790474256
Short name T329
Test name
Test status
Simulation time 213843162 ps
CPU time 4.6 seconds
Started Feb 28 06:01:53 PM PST 24
Finished Feb 28 06:01:58 PM PST 24
Peak memory 214728 kb
Host smart-d8244a24-a4ec-49d9-93c8-2c630c72b19b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790474256 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2790474256
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1248995467
Short name T511
Test name
Test status
Simulation time 187492690737 ps
CPU time 2384.06 seconds
Started Feb 28 06:01:58 PM PST 24
Finished Feb 28 06:41:43 PM PST 24
Peak memory 231008 kb
Host smart-6c61ae82-e099-4632-9a1e-6639c1e526d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248995467 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1248995467
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3128011980
Short name T544
Test name
Test status
Simulation time 41381357 ps
CPU time 1.16 seconds
Started Feb 28 06:01:57 PM PST 24
Finished Feb 28 06:01:58 PM PST 24
Peak memory 215076 kb
Host smart-2457776d-0d64-402b-ae3f-f54b12e09e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128011980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3128011980
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2942782288
Short name T609
Test name
Test status
Simulation time 36622198 ps
CPU time 1 seconds
Started Feb 28 06:02:05 PM PST 24
Finished Feb 28 06:02:06 PM PST 24
Peak memory 205420 kb
Host smart-84d1030e-d242-45fc-8b8d-6aec9a7e81b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942782288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2942782288
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3182256721
Short name T115
Test name
Test status
Simulation time 10320691 ps
CPU time 0.85 seconds
Started Feb 28 06:01:58 PM PST 24
Finished Feb 28 06:01:59 PM PST 24
Peak memory 215220 kb
Host smart-607b5a5a-3a96-49b4-9eee-fc0f2518f8c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182256721 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3182256721
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2283600258
Short name T606
Test name
Test status
Simulation time 61559767 ps
CPU time 1.21 seconds
Started Feb 28 06:02:00 PM PST 24
Finished Feb 28 06:02:01 PM PST 24
Peak memory 215824 kb
Host smart-43d90d0c-aa3c-45db-9ebd-addb15b9a1d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283600258 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2283600258
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2752483079
Short name T69
Test name
Test status
Simulation time 36189924 ps
CPU time 1.11 seconds
Started Feb 28 06:01:57 PM PST 24
Finished Feb 28 06:01:59 PM PST 24
Peak memory 216020 kb
Host smart-dd315a1f-8192-45da-b734-c91257715637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752483079 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2752483079
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3214391
Short name T288
Test name
Test status
Simulation time 171501660 ps
CPU time 3.56 seconds
Started Feb 28 06:02:00 PM PST 24
Finished Feb 28 06:02:04 PM PST 24
Peak memory 218968 kb
Host smart-6986fb18-bb46-4254-b461-125cc00f2a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3214391
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.532458540
Short name T830
Test name
Test status
Simulation time 28400999 ps
CPU time 1.06 seconds
Started Feb 28 06:01:59 PM PST 24
Finished Feb 28 06:02:00 PM PST 24
Peak memory 222604 kb
Host smart-2509091c-d106-4110-9167-64729ee4ccbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532458540 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.532458540
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.194250905
Short name T514
Test name
Test status
Simulation time 44191014 ps
CPU time 0.92 seconds
Started Feb 28 06:01:59 PM PST 24
Finished Feb 28 06:02:00 PM PST 24
Peak memory 214708 kb
Host smart-a366af7f-4151-4dbf-82d9-18cdbd5c0c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194250905 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.194250905
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2482863236
Short name T419
Test name
Test status
Simulation time 679373404 ps
CPU time 3.57 seconds
Started Feb 28 06:01:59 PM PST 24
Finished Feb 28 06:02:03 PM PST 24
Peak memory 214788 kb
Host smart-2ca908da-26cf-48a3-b123-0272e927381a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482863236 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2482863236
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2441523190
Short name T159
Test name
Test status
Simulation time 33155613615 ps
CPU time 739 seconds
Started Feb 28 06:01:59 PM PST 24
Finished Feb 28 06:14:18 PM PST 24
Peak memory 220792 kb
Host smart-ddc1827b-63a9-4d80-aff6-0eac6e7c7e40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441523190 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2441523190
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2119540480
Short name T804
Test name
Test status
Simulation time 25794479 ps
CPU time 1.21 seconds
Started Feb 28 06:01:57 PM PST 24
Finished Feb 28 06:01:58 PM PST 24
Peak memory 215064 kb
Host smart-a91073c8-f8ec-42c1-910b-6758bb5c4340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119540480 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2119540480
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2828762532
Short name T379
Test name
Test status
Simulation time 22866360 ps
CPU time 0.86 seconds
Started Feb 28 06:02:04 PM PST 24
Finished Feb 28 06:02:06 PM PST 24
Peak memory 205076 kb
Host smart-598c5df9-336c-4f0b-8a83-5d8b9498c642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828762532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2828762532
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1110317868
Short name T164
Test name
Test status
Simulation time 13338654 ps
CPU time 0.93 seconds
Started Feb 28 06:02:03 PM PST 24
Finished Feb 28 06:02:04 PM PST 24
Peak memory 215320 kb
Host smart-d06f6733-95e1-45ed-9f51-60501a91759f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110317868 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1110317868
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.722597949
Short name T314
Test name
Test status
Simulation time 45539193 ps
CPU time 1.11 seconds
Started Feb 28 06:02:01 PM PST 24
Finished Feb 28 06:02:02 PM PST 24
Peak memory 217092 kb
Host smart-3ea56e5b-9142-4429-8266-642059c2d45b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722597949 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.722597949
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.995838108
Short name T481
Test name
Test status
Simulation time 19833039 ps
CPU time 1.17 seconds
Started Feb 28 06:02:05 PM PST 24
Finished Feb 28 06:02:06 PM PST 24
Peak memory 230576 kb
Host smart-1b3c9eab-a7cf-4118-805b-25fdc1ea0e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995838108 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.995838108
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.849603680
Short name T410
Test name
Test status
Simulation time 45066015 ps
CPU time 1.19 seconds
Started Feb 28 06:02:04 PM PST 24
Finished Feb 28 06:02:07 PM PST 24
Peak memory 216044 kb
Host smart-7181ae5a-99a2-46ee-8ca3-4be1f6f4036f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849603680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.849603680
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3201780917
Short name T400
Test name
Test status
Simulation time 39236379 ps
CPU time 0.88 seconds
Started Feb 28 06:02:05 PM PST 24
Finished Feb 28 06:02:06 PM PST 24
Peak memory 214568 kb
Host smart-dc3b3cb5-7367-48bb-af25-1201aaf7ad58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201780917 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3201780917
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1253642182
Short name T333
Test name
Test status
Simulation time 16496237 ps
CPU time 0.99 seconds
Started Feb 28 06:01:58 PM PST 24
Finished Feb 28 06:01:59 PM PST 24
Peak memory 214696 kb
Host smart-cbce0835-e54d-4435-9ca3-c976af8f4042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253642182 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1253642182
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.35887938
Short name T392
Test name
Test status
Simulation time 517575820 ps
CPU time 5.96 seconds
Started Feb 28 06:01:57 PM PST 24
Finished Feb 28 06:02:03 PM PST 24
Peak memory 217120 kb
Host smart-c4be90a6-e3ea-43ba-8877-580eaa4fd4bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35887938 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.35887938
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2788856938
Short name T565
Test name
Test status
Simulation time 33132890153 ps
CPU time 755.46 seconds
Started Feb 28 06:02:00 PM PST 24
Finished Feb 28 06:14:36 PM PST 24
Peak memory 217976 kb
Host smart-48f79510-7113-4341-ab9d-43e29f0ffd2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788856938 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2788856938
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2570856554
Short name T246
Test name
Test status
Simulation time 41073279 ps
CPU time 1.36 seconds
Started Feb 28 06:02:03 PM PST 24
Finished Feb 28 06:02:05 PM PST 24
Peak memory 215164 kb
Host smart-b2b3cd5c-9c34-45f0-8636-17b3e37bf0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570856554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2570856554
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.705793490
Short name T810
Test name
Test status
Simulation time 28276535 ps
CPU time 0.97 seconds
Started Feb 28 06:02:02 PM PST 24
Finished Feb 28 06:02:03 PM PST 24
Peak memory 205900 kb
Host smart-596ac0ac-1fcf-45f4-94c3-ea2d7531bb16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705793490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.705793490
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1342576785
Short name T181
Test name
Test status
Simulation time 13310961 ps
CPU time 0.98 seconds
Started Feb 28 06:02:05 PM PST 24
Finished Feb 28 06:02:07 PM PST 24
Peak memory 215100 kb
Host smart-0fad9052-d0b8-483b-b650-9122c63bd39b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342576785 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1342576785
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3740519907
Short name T94
Test name
Test status
Simulation time 41927585 ps
CPU time 1.27 seconds
Started Feb 28 06:02:04 PM PST 24
Finished Feb 28 06:02:06 PM PST 24
Peak memory 215896 kb
Host smart-f3a7ac8c-9273-4081-a14a-78cbf5126025
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740519907 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3740519907
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3522961495
Short name T374
Test name
Test status
Simulation time 23885603 ps
CPU time 1.13 seconds
Started Feb 28 06:02:04 PM PST 24
Finished Feb 28 06:02:06 PM PST 24
Peak memory 222536 kb
Host smart-411b3d6d-ff92-40f1-948e-6dd79a6e3a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522961495 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3522961495
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3426375073
Short name T649
Test name
Test status
Simulation time 124207354 ps
CPU time 1.14 seconds
Started Feb 28 06:02:05 PM PST 24
Finished Feb 28 06:02:06 PM PST 24
Peak memory 216056 kb
Host smart-19922589-4f71-4fcd-8081-03562513e871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426375073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3426375073
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2433328336
Short name T62
Test name
Test status
Simulation time 23340148 ps
CPU time 0.93 seconds
Started Feb 28 06:02:08 PM PST 24
Finished Feb 28 06:02:09 PM PST 24
Peak memory 215172 kb
Host smart-08cdf538-65a4-485b-ac5a-5079a17762fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433328336 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2433328336
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1586466529
Short name T436
Test name
Test status
Simulation time 17979337 ps
CPU time 0.95 seconds
Started Feb 28 06:02:03 PM PST 24
Finished Feb 28 06:02:04 PM PST 24
Peak memory 214732 kb
Host smart-1730dbf8-5678-4584-a28e-65c547126c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586466529 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1586466529
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2385351179
Short name T578
Test name
Test status
Simulation time 393263813 ps
CPU time 7.75 seconds
Started Feb 28 06:02:03 PM PST 24
Finished Feb 28 06:02:11 PM PST 24
Peak memory 218724 kb
Host smart-0995f9cd-9e2d-4915-a72d-dda07e18c499
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385351179 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2385351179
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_alert.957513452
Short name T252
Test name
Test status
Simulation time 48988166 ps
CPU time 1.26 seconds
Started Feb 28 06:00:12 PM PST 24
Finished Feb 28 06:00:13 PM PST 24
Peak memory 215008 kb
Host smart-44a32d34-767c-42c1-9728-c7b573c76c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957513452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.957513452
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.321757162
Short name T672
Test name
Test status
Simulation time 98833113 ps
CPU time 1.02 seconds
Started Feb 28 06:00:12 PM PST 24
Finished Feb 28 06:00:13 PM PST 24
Peak memory 206240 kb
Host smart-c438af2a-71a1-46f9-a0f5-db8dff0b13e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321757162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.321757162
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.4136833643
Short name T124
Test name
Test status
Simulation time 29107308 ps
CPU time 0.86 seconds
Started Feb 28 06:00:11 PM PST 24
Finished Feb 28 06:00:12 PM PST 24
Peak memory 215156 kb
Host smart-503457a5-97fb-495a-a020-f3ac854accdb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136833643 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.4136833643
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3943109469
Short name T10
Test name
Test status
Simulation time 31224174 ps
CPU time 1.06 seconds
Started Feb 28 06:00:11 PM PST 24
Finished Feb 28 06:00:12 PM PST 24
Peak memory 217140 kb
Host smart-86fa9ce9-8a95-46f4-8951-22cd7f87613b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943109469 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3943109469
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.634157457
Short name T122
Test name
Test status
Simulation time 22712656 ps
CPU time 0.95 seconds
Started Feb 28 06:00:12 PM PST 24
Finished Feb 28 06:00:13 PM PST 24
Peak memory 217224 kb
Host smart-b1eeb058-cebb-4e82-b3e4-24522df2438a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634157457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.634157457
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1620908176
Short name T467
Test name
Test status
Simulation time 101948854 ps
CPU time 1.75 seconds
Started Feb 28 06:00:12 PM PST 24
Finished Feb 28 06:00:14 PM PST 24
Peak memory 219132 kb
Host smart-00cf953a-ecc0-41c9-91b1-789d822c0c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620908176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1620908176
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1478883940
Short name T134
Test name
Test status
Simulation time 28911285 ps
CPU time 1.12 seconds
Started Feb 28 06:00:10 PM PST 24
Finished Feb 28 06:00:11 PM PST 24
Peak memory 215212 kb
Host smart-a1cf4b97-ac6e-495c-a264-b286f6c0c612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478883940 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1478883940
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.440869331
Short name T131
Test name
Test status
Simulation time 60532518 ps
CPU time 0.96 seconds
Started Feb 28 06:00:11 PM PST 24
Finished Feb 28 06:00:12 PM PST 24
Peak memory 206524 kb
Host smart-1e92ac4a-2922-44dd-8dc7-f07dc0b377b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440869331 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.440869331
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3544451448
Short name T661
Test name
Test status
Simulation time 29475722 ps
CPU time 0.94 seconds
Started Feb 28 06:00:11 PM PST 24
Finished Feb 28 06:00:12 PM PST 24
Peak memory 214784 kb
Host smart-c9e41af9-ad2a-44b0-8e02-8881dfc7a018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544451448 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3544451448
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3118271775
Short name T319
Test name
Test status
Simulation time 352935757 ps
CPU time 4.14 seconds
Started Feb 28 06:00:11 PM PST 24
Finished Feb 28 06:00:15 PM PST 24
Peak memory 215908 kb
Host smart-2cb452b6-51b5-4c0d-8626-6b00c826bef9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118271775 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3118271775
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.829919755
Short name T557
Test name
Test status
Simulation time 148830108283 ps
CPU time 1899.56 seconds
Started Feb 28 06:00:10 PM PST 24
Finished Feb 28 06:31:50 PM PST 24
Peak memory 227344 kb
Host smart-6d1be4ac-192e-409f-92dc-47d419288c14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829919755 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.829919755
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.3668762103
Short name T318
Test name
Test status
Simulation time 19158481 ps
CPU time 1.07 seconds
Started Feb 28 06:02:01 PM PST 24
Finished Feb 28 06:02:02 PM PST 24
Peak memory 217220 kb
Host smart-3f1134de-ae25-4822-8447-991c4cd1d232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668762103 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3668762103
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2499149036
Short name T273
Test name
Test status
Simulation time 45600246 ps
CPU time 1.5 seconds
Started Feb 28 06:02:02 PM PST 24
Finished Feb 28 06:02:04 PM PST 24
Peak memory 217408 kb
Host smart-379dc52e-dff2-4d06-a0d6-d195cc2ccc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499149036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2499149036
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.1598016485
Short name T105
Test name
Test status
Simulation time 27934594 ps
CPU time 0.82 seconds
Started Feb 28 06:02:00 PM PST 24
Finished Feb 28 06:02:01 PM PST 24
Peak memory 217104 kb
Host smart-ca7562ae-bfbe-45ac-8f05-b09b884cf606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598016485 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1598016485
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1695372365
Short name T433
Test name
Test status
Simulation time 49256118 ps
CPU time 1.91 seconds
Started Feb 28 06:02:01 PM PST 24
Finished Feb 28 06:02:03 PM PST 24
Peak memory 217288 kb
Host smart-9d5af7f6-ef8c-4839-be1a-b9c0ca1a1fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695372365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1695372365
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.1855998521
Short name T620
Test name
Test status
Simulation time 22040475 ps
CPU time 0.92 seconds
Started Feb 28 06:02:02 PM PST 24
Finished Feb 28 06:02:03 PM PST 24
Peak memory 216736 kb
Host smart-ac80a55f-3545-4e44-afa2-0615330a6fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855998521 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1855998521
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3883291773
Short name T734
Test name
Test status
Simulation time 64006787 ps
CPU time 1.29 seconds
Started Feb 28 06:02:00 PM PST 24
Finished Feb 28 06:02:02 PM PST 24
Peak memory 216020 kb
Host smart-4480ccbf-a6a5-4f92-af9f-e7137293b3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883291773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3883291773
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.2492925857
Short name T512
Test name
Test status
Simulation time 23908550 ps
CPU time 1.15 seconds
Started Feb 28 06:02:06 PM PST 24
Finished Feb 28 06:02:08 PM PST 24
Peak memory 222476 kb
Host smart-eac12672-88fa-48ad-b16a-20e71c7a0606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492925857 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2492925857
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3662731512
Short name T668
Test name
Test status
Simulation time 48099522 ps
CPU time 1.81 seconds
Started Feb 28 06:02:03 PM PST 24
Finished Feb 28 06:02:06 PM PST 24
Peak memory 217084 kb
Host smart-b025299e-4635-4891-87c2-93522d9a35f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662731512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3662731512
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.2856430121
Short name T583
Test name
Test status
Simulation time 71196090 ps
CPU time 0.81 seconds
Started Feb 28 06:02:02 PM PST 24
Finished Feb 28 06:02:03 PM PST 24
Peak memory 217056 kb
Host smart-26b16397-b325-4c96-9848-8680afa4d0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856430121 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2856430121
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.180888828
Short name T805
Test name
Test status
Simulation time 116825915 ps
CPU time 1.23 seconds
Started Feb 28 06:02:02 PM PST 24
Finished Feb 28 06:02:03 PM PST 24
Peak memory 217724 kb
Host smart-f91fa86a-2cc9-4c0a-9b46-e0802a9d7d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180888828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.180888828
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.2659064472
Short name T84
Test name
Test status
Simulation time 179968693 ps
CPU time 1.07 seconds
Started Feb 28 06:02:06 PM PST 24
Finished Feb 28 06:02:07 PM PST 24
Peak memory 230672 kb
Host smart-7fd2fc81-2c56-4599-acd7-a6e4ebf3367f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659064472 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2659064472
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3171975371
Short name T508
Test name
Test status
Simulation time 45096712 ps
CPU time 1.42 seconds
Started Feb 28 06:02:03 PM PST 24
Finished Feb 28 06:02:04 PM PST 24
Peak memory 218184 kb
Host smart-bcafb2c7-d84a-4bb5-ac9f-00abe5223149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171975371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3171975371
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.1755511779
Short name T102
Test name
Test status
Simulation time 85263902 ps
CPU time 0.93 seconds
Started Feb 28 06:02:05 PM PST 24
Finished Feb 28 06:02:07 PM PST 24
Peak memory 230476 kb
Host smart-3fd20484-9eb4-46dd-a463-5ead69535613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755511779 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1755511779
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.612585587
Short name T577
Test name
Test status
Simulation time 63963177 ps
CPU time 2.81 seconds
Started Feb 28 06:02:05 PM PST 24
Finished Feb 28 06:02:09 PM PST 24
Peak memory 216248 kb
Host smart-aabf7612-3f9b-4251-9204-43d759535dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612585587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.612585587
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.1187252755
Short name T398
Test name
Test status
Simulation time 37644172 ps
CPU time 1.09 seconds
Started Feb 28 06:02:06 PM PST 24
Finished Feb 28 06:02:08 PM PST 24
Peak memory 216272 kb
Host smart-f3b3544b-efa6-4d52-8cc7-77193ef6ca3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187252755 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1187252755
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.922157017
Short name T254
Test name
Test status
Simulation time 56564256 ps
CPU time 2.15 seconds
Started Feb 28 06:02:03 PM PST 24
Finished Feb 28 06:02:06 PM PST 24
Peak memory 216404 kb
Host smart-18122604-d123-4758-843b-3c53c883c90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922157017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.922157017
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.2714611403
Short name T476
Test name
Test status
Simulation time 24247164 ps
CPU time 1.21 seconds
Started Feb 28 06:02:04 PM PST 24
Finished Feb 28 06:02:06 PM PST 24
Peak memory 218552 kb
Host smart-b8d8e752-e8c3-4268-985c-b26ab3903970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714611403 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2714611403
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/59.edn_err.271279667
Short name T81
Test name
Test status
Simulation time 31155359 ps
CPU time 1.05 seconds
Started Feb 28 06:02:04 PM PST 24
Finished Feb 28 06:02:05 PM PST 24
Peak memory 219128 kb
Host smart-4158104c-dfcc-4922-be13-8e0d2e2c9e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271279667 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.271279667
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.4067620144
Short name T757
Test name
Test status
Simulation time 45958636 ps
CPU time 1.56 seconds
Started Feb 28 06:02:07 PM PST 24
Finished Feb 28 06:02:09 PM PST 24
Peak memory 218316 kb
Host smart-3e2e9fc2-1029-47a0-9b66-67378aa22951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067620144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.4067620144
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.4140318619
Short name T247
Test name
Test status
Simulation time 30028464 ps
CPU time 1.3 seconds
Started Feb 28 06:00:15 PM PST 24
Finished Feb 28 06:00:17 PM PST 24
Peak memory 215016 kb
Host smart-8cf7a90f-5228-4ca2-9cc0-59f6668fd0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140318619 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.4140318619
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.990050692
Short name T330
Test name
Test status
Simulation time 104322292 ps
CPU time 0.88 seconds
Started Feb 28 06:00:16 PM PST 24
Finished Feb 28 06:00:17 PM PST 24
Peak memory 206276 kb
Host smart-607e51c3-9388-44f2-9680-64b23447b8f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990050692 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.990050692
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3989581339
Short name T652
Test name
Test status
Simulation time 30813050 ps
CPU time 0.83 seconds
Started Feb 28 06:00:14 PM PST 24
Finished Feb 28 06:00:15 PM PST 24
Peak memory 215164 kb
Host smart-17c94390-29a6-462a-8bb8-451971f614eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989581339 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3989581339
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_err.2481308821
Short name T85
Test name
Test status
Simulation time 47432556 ps
CPU time 0.96 seconds
Started Feb 28 06:00:17 PM PST 24
Finished Feb 28 06:00:18 PM PST 24
Peak memory 217388 kb
Host smart-c347bb58-c4e5-433d-b275-731451af0186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481308821 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2481308821
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.908725181
Short name T798
Test name
Test status
Simulation time 62399467 ps
CPU time 2.25 seconds
Started Feb 28 06:00:17 PM PST 24
Finished Feb 28 06:00:19 PM PST 24
Peak memory 217184 kb
Host smart-44a38342-5587-481d-987a-d42af489f1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908725181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.908725181
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1096968584
Short name T353
Test name
Test status
Simulation time 95142540 ps
CPU time 0.87 seconds
Started Feb 28 06:00:14 PM PST 24
Finished Feb 28 06:00:15 PM PST 24
Peak memory 214672 kb
Host smart-aa2ae66e-ff40-46fc-aa8d-93cfcf0b2bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096968584 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1096968584
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.3736616705
Short name T761
Test name
Test status
Simulation time 17603873 ps
CPU time 0.99 seconds
Started Feb 28 06:00:11 PM PST 24
Finished Feb 28 06:00:13 PM PST 24
Peak memory 206488 kb
Host smart-8941d7bd-c18b-4522-afb7-f818b17f4462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736616705 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3736616705
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.363877254
Short name T303
Test name
Test status
Simulation time 19579841 ps
CPU time 1.01 seconds
Started Feb 28 06:00:13 PM PST 24
Finished Feb 28 06:00:14 PM PST 24
Peak memory 214716 kb
Host smart-8eda4c9c-c04a-4fcc-ad58-2dac15f9cab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363877254 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.363877254
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1896937473
Short name T697
Test name
Test status
Simulation time 37670926 ps
CPU time 1.24 seconds
Started Feb 28 06:00:16 PM PST 24
Finished Feb 28 06:00:17 PM PST 24
Peak memory 206500 kb
Host smart-3ca9066e-7a10-4cf8-8fb8-a55bb2171a8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896937473 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1896937473
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3863781503
Short name T27
Test name
Test status
Simulation time 78679195928 ps
CPU time 1528.27 seconds
Started Feb 28 06:00:15 PM PST 24
Finished Feb 28 06:25:44 PM PST 24
Peak memory 225076 kb
Host smart-887af8ac-39f5-40f5-bd9f-dfefebcb5457
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863781503 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3863781503
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.4139370854
Short name T526
Test name
Test status
Simulation time 19472890 ps
CPU time 1.02 seconds
Started Feb 28 06:02:04 PM PST 24
Finished Feb 28 06:02:05 PM PST 24
Peak memory 217264 kb
Host smart-df7858af-34ec-4cd0-bc30-0f72eea037af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139370854 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.4139370854
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3548660741
Short name T52
Test name
Test status
Simulation time 57107374 ps
CPU time 1.2 seconds
Started Feb 28 06:02:02 PM PST 24
Finished Feb 28 06:02:04 PM PST 24
Peak memory 217136 kb
Host smart-84e2adf6-dc04-44eb-b08d-5873a10b343b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548660741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3548660741
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.386225938
Short name T7
Test name
Test status
Simulation time 20281390 ps
CPU time 1.14 seconds
Started Feb 28 06:02:04 PM PST 24
Finished Feb 28 06:02:06 PM PST 24
Peak memory 216144 kb
Host smart-77a1805a-8ae3-45b2-b0aa-e0c6f16924f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386225938 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.386225938
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3986891038
Short name T772
Test name
Test status
Simulation time 65242749 ps
CPU time 1.34 seconds
Started Feb 28 06:02:05 PM PST 24
Finished Feb 28 06:02:07 PM PST 24
Peak memory 215972 kb
Host smart-a224b12d-0da4-46f2-a49b-3fcc3f179209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986891038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3986891038
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.3179973121
Short name T426
Test name
Test status
Simulation time 18457534 ps
CPU time 1.04 seconds
Started Feb 28 06:02:04 PM PST 24
Finished Feb 28 06:02:06 PM PST 24
Peak memory 217600 kb
Host smart-2cec0a53-afd7-4961-a58b-366699190a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179973121 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3179973121
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3799357349
Short name T651
Test name
Test status
Simulation time 22786208 ps
CPU time 0.98 seconds
Started Feb 28 06:02:05 PM PST 24
Finished Feb 28 06:02:07 PM PST 24
Peak memory 215944 kb
Host smart-e8c8b653-49ea-4ed5-ad8a-425bc8c5674b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799357349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3799357349
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.4291593119
Short name T594
Test name
Test status
Simulation time 21869860 ps
CPU time 0.96 seconds
Started Feb 28 06:02:05 PM PST 24
Finished Feb 28 06:02:07 PM PST 24
Peak memory 217520 kb
Host smart-9a29e7b0-530b-41ee-ac27-7fa8a80921b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291593119 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.4291593119
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/64.edn_err.4062985073
Short name T634
Test name
Test status
Simulation time 19280359 ps
CPU time 1.21 seconds
Started Feb 28 06:02:07 PM PST 24
Finished Feb 28 06:02:09 PM PST 24
Peak memory 230592 kb
Host smart-c8c27794-b1f4-4d16-8429-9c03d595599c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062985073 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.4062985073
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1299483400
Short name T31
Test name
Test status
Simulation time 150776872 ps
CPU time 1.29 seconds
Started Feb 28 06:02:03 PM PST 24
Finished Feb 28 06:02:05 PM PST 24
Peak memory 215996 kb
Host smart-adca2045-855a-45a0-a368-b44ead0db6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299483400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1299483400
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_genbits.1921771505
Short name T416
Test name
Test status
Simulation time 45553630 ps
CPU time 1.15 seconds
Started Feb 28 06:02:11 PM PST 24
Finished Feb 28 06:02:13 PM PST 24
Peak memory 217036 kb
Host smart-18d33d75-c04e-4884-addd-6716fcf23be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921771505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1921771505
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.3785650687
Short name T522
Test name
Test status
Simulation time 20168641 ps
CPU time 0.97 seconds
Started Feb 28 06:02:07 PM PST 24
Finished Feb 28 06:02:09 PM PST 24
Peak memory 217456 kb
Host smart-582d0b82-a8fe-49a4-a647-2cc944b96d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785650687 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3785650687
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2248319900
Short name T257
Test name
Test status
Simulation time 26270985 ps
CPU time 1.2 seconds
Started Feb 28 06:02:07 PM PST 24
Finished Feb 28 06:02:09 PM PST 24
Peak memory 215884 kb
Host smart-4c04761d-bb80-488e-b105-2f1cf45fa344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248319900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2248319900
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.3700920211
Short name T112
Test name
Test status
Simulation time 28647893 ps
CPU time 1.1 seconds
Started Feb 28 06:02:09 PM PST 24
Finished Feb 28 06:02:10 PM PST 24
Peak memory 222424 kb
Host smart-70c6fc52-7418-4fa7-ac5f-a5e1af5e7748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700920211 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3700920211
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2113145085
Short name T532
Test name
Test status
Simulation time 34353968 ps
CPU time 1.05 seconds
Started Feb 28 06:02:08 PM PST 24
Finished Feb 28 06:02:09 PM PST 24
Peak memory 214720 kb
Host smart-3a672489-5816-4055-bb97-2243c804ed1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113145085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2113145085
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.3491665861
Short name T581
Test name
Test status
Simulation time 22577635 ps
CPU time 1.27 seconds
Started Feb 28 06:02:09 PM PST 24
Finished Feb 28 06:02:10 PM PST 24
Peak memory 222384 kb
Host smart-4596e37e-82df-4a36-9318-8c5676f58dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491665861 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3491665861
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.4279784289
Short name T534
Test name
Test status
Simulation time 31869343 ps
CPU time 1.31 seconds
Started Feb 28 06:02:08 PM PST 24
Finished Feb 28 06:02:09 PM PST 24
Peak memory 217320 kb
Host smart-7b9044b8-ff16-4de3-a3e5-97596fa4b4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279784289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.4279784289
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.3162875493
Short name T727
Test name
Test status
Simulation time 19031085 ps
CPU time 1.16 seconds
Started Feb 28 06:02:14 PM PST 24
Finished Feb 28 06:02:16 PM PST 24
Peak memory 222368 kb
Host smart-c87f36f9-81f6-4edc-ae5a-5ac9e9a6063c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162875493 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3162875493
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.3543939827
Short name T423
Test name
Test status
Simulation time 28259036 ps
CPU time 1.2 seconds
Started Feb 28 06:02:12 PM PST 24
Finished Feb 28 06:02:14 PM PST 24
Peak memory 215976 kb
Host smart-0e3f1581-29df-4619-9e55-8a0864c818fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543939827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3543939827
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3020640990
Short name T239
Test name
Test status
Simulation time 39031039 ps
CPU time 1.22 seconds
Started Feb 28 06:00:19 PM PST 24
Finished Feb 28 06:00:20 PM PST 24
Peak memory 215024 kb
Host smart-95ac3dae-b30a-4e24-9a34-99f310c437b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020640990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3020640990
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2651852463
Short name T43
Test name
Test status
Simulation time 40023907 ps
CPU time 0.87 seconds
Started Feb 28 06:00:25 PM PST 24
Finished Feb 28 06:00:26 PM PST 24
Peak memory 206224 kb
Host smart-75d31bc3-c023-4523-9707-cb8e8519f02f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651852463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2651852463
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3655502399
Short name T770
Test name
Test status
Simulation time 13808379 ps
CPU time 0.96 seconds
Started Feb 28 06:00:20 PM PST 24
Finished Feb 28 06:00:21 PM PST 24
Peak memory 215016 kb
Host smart-874e256a-b564-4de4-82db-51b4f45f0025
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655502399 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3655502399
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.4167316863
Short name T73
Test name
Test status
Simulation time 36145617 ps
CPU time 1.42 seconds
Started Feb 28 06:00:25 PM PST 24
Finished Feb 28 06:00:27 PM PST 24
Peak memory 215856 kb
Host smart-bf5884db-d42e-4a82-8ce4-cb17ed8e4eff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167316863 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.4167316863
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3514500751
Short name T65
Test name
Test status
Simulation time 19623459 ps
CPU time 1.08 seconds
Started Feb 28 06:00:24 PM PST 24
Finished Feb 28 06:00:25 PM PST 24
Peak memory 217352 kb
Host smart-1c36bf85-48d5-404d-8748-e1b8bfeb62b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514500751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3514500751
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_regwen.863020141
Short name T240
Test name
Test status
Simulation time 44101751 ps
CPU time 0.89 seconds
Started Feb 28 06:00:15 PM PST 24
Finished Feb 28 06:00:16 PM PST 24
Peak memory 206500 kb
Host smart-6525fe78-be83-4219-9e7f-49167cb6fdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863020141 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.863020141
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.4259491096
Short name T301
Test name
Test status
Simulation time 60356767 ps
CPU time 0.94 seconds
Started Feb 28 06:00:16 PM PST 24
Finished Feb 28 06:00:17 PM PST 24
Peak memory 214784 kb
Host smart-330a1671-3367-4de9-a65b-7db3d9c7c39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259491096 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.4259491096
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.4116566406
Short name T454
Test name
Test status
Simulation time 623535513 ps
CPU time 7 seconds
Started Feb 28 06:00:18 PM PST 24
Finished Feb 28 06:00:26 PM PST 24
Peak memory 217296 kb
Host smart-ab8189cb-c9f9-42f8-9b6b-7782d815ad49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116566406 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.4116566406
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2044113897
Short name T480
Test name
Test status
Simulation time 39232720003 ps
CPU time 265.12 seconds
Started Feb 28 06:00:20 PM PST 24
Finished Feb 28 06:04:45 PM PST 24
Peak memory 217876 kb
Host smart-2a53d603-e5a2-41cf-8c3b-423765c4aa48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044113897 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2044113897
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.1999397684
Short name T78
Test name
Test status
Simulation time 39987584 ps
CPU time 0.94 seconds
Started Feb 28 06:02:09 PM PST 24
Finished Feb 28 06:02:10 PM PST 24
Peak memory 218548 kb
Host smart-cd8e50ca-b302-4a43-a06e-813253be9757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999397684 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1999397684
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3678197484
Short name T284
Test name
Test status
Simulation time 33005056 ps
CPU time 1.26 seconds
Started Feb 28 06:02:08 PM PST 24
Finished Feb 28 06:02:09 PM PST 24
Peak memory 215996 kb
Host smart-fa331ba0-1d0d-40ce-98e3-72f173e20fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678197484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3678197484
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.1288712944
Short name T796
Test name
Test status
Simulation time 23319257 ps
CPU time 0.93 seconds
Started Feb 28 06:02:08 PM PST 24
Finished Feb 28 06:02:09 PM PST 24
Peak memory 217392 kb
Host smart-8a3eaaa6-62be-4af0-a4a6-6009653ff8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288712944 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1288712944
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1799278318
Short name T736
Test name
Test status
Simulation time 172886241 ps
CPU time 3.07 seconds
Started Feb 28 06:02:08 PM PST 24
Finished Feb 28 06:02:11 PM PST 24
Peak memory 217352 kb
Host smart-b806aef7-823b-4987-ac38-c696b13359c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799278318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1799278318
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.2675244244
Short name T51
Test name
Test status
Simulation time 81044285 ps
CPU time 1.16 seconds
Started Feb 28 06:02:13 PM PST 24
Finished Feb 28 06:02:15 PM PST 24
Peak memory 223416 kb
Host smart-48b087fd-9910-4276-b132-2d36c14d946c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675244244 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2675244244
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3612912748
Short name T346
Test name
Test status
Simulation time 49524148 ps
CPU time 1.45 seconds
Started Feb 28 06:02:09 PM PST 24
Finished Feb 28 06:02:10 PM PST 24
Peak memory 217008 kb
Host smart-9e592b86-968e-40a6-b49b-60024ba6abc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612912748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3612912748
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.1200786583
Short name T70
Test name
Test status
Simulation time 21896345 ps
CPU time 1.17 seconds
Started Feb 28 06:02:21 PM PST 24
Finished Feb 28 06:02:22 PM PST 24
Peak memory 228996 kb
Host smart-c3bdfce0-6bcc-439c-acc9-4c9c2f2049c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200786583 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1200786583
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/74.edn_err.920186232
Short name T560
Test name
Test status
Simulation time 23315903 ps
CPU time 0.98 seconds
Started Feb 28 06:02:10 PM PST 24
Finished Feb 28 06:02:12 PM PST 24
Peak memory 217400 kb
Host smart-2129f8b3-206c-4ec4-8d86-f458de3870c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920186232 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.920186232
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.247591914
Short name T296
Test name
Test status
Simulation time 73980002 ps
CPU time 2.85 seconds
Started Feb 28 06:02:11 PM PST 24
Finished Feb 28 06:02:15 PM PST 24
Peak memory 216076 kb
Host smart-23439a1c-94a0-423d-b572-e94fc06f9ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247591914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.247591914
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.2498629126
Short name T717
Test name
Test status
Simulation time 33357594 ps
CPU time 0.85 seconds
Started Feb 28 06:02:19 PM PST 24
Finished Feb 28 06:02:20 PM PST 24
Peak memory 217124 kb
Host smart-98bf7164-9485-4c0e-8916-9f9f8900d773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498629126 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2498629126
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.6354359
Short name T784
Test name
Test status
Simulation time 105069352 ps
CPU time 1.71 seconds
Started Feb 28 06:02:15 PM PST 24
Finished Feb 28 06:02:18 PM PST 24
Peak memory 218672 kb
Host smart-319d0975-c3d6-45c4-bb6e-206fa4da0b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6354359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.6354359
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.3526717021
Short name T351
Test name
Test status
Simulation time 28758830 ps
CPU time 0.98 seconds
Started Feb 28 06:02:10 PM PST 24
Finished Feb 28 06:02:11 PM PST 24
Peak memory 216256 kb
Host smart-ac952480-87ad-46b5-8ef7-38d330c81717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526717021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3526717021
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1572445326
Short name T622
Test name
Test status
Simulation time 49908941 ps
CPU time 1.1 seconds
Started Feb 28 06:02:13 PM PST 24
Finished Feb 28 06:02:14 PM PST 24
Peak memory 217036 kb
Host smart-5a3e437f-7571-4362-b222-65ffb9d08951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572445326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1572445326
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.1711791211
Short name T82
Test name
Test status
Simulation time 28427957 ps
CPU time 1.09 seconds
Started Feb 28 06:02:21 PM PST 24
Finished Feb 28 06:02:22 PM PST 24
Peak memory 229004 kb
Host smart-63ff414e-fa88-421c-bffd-89c2852ca000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711791211 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1711791211
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3527876763
Short name T531
Test name
Test status
Simulation time 39277552 ps
CPU time 1.09 seconds
Started Feb 28 06:02:13 PM PST 24
Finished Feb 28 06:02:15 PM PST 24
Peak memory 218080 kb
Host smart-fcf9ad8f-a2e9-430f-b262-1509f005e004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527876763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3527876763
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.1416949157
Short name T123
Test name
Test status
Simulation time 21178328 ps
CPU time 1 seconds
Started Feb 28 06:02:12 PM PST 24
Finished Feb 28 06:02:14 PM PST 24
Peak memory 230576 kb
Host smart-43454fe5-f692-4764-85cf-8324fa7ba0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416949157 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.1416949157
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1105725837
Short name T14
Test name
Test status
Simulation time 89412530 ps
CPU time 1.23 seconds
Started Feb 28 06:02:15 PM PST 24
Finished Feb 28 06:02:17 PM PST 24
Peak memory 217408 kb
Host smart-c0fbd53b-26d1-4780-b0f3-7867eb646a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105725837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1105725837
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.1115760970
Short name T157
Test name
Test status
Simulation time 20111014 ps
CPU time 0.97 seconds
Started Feb 28 06:02:13 PM PST 24
Finished Feb 28 06:02:15 PM PST 24
Peak memory 217660 kb
Host smart-f35fa4ec-894e-463a-8730-4be0782e8539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115760970 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1115760970
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2139629657
Short name T580
Test name
Test status
Simulation time 116946335 ps
CPU time 3.16 seconds
Started Feb 28 06:02:11 PM PST 24
Finished Feb 28 06:02:15 PM PST 24
Peak memory 217468 kb
Host smart-0053fa7d-dec1-4a21-b9f1-eca2df7230e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139629657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2139629657
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1224985400
Short name T127
Test name
Test status
Simulation time 154637618 ps
CPU time 1.37 seconds
Started Feb 28 06:00:23 PM PST 24
Finished Feb 28 06:00:25 PM PST 24
Peak memory 215172 kb
Host smart-b86f5dcd-83b6-41cf-af47-1baa115ba48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224985400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1224985400
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3610696408
Short name T603
Test name
Test status
Simulation time 42507453 ps
CPU time 0.83 seconds
Started Feb 28 06:00:24 PM PST 24
Finished Feb 28 06:00:25 PM PST 24
Peak memory 206012 kb
Host smart-4acf4d62-1f6f-44bd-85cf-5f93ffe08567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610696408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3610696408
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.110270440
Short name T99
Test name
Test status
Simulation time 12972153 ps
CPU time 0.91 seconds
Started Feb 28 06:00:23 PM PST 24
Finished Feb 28 06:00:24 PM PST 24
Peak memory 214988 kb
Host smart-3f8b9cae-d249-4746-b667-fd8d5810ee8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110270440 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.110270440
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_err.2761668773
Short name T615
Test name
Test status
Simulation time 29057481 ps
CPU time 0.82 seconds
Started Feb 28 06:00:21 PM PST 24
Finished Feb 28 06:00:22 PM PST 24
Peak memory 216820 kb
Host smart-7586999e-72a3-4018-8ea6-4522945278bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761668773 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2761668773
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.639651925
Short name T569
Test name
Test status
Simulation time 46359442 ps
CPU time 1.67 seconds
Started Feb 28 06:00:25 PM PST 24
Finished Feb 28 06:00:27 PM PST 24
Peak memory 216032 kb
Host smart-2893b06f-97a0-418a-9423-7f909783b491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639651925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.639651925
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.74937154
Short name T15
Test name
Test status
Simulation time 23540594 ps
CPU time 1.23 seconds
Started Feb 28 06:00:20 PM PST 24
Finished Feb 28 06:00:22 PM PST 24
Peak memory 222484 kb
Host smart-31bad378-d7db-45be-a1b2-ec3714b3eb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74937154 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.74937154
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_smoke.2517642584
Short name T640
Test name
Test status
Simulation time 25645529 ps
CPU time 0.85 seconds
Started Feb 28 06:00:17 PM PST 24
Finished Feb 28 06:00:18 PM PST 24
Peak memory 214796 kb
Host smart-7b9abcdf-a5b1-4335-a3aa-0d6e826c2fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517642584 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2517642584
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2004568428
Short name T760
Test name
Test status
Simulation time 285844681 ps
CPU time 5.76 seconds
Started Feb 28 06:00:23 PM PST 24
Finished Feb 28 06:00:29 PM PST 24
Peak memory 216136 kb
Host smart-d541ca2b-bd5e-4841-a275-ebfa0717aa30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004568428 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2004568428
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1252732338
Short name T366
Test name
Test status
Simulation time 40414472526 ps
CPU time 933.29 seconds
Started Feb 28 06:00:25 PM PST 24
Finished Feb 28 06:15:59 PM PST 24
Peak memory 217684 kb
Host smart-ea113245-a20d-404b-87bc-a22897ef5fc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252732338 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1252732338
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.3041578894
Short name T79
Test name
Test status
Simulation time 26225534 ps
CPU time 1 seconds
Started Feb 28 06:02:11 PM PST 24
Finished Feb 28 06:02:13 PM PST 24
Peak memory 218472 kb
Host smart-e6e80fb2-3498-4a6b-acf6-42484d984c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041578894 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3041578894
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1506264633
Short name T701
Test name
Test status
Simulation time 49861457 ps
CPU time 1.1 seconds
Started Feb 28 06:02:21 PM PST 24
Finished Feb 28 06:02:22 PM PST 24
Peak memory 215760 kb
Host smart-3c7fc7cc-5c71-47cc-ba57-606dd237e222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506264633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1506264633
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.605279122
Short name T740
Test name
Test status
Simulation time 21280563 ps
CPU time 0.95 seconds
Started Feb 28 06:02:16 PM PST 24
Finished Feb 28 06:02:18 PM PST 24
Peak memory 217304 kb
Host smart-1176781e-9e2b-4516-ac89-3aef3c013601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605279122 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.605279122
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1801060966
Short name T325
Test name
Test status
Simulation time 42588639 ps
CPU time 1.46 seconds
Started Feb 28 06:02:15 PM PST 24
Finished Feb 28 06:02:17 PM PST 24
Peak memory 216060 kb
Host smart-ba408793-36e7-4ecc-a4b6-287cd791abca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801060966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1801060966
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.1790006658
Short name T705
Test name
Test status
Simulation time 28820200 ps
CPU time 0.81 seconds
Started Feb 28 06:02:15 PM PST 24
Finished Feb 28 06:02:16 PM PST 24
Peak memory 216800 kb
Host smart-d7f31d3b-4b6f-4bdd-9cd8-c892a99b0872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790006658 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1790006658
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1605260240
Short name T825
Test name
Test status
Simulation time 47777997 ps
CPU time 1.19 seconds
Started Feb 28 06:02:16 PM PST 24
Finished Feb 28 06:02:18 PM PST 24
Peak memory 217332 kb
Host smart-a2d9508d-2f6b-40ac-b605-8c057f59d30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605260240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1605260240
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.3560161135
Short name T667
Test name
Test status
Simulation time 22079648 ps
CPU time 0.92 seconds
Started Feb 28 06:02:18 PM PST 24
Finished Feb 28 06:02:19 PM PST 24
Peak memory 217408 kb
Host smart-d5724eee-e8e7-4481-8216-806237626553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560161135 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3560161135
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.4109365993
Short name T715
Test name
Test status
Simulation time 129269022 ps
CPU time 1.16 seconds
Started Feb 28 06:02:16 PM PST 24
Finished Feb 28 06:02:17 PM PST 24
Peak memory 216264 kb
Host smart-17720e1a-6d4b-485e-9c6b-73d3ad3f105e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109365993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.4109365993
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.1145713002
Short name T8
Test name
Test status
Simulation time 19172091 ps
CPU time 1.22 seconds
Started Feb 28 06:02:15 PM PST 24
Finished Feb 28 06:02:16 PM PST 24
Peak memory 230636 kb
Host smart-db05c2c3-5f85-4771-a391-b87f1c4977c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145713002 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1145713002
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.4254247056
Short name T704
Test name
Test status
Simulation time 47394230 ps
CPU time 1.08 seconds
Started Feb 28 06:02:20 PM PST 24
Finished Feb 28 06:02:21 PM PST 24
Peak memory 217004 kb
Host smart-6f901707-6778-4053-8382-351a2b007105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254247056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.4254247056
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.2082992047
Short name T92
Test name
Test status
Simulation time 22166477 ps
CPU time 1.14 seconds
Started Feb 28 06:02:14 PM PST 24
Finished Feb 28 06:02:15 PM PST 24
Peak memory 216028 kb
Host smart-f355b3f1-68f4-4ef2-b814-0e2638dd59fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082992047 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2082992047
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3558711757
Short name T460
Test name
Test status
Simulation time 89169578 ps
CPU time 1.15 seconds
Started Feb 28 06:02:15 PM PST 24
Finished Feb 28 06:02:17 PM PST 24
Peak memory 216128 kb
Host smart-c418bd7b-b8e3-48a3-8714-9442febe7898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558711757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3558711757
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.432895707
Short name T118
Test name
Test status
Simulation time 19631693 ps
CPU time 1.17 seconds
Started Feb 28 06:02:16 PM PST 24
Finished Feb 28 06:02:18 PM PST 24
Peak memory 222444 kb
Host smart-dc9496da-a539-4763-ba80-e60f9d23a344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432895707 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.432895707
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.674287039
Short name T370
Test name
Test status
Simulation time 43815034 ps
CPU time 1.81 seconds
Started Feb 28 06:02:16 PM PST 24
Finished Feb 28 06:02:19 PM PST 24
Peak memory 217108 kb
Host smart-68189885-fcdd-4d45-bbcb-42fadaec6208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674287039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.674287039
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1132049736
Short name T177
Test name
Test status
Simulation time 31360910 ps
CPU time 1.25 seconds
Started Feb 28 06:02:13 PM PST 24
Finished Feb 28 06:02:15 PM PST 24
Peak memory 218432 kb
Host smart-f55416af-df3f-4f72-8d01-4377aa9ff0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132049736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1132049736
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2210592745
Short name T617
Test name
Test status
Simulation time 31460212 ps
CPU time 1.41 seconds
Started Feb 28 06:02:17 PM PST 24
Finished Feb 28 06:02:19 PM PST 24
Peak memory 217076 kb
Host smart-9a76f6d8-11a8-41c3-a6c3-631e5bf508cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210592745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2210592745
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.279767994
Short name T596
Test name
Test status
Simulation time 49122164 ps
CPU time 0.84 seconds
Started Feb 28 06:02:16 PM PST 24
Finished Feb 28 06:02:17 PM PST 24
Peak memory 216928 kb
Host smart-d53490a5-3b1b-44b9-bdef-21b7a5d868a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279767994 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.279767994
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1464028011
Short name T285
Test name
Test status
Simulation time 77705686 ps
CPU time 1.24 seconds
Started Feb 28 06:02:14 PM PST 24
Finished Feb 28 06:02:16 PM PST 24
Peak memory 217996 kb
Host smart-5f14e481-f824-44da-b64d-db334433b560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464028011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1464028011
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.2410063824
Short name T106
Test name
Test status
Simulation time 44648094 ps
CPU time 1.18 seconds
Started Feb 28 06:02:19 PM PST 24
Finished Feb 28 06:02:21 PM PST 24
Peak memory 218344 kb
Host smart-4e1d55df-c9b0-45c9-a25b-edfcfbed925d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410063824 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2410063824
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.97081510
Short name T12
Test name
Test status
Simulation time 65576142 ps
CPU time 1.27 seconds
Started Feb 28 06:02:15 PM PST 24
Finished Feb 28 06:02:17 PM PST 24
Peak memory 216244 kb
Host smart-fc4d0444-e997-4826-bf66-646b487dfc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97081510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.97081510
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3378280580
Short name T110
Test name
Test status
Simulation time 46265108 ps
CPU time 1.12 seconds
Started Feb 28 06:00:25 PM PST 24
Finished Feb 28 06:00:27 PM PST 24
Peak memory 214980 kb
Host smart-ef7002ea-e827-4be2-923d-63029918b502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378280580 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3378280580
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1934494086
Short name T430
Test name
Test status
Simulation time 12142917 ps
CPU time 0.88 seconds
Started Feb 28 06:00:25 PM PST 24
Finished Feb 28 06:00:26 PM PST 24
Peak memory 205168 kb
Host smart-3a811400-5da5-4f9b-bf83-63f17de72bc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934494086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1934494086
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.381312445
Short name T180
Test name
Test status
Simulation time 13335916 ps
CPU time 0.88 seconds
Started Feb 28 06:00:27 PM PST 24
Finished Feb 28 06:00:28 PM PST 24
Peak memory 215032 kb
Host smart-b728290b-1c4d-4e4b-ba51-845c5c5bacfc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381312445 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.381312445
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1088729264
Short name T93
Test name
Test status
Simulation time 35748827 ps
CPU time 1.23 seconds
Started Feb 28 06:00:26 PM PST 24
Finished Feb 28 06:00:27 PM PST 24
Peak memory 215848 kb
Host smart-6fe1ae22-26bd-4598-8430-d5019e0a2d4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088729264 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1088729264
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1328091460
Short name T593
Test name
Test status
Simulation time 21893164 ps
CPU time 0.91 seconds
Started Feb 28 06:00:27 PM PST 24
Finished Feb 28 06:00:28 PM PST 24
Peak memory 216888 kb
Host smart-48945777-fc25-49eb-9106-526a6e8b71ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328091460 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1328091460
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.3022177273
Short name T600
Test name
Test status
Simulation time 58881721 ps
CPU time 1.16 seconds
Started Feb 28 06:00:26 PM PST 24
Finished Feb 28 06:00:27 PM PST 24
Peak memory 215888 kb
Host smart-dde518e0-b7fa-46b0-9bac-ec936a24226c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022177273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3022177273
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2950334898
Short name T132
Test name
Test status
Simulation time 104813368 ps
CPU time 0.86 seconds
Started Feb 28 06:00:28 PM PST 24
Finished Feb 28 06:00:30 PM PST 24
Peak memory 214992 kb
Host smart-0bfb0c6d-7d64-4350-a1c5-8c716ab2f07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950334898 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2950334898
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3466197606
Short name T237
Test name
Test status
Simulation time 46252287 ps
CPU time 0.88 seconds
Started Feb 28 06:00:26 PM PST 24
Finished Feb 28 06:00:27 PM PST 24
Peak memory 206508 kb
Host smart-02377ee4-fe9b-4124-b77c-bd3290fb0515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466197606 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3466197606
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3032633981
Short name T340
Test name
Test status
Simulation time 27678022 ps
CPU time 0.95 seconds
Started Feb 28 06:00:23 PM PST 24
Finished Feb 28 06:00:24 PM PST 24
Peak memory 214712 kb
Host smart-c9f6f40e-1b96-463f-b0f6-268c05fd569d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032633981 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3032633981
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.4217079552
Short name T791
Test name
Test status
Simulation time 683137059 ps
CPU time 3.38 seconds
Started Feb 28 06:00:25 PM PST 24
Finished Feb 28 06:00:29 PM PST 24
Peak memory 215840 kb
Host smart-2d0c2938-4ce6-4760-bc69-7ac18decc7b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217079552 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.4217079552
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3748635869
Short name T395
Test name
Test status
Simulation time 90857518943 ps
CPU time 1132.49 seconds
Started Feb 28 06:00:25 PM PST 24
Finished Feb 28 06:19:18 PM PST 24
Peak memory 223304 kb
Host smart-e3036633-5cef-4485-9990-b4dd0f4fdfef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748635869 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3748635869
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.17752898
Short name T113
Test name
Test status
Simulation time 46793489 ps
CPU time 1.11 seconds
Started Feb 28 06:02:18 PM PST 24
Finished Feb 28 06:02:19 PM PST 24
Peak memory 218608 kb
Host smart-2f2d0d94-b2be-4df4-a59c-0c711a11096a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17752898 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.17752898
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.473198738
Short name T364
Test name
Test status
Simulation time 51681471 ps
CPU time 1.05 seconds
Started Feb 28 06:02:19 PM PST 24
Finished Feb 28 06:02:20 PM PST 24
Peak memory 215732 kb
Host smart-2ba0e348-6bb8-4ebd-bfb1-033c85f2a282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473198738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.473198738
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.3623160437
Short name T520
Test name
Test status
Simulation time 36192691 ps
CPU time 1.07 seconds
Started Feb 28 06:02:19 PM PST 24
Finished Feb 28 06:02:20 PM PST 24
Peak memory 218556 kb
Host smart-2c057221-8ab0-4983-b782-bcaaee148c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623160437 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3623160437
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.376032892
Short name T571
Test name
Test status
Simulation time 47233730 ps
CPU time 1.34 seconds
Started Feb 28 06:02:21 PM PST 24
Finished Feb 28 06:02:22 PM PST 24
Peak memory 216076 kb
Host smart-bdadf948-bdc2-491c-acf8-06509f508dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376032892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.376032892
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.4226514388
Short name T117
Test name
Test status
Simulation time 32050023 ps
CPU time 0.95 seconds
Started Feb 28 06:02:22 PM PST 24
Finished Feb 28 06:02:23 PM PST 24
Peak memory 222192 kb
Host smart-674ec326-4c97-46b4-a7de-01e7744da7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226514388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.4226514388
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.364257422
Short name T507
Test name
Test status
Simulation time 59071343 ps
CPU time 2.11 seconds
Started Feb 28 06:02:22 PM PST 24
Finished Feb 28 06:02:24 PM PST 24
Peak memory 218868 kb
Host smart-2b803413-7f7d-48a6-a118-92d2c7c43c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364257422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.364257422
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.2543917343
Short name T72
Test name
Test status
Simulation time 22519532 ps
CPU time 1.1 seconds
Started Feb 28 06:02:19 PM PST 24
Finished Feb 28 06:02:21 PM PST 24
Peak memory 218640 kb
Host smart-4dfb8d89-3bd5-4a6f-aa4a-a3b8a10b9f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543917343 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2543917343
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2243246394
Short name T758
Test name
Test status
Simulation time 79578051 ps
CPU time 1.37 seconds
Started Feb 28 06:02:19 PM PST 24
Finished Feb 28 06:02:20 PM PST 24
Peak memory 217688 kb
Host smart-6cd7963b-39d2-4418-99e8-5be9c60e15e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243246394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2243246394
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.3563861302
Short name T582
Test name
Test status
Simulation time 22090287 ps
CPU time 0.95 seconds
Started Feb 28 06:02:20 PM PST 24
Finished Feb 28 06:02:21 PM PST 24
Peak memory 217264 kb
Host smart-9fd1a7c2-d55a-4601-8b51-3ef6a57a7dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563861302 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3563861302
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.90641432
Short name T310
Test name
Test status
Simulation time 67389620 ps
CPU time 1.61 seconds
Started Feb 28 06:02:17 PM PST 24
Finished Feb 28 06:02:19 PM PST 24
Peak memory 217348 kb
Host smart-c3820ae0-804c-4fed-8c75-a69f8b85e3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90641432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.90641432
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.1446822519
Short name T670
Test name
Test status
Simulation time 45090131 ps
CPU time 0.93 seconds
Started Feb 28 06:02:22 PM PST 24
Finished Feb 28 06:02:23 PM PST 24
Peak memory 217460 kb
Host smart-092cdbab-b5b5-4652-bade-a2a4996e2c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446822519 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1446822519
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2931084828
Short name T418
Test name
Test status
Simulation time 28131395 ps
CPU time 1.26 seconds
Started Feb 28 06:02:18 PM PST 24
Finished Feb 28 06:02:20 PM PST 24
Peak memory 215848 kb
Host smart-63fac30c-90fa-49f4-9f40-d19bedd8ecb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931084828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2931084828
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.4196408538
Short name T50
Test name
Test status
Simulation time 18142687 ps
CPU time 1.1 seconds
Started Feb 28 06:02:17 PM PST 24
Finished Feb 28 06:02:18 PM PST 24
Peak memory 222344 kb
Host smart-0714b3bf-7a6b-4fec-b2c3-47331c5675d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196408538 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.4196408538
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2562574378
Short name T764
Test name
Test status
Simulation time 115007638 ps
CPU time 2.76 seconds
Started Feb 28 06:02:19 PM PST 24
Finished Feb 28 06:02:22 PM PST 24
Peak memory 216124 kb
Host smart-86554223-c91c-4f53-bd37-ecd042f9c2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562574378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2562574378
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.3241521952
Short name T96
Test name
Test status
Simulation time 35166399 ps
CPU time 0.89 seconds
Started Feb 28 06:02:22 PM PST 24
Finished Feb 28 06:02:23 PM PST 24
Peak memory 217088 kb
Host smart-c3368de7-4aa6-4646-9ea8-69fe3492ca9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241521952 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.3241521952
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.1781953319
Short name T275
Test name
Test status
Simulation time 72160275 ps
CPU time 1.87 seconds
Started Feb 28 06:02:20 PM PST 24
Finished Feb 28 06:02:22 PM PST 24
Peak memory 218832 kb
Host smart-d4934fb5-3a3e-433f-a107-5f6f4ebbc223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781953319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1781953319
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.2640755868
Short name T759
Test name
Test status
Simulation time 25100950 ps
CPU time 1.08 seconds
Started Feb 28 06:02:21 PM PST 24
Finished Feb 28 06:02:22 PM PST 24
Peak memory 230656 kb
Host smart-9fd518a1-25e3-4f5e-8e63-5d3ff3682596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640755868 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2640755868
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.519648631
Short name T707
Test name
Test status
Simulation time 97100403 ps
CPU time 1.29 seconds
Started Feb 28 06:02:23 PM PST 24
Finished Feb 28 06:02:25 PM PST 24
Peak memory 216004 kb
Host smart-65b156e7-35bb-4623-941e-0f298ed58963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519648631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.519648631
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.935779543
Short name T16
Test name
Test status
Simulation time 50024756 ps
CPU time 1 seconds
Started Feb 28 06:02:25 PM PST 24
Finished Feb 28 06:02:26 PM PST 24
Peak memory 230424 kb
Host smart-575349d0-48cb-4113-8e27-262a7b6c1d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935779543 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.935779543
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3141565371
Short name T23
Test name
Test status
Simulation time 37063576 ps
CPU time 1.28 seconds
Started Feb 28 06:02:21 PM PST 24
Finished Feb 28 06:02:22 PM PST 24
Peak memory 215876 kb
Host smart-2f3ba527-6727-45ec-9dc7-76eaaf63ec80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141565371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3141565371
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%