ASSERT | PROPERTIES | SEQUENCES | |
Total | 428 | 0 | 10 |
Category 0 | 428 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 428 | 0 | 10 |
Severity 0 | 428 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 428 | 100.00 |
Uncovered | 15 | 3.50 |
Success | 413 | 96.50 |
Failure | 0 | 0.00 |
Incomplete | 9 | 2.10 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep.DataOStableWhenPending_A | 0 | 0 | 209531609 | 189931548 | 0 | 805 | |
tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep.DataOStableWhenPending_A | 0 | 0 | 209531609 | 265476 | 0 | 805 | |
tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep.DataOStableWhenPending_A | 0 | 0 | 209531609 | 261911 | 0 | 805 | |
tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep.DataOStableWhenPending_A | 0 | 0 | 209531609 | 202743 | 0 | 805 | |
tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep.DataOStableWhenPending_A | 0 | 0 | 209531609 | 188402 | 0 | 805 | |
tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep.DataOStableWhenPending_A | 0 | 0 | 209531609 | 200973 | 0 | 805 | |
tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep.DataOStableWhenPending_A | 0 | 0 | 209531609 | 169853 | 0 | 805 | |
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb.RoundRobin_A | 0 | 0 | 209531609 | 0 | 0 | 805 | |
tb.dut.u_edn_core.u_prim_packer_fifo_cs.DataOStableWhenPending_A | 0 | 0 | 209531609 | 77801 | 0 | 805 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 210007681 | 374 | 374 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 210007681 | 56 | 56 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 210007681 | 58 | 58 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 210007681 | 37 | 37 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 210007681 | 7 | 7 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 210007681 | 30 | 30 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 210007681 | 22 | 22 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 210007681 | 2077 | 2077 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 210007681 | 3580 | 3580 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 210007681 | 60627 | 60627 | 906 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 210007681 | 374 | 374 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 210007681 | 56 | 56 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 210007681 | 58 | 58 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 210007681 | 37 | 37 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 210007681 | 7 | 7 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 210007681 | 30 | 30 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 210007681 | 22 | 22 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 210007681 | 2077 | 2077 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 210007681 | 3580 | 3580 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 210007681 | 60627 | 60627 | 906 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |