Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	145	1			T20	1		T36	1		T117	1
auto_req_mode	132	1			T8	1		T9	1		T10	1
sw_mode	2791	1			T1	22		T2	1		T28	11

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

299

1

T2

1

T8

1

T20

1

single

89

1

T29

1

T117

1

T270

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1318	1			T8	1		T20	1		T36	1
auto[2]	161	1			T161	20		T271	1		T272	1
auto[3]	307	1			T2	1		T155	31		T29	1
auto[4]	38	1			T30	1		T133	12		T273	2
auto[5]	70	1			T187	25		T189	29		T274	1
auto[6]	31	1			T1	22		T275	1		T276	1
auto[7]	1143	1			T28	11		T10	1		T22	42

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	94	1			T20	1		T36	1		T117	1
auto[1]	auto_req_mode	73	1			T8	1		T9	1		T130	1
auto[1]	sw_mode	1151	1			T37	1		T21	45		T158	1
auto[2]	boot_req_mode	6	1			T277	1		T278	1		T279	1
auto[2]	auto_req_mode	5	1			T280	1		T281	1		T260	1
auto[2]	sw_mode	150	1			T161	20		T271	1		T272	1
auto[3]	boot_req_mode	6	1			T174	1		T282	1		T283	1
auto[3]	auto_req_mode	6	1			T29	1		T173	1		T284	1
auto[3]	sw_mode	295	1			T2	1		T155	31		T253	1
auto[4]	boot_req_mode	1	1			T285	1		-	-		-	-
auto[4]	auto_req_mode	4	1			T286	1		T287	1		T288	1
auto[4]	sw_mode	33	1			T30	1		T133	12		T273	2
auto[5]	boot_req_mode	1	1			T289	1		-	-		-	-
auto[5]	auto_req_mode	1	1			T290	1		-	-		-	-
auto[5]	sw_mode	68	1			T187	25		T189	29		T274	1
auto[6]	boot_req_mode	3	1			T275	1		T276	1		T291	1
auto[6]	auto_req_mode	4	1			T292	1		T293	1		T294	1
auto[6]	sw_mode	24	1			T1	22		T295	1		T296	1
auto[7]	boot_req_mode	34	1			T178	1		T31	1		T179	1
auto[7]	auto_req_mode	39	1			T10	1		T23	1		T170	1
auto[7]	sw_mode	1070	1			T28	11		T22	42		T156	4